JP2025088548A - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
JP2025088548A
JP2025088548A JP2023203322A JP2023203322A JP2025088548A JP 2025088548 A JP2025088548 A JP 2025088548A JP 2023203322 A JP2023203322 A JP 2023203322A JP 2023203322 A JP2023203322 A JP 2023203322A JP 2025088548 A JP2025088548 A JP 2025088548A
Authority
JP
Japan
Prior art keywords
bridge
layer
wiring
electronic component
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023203322A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025088548A5 (https=
Inventor
敏央 野中
Toshinaka Nonaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rapidus Corp
Original Assignee
Rapidus Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rapidus Corp filed Critical Rapidus Corp
Priority to JP2023203322A priority Critical patent/JP2025088548A/ja
Priority to PCT/JP2024/039125 priority patent/WO2025115520A1/ja
Priority to TW113145289A priority patent/TW202545041A/zh
Publication of JP2025088548A publication Critical patent/JP2025088548A/ja
Publication of JP2025088548A5 publication Critical patent/JP2025088548A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2023203322A 2023-11-30 2023-11-30 電子装置 Pending JP2025088548A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2023203322A JP2025088548A (ja) 2023-11-30 2023-11-30 電子装置
PCT/JP2024/039125 WO2025115520A1 (ja) 2023-11-30 2024-11-01 電子装置
TW113145289A TW202545041A (zh) 2023-11-30 2024-11-25 電子裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2023203322A JP2025088548A (ja) 2023-11-30 2023-11-30 電子装置

Publications (2)

Publication Number Publication Date
JP2025088548A true JP2025088548A (ja) 2025-06-11
JP2025088548A5 JP2025088548A5 (https=) 2026-02-27

Family

ID=95897661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023203322A Pending JP2025088548A (ja) 2023-11-30 2023-11-30 電子装置

Country Status (3)

Country Link
JP (1) JP2025088548A (https=)
TW (1) TW202545041A (https=)
WO (1) WO2025115520A1 (https=)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022465A (ja) * 2012-07-13 2014-02-03 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2018523925A (ja) * 2015-08-21 2018-08-23 クアルコム，インコーポレイテッド リソエッチング可能層内にブリッジを備える集積デバイスパッケージ
CN113130464A (zh) * 2019-12-31 2021-07-16 力成科技股份有限公司 封装结构及其制造方法
JP2021153173A (ja) * 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジ電力供給のアーキテクチャおよびプロセス
JP2021532578A (ja) * 2018-07-24 2021-11-25 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation チップとパッケージ基板との間の電源接続を提供するチップ相互接続ブリッジを有するマルチチップ・パッケージ構造体
US20230207475A1 (en) * 2021-12-23 2023-06-29 Intel Corporation Hybrid bonded stacked memory with tsv as chiplet for package structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022465A (ja) * 2012-07-13 2014-02-03 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2018523925A (ja) * 2015-08-21 2018-08-23 クアルコム，インコーポレイテッド リソエッチング可能層内にブリッジを備える集積デバイスパッケージ
JP2021532578A (ja) * 2018-07-24 2021-11-25 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation チップとパッケージ基板との間の電源接続を提供するチップ相互接続ブリッジを有するマルチチップ・パッケージ構造体
CN113130464A (zh) * 2019-12-31 2021-07-16 力成科技股份有限公司 封装结构及其制造方法
JP2021153173A (ja) * 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジ電力供給のアーキテクチャおよびプロセス
US20230207475A1 (en) * 2021-12-23 2023-06-29 Intel Corporation Hybrid bonded stacked memory with tsv as chiplet for package structure

Also Published As

Publication number Publication date
TW202545041A (zh) 2025-11-16
WO2025115520A1 (ja) 2025-06-05

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