JP2024524391A - 接合層内にルーティング構造体を有する素子 - Google Patents

接合層内にルーティング構造体を有する素子 Download PDF

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JP2024524391A
JP2024524391A JP2023580542A JP2023580542A JP2024524391A JP 2024524391 A JP2024524391 A JP 2024524391A JP 2023580542 A JP2023580542 A JP 2023580542A JP 2023580542 A JP2023580542 A JP 2023580542A JP 2024524391 A JP2024524391 A JP 2024524391A
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contact pad
bonding
layer
bonding layer
routing
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JP2024524391A5 (https=
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ガイウス ギルマン ジュニア ファウンテン
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アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド
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    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
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    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
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    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
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    • H10W72/931—Shapes of bond pads
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    • H10W72/931—Shapes of bond pads
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W80/00—Direct bonding of chips, wafers or substrates
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    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
JP2023580542A 2021-06-30 2022-06-29 接合層内にルーティング構造体を有する素子 Pending JP2024524391A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163217046P 2021-06-30 2021-06-30
US63/217,046 2021-06-30
PCT/US2022/035559 WO2023278605A1 (en) 2021-06-30 2022-06-29 Element with routing structure in bonding layer

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JP2024524391A true JP2024524391A (ja) 2024-07-05
JP2024524391A5 JP2024524391A5 (https=) 2025-07-08

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US (1) US20230005850A1 (https=)
EP (1) EP4364194A4 (https=)
JP (1) JP2024524391A (https=)
KR (1) KR20240028356A (https=)
CN (1) CN117716488A (https=)
TW (1) TW202315012A (https=)
WO (1) WO2023278605A1 (https=)

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