JP2024520311A5 - - Google Patents

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Publication number
JP2024520311A5
JP2024520311A5 JP2023570344A JP2023570344A JP2024520311A5 JP 2024520311 A5 JP2024520311 A5 JP 2024520311A5 JP 2023570344 A JP2023570344 A JP 2023570344A JP 2023570344 A JP2023570344 A JP 2023570344A JP 2024520311 A5 JP2024520311 A5 JP 2024520311A5
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JP
Japan
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JP2023570344A
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Japanese (ja)
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JP2024520311A (ja
JP7789088B2 (ja
JPWO2022249077A5 (https=
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Priority claimed from US17/303,333 external-priority patent/US11735575B2/en
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Publication of JPWO2022249077A5 publication Critical patent/JPWO2022249077A5/ja
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JP2023570344A 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング Active JP7789088B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/303,333 US11735575B2 (en) 2021-05-27 2021-05-27 Bonding of bridge to multiple semiconductor chips
US17/303,333 2021-05-27
PCT/IB2022/054874 WO2022249077A1 (en) 2021-05-27 2022-05-25 Bonding of bridge to multiple semiconductor chips

Publications (4)

Publication Number Publication Date
JP2024520311A JP2024520311A (ja) 2024-05-24
JP2024520311A5 true JP2024520311A5 (https=) 2024-07-31
JPWO2022249077A5 JPWO2022249077A5 (https=) 2024-07-31
JP7789088B2 JP7789088B2 (ja) 2025-12-19

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ID=84194293

Family Applications (1)

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JP2023570344A Active JP7789088B2 (ja) 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング

Country Status (7)

Country Link
US (2) US11735575B2 (https=)
JP (1) JP7789088B2 (https=)
CN (1) CN117397025A (https=)
DE (1) DE112022001645B4 (https=)
GB (1) GB2622173A (https=)
TW (1) TWI824443B (https=)
WO (1) WO2022249077A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips
US12300660B2 (en) * 2022-01-27 2025-05-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a bonded semiconductor structure
KR102737071B1 (ko) * 2024-01-02 2024-12-03 엘지이노텍 주식회사 회로기판 및 이를 포함하는 반도체 패키지 기판
CN118156222B (zh) * 2024-05-13 2024-08-06 日月新半导体(威海)有限公司 一种半导体芯片的封装模块及其制备方法
WO2026059959A1 (en) * 2024-09-16 2026-03-19 Kulicke And Soffa Industries, Inc. Systems for bonding a semiconductor element to a substrate using reducing gas and related methods

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US6882546B2 (en) 2001-10-03 2005-04-19 Formfactor, Inc. Multiple die interconnect system
JP3872763B2 (ja) 2003-02-26 2007-01-24 東レエンジニアリング株式会社 ボンディング方法
US7348666B2 (en) 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
JP4265997B2 (ja) 2004-07-14 2009-05-20 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
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JP4484831B2 (ja) * 2006-03-02 2010-06-16 パナソニック株式会社 電子部品内蔵モジュールおよび電子部品内蔵モジュールの製造方法
JP5183028B2 (ja) 2006-03-02 2013-04-17 神港精機株式会社 固着材およびバンプ形成方法
JP4991495B2 (ja) * 2007-11-26 2012-08-01 東京エレクトロン株式会社 検査用保持部材及び検査用保持部材の製造方法
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP5645592B2 (ja) 2010-10-21 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101740483B1 (ko) 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9142532B2 (en) 2012-04-24 2015-09-22 Bondtech Co., Ltd. Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
WO2015023232A1 (en) 2013-08-14 2015-02-19 Orion Systems Integration Pte Ltd Apparatus And Method For Bonding A Plurality Of Semiconductor Chips Onto A Substrate
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TWI652778B (zh) 2016-01-27 2019-03-01 Amkor Technology, Inc. 半導體封裝以及其製造方法
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US10833051B2 (en) 2019-01-24 2020-11-10 International Business Machines Corporation Precision alignment of multi-chip high density interconnects
US10991635B2 (en) 2019-07-20 2021-04-27 International Business Machines Corporation Multiple chip bridge connector
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US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips

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