JPWO2022249077A5 - - Google Patents

Download PDF

Info

Publication number
JPWO2022249077A5
JPWO2022249077A5 JP2023570344A JP2023570344A JPWO2022249077A5 JP WO2022249077 A5 JPWO2022249077 A5 JP WO2022249077A5 JP 2023570344 A JP2023570344 A JP 2023570344A JP 2023570344 A JP2023570344 A JP 2023570344A JP WO2022249077 A5 JPWO2022249077 A5 JP WO2022249077A5
Authority
JP
Japan
Prior art keywords
chip
handler
bridge member
bridge
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023570344A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024520311A (ja
JP2024520311A5 (https=
JP7789088B2 (ja
Publication date
Priority claimed from US17/303,333 external-priority patent/US11735575B2/en
Application filed filed Critical
Publication of JP2024520311A publication Critical patent/JP2024520311A/ja
Publication of JP2024520311A5 publication Critical patent/JP2024520311A5/ja
Publication of JPWO2022249077A5 publication Critical patent/JPWO2022249077A5/ja
Application granted granted Critical
Publication of JP7789088B2 publication Critical patent/JP7789088B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2023570344A 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング Active JP7789088B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/303,333 US11735575B2 (en) 2021-05-27 2021-05-27 Bonding of bridge to multiple semiconductor chips
US17/303,333 2021-05-27
PCT/IB2022/054874 WO2022249077A1 (en) 2021-05-27 2022-05-25 Bonding of bridge to multiple semiconductor chips

Publications (4)

Publication Number Publication Date
JP2024520311A JP2024520311A (ja) 2024-05-24
JP2024520311A5 JP2024520311A5 (https=) 2024-07-31
JPWO2022249077A5 true JPWO2022249077A5 (https=) 2024-07-31
JP7789088B2 JP7789088B2 (ja) 2025-12-19

Family

ID=84194293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023570344A Active JP7789088B2 (ja) 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング

Country Status (7)

Country Link
US (2) US11735575B2 (https=)
JP (1) JP7789088B2 (https=)
CN (1) CN117397025A (https=)
DE (1) DE112022001645B4 (https=)
GB (1) GB2622173A (https=)
TW (1) TWI824443B (https=)
WO (1) WO2022249077A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips
US12300660B2 (en) * 2022-01-27 2025-05-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a bonded semiconductor structure
KR102737071B1 (ko) * 2024-01-02 2024-12-03 엘지이노텍 주식회사 회로기판 및 이를 포함하는 반도체 패키지 기판
CN118156222B (zh) * 2024-05-13 2024-08-06 日月新半导体(威海)有限公司 一种半导体芯片的封装模块及其制备方法
WO2026059959A1 (en) * 2024-09-16 2026-03-19 Kulicke And Soffa Industries, Inc. Systems for bonding a semiconductor element to a substrate using reducing gas and related methods

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882546B2 (en) 2001-10-03 2005-04-19 Formfactor, Inc. Multiple die interconnect system
JP3872763B2 (ja) 2003-02-26 2007-01-24 東レエンジニアリング株式会社 ボンディング方法
US7348666B2 (en) 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
JP4265997B2 (ja) 2004-07-14 2009-05-20 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP4484831B2 (ja) * 2006-03-02 2010-06-16 パナソニック株式会社 電子部品内蔵モジュールおよび電子部品内蔵モジュールの製造方法
JP5183028B2 (ja) 2006-03-02 2013-04-17 神港精機株式会社 固着材およびバンプ形成方法
JP4991495B2 (ja) * 2007-11-26 2012-08-01 東京エレクトロン株式会社 検査用保持部材及び検査用保持部材の製造方法
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP5645592B2 (ja) 2010-10-21 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101740483B1 (ko) 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9142532B2 (en) 2012-04-24 2015-09-22 Bondtech Co., Ltd. Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
WO2015023232A1 (en) 2013-08-14 2015-02-19 Orion Systems Integration Pte Ltd Apparatus And Method For Bonding A Plurality Of Semiconductor Chips Onto A Substrate
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
TWI652778B (zh) 2016-01-27 2019-03-01 Amkor Technology, Inc. 半導體封裝以及其製造方法
US10170428B2 (en) * 2016-06-29 2019-01-01 Intel Corporation Cavity generation for embedded interconnect bridges utilizing temporary structures
US10483156B2 (en) * 2017-11-29 2019-11-19 International Business Machines Corporation Non-embedded silicon bridge chip for multi-chip module
US10490503B2 (en) 2018-03-27 2019-11-26 Intel Corporation Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same
US10535608B1 (en) 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
US10916507B2 (en) 2018-12-04 2021-02-09 International Business Machines Corporation Multiple chip carrier for bridge assembly
US10833051B2 (en) 2019-01-24 2020-11-10 International Business Machines Corporation Precision alignment of multi-chip high density interconnects
US10991635B2 (en) 2019-07-20 2021-04-27 International Business Machines Corporation Multiple chip bridge connector
US11164817B2 (en) * 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11094637B2 (en) 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US12159840B2 (en) * 2020-06-23 2024-12-03 Intel Corporation Scalable and interoperable PHYLESS die-to-die IO solution
US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips

Similar Documents

Publication Publication Date Title
JPH10107121A5 (https=)
WO2000046665A3 (en) Zero overhead exception handling
JPWO2022249077A5 (https=)
JP2000323384A5 (https=)
CN103730401A (zh) 一种改进型芯片夹持装置
KR102128618B1 (ko) 유연성을 갖는 재료의 가공을 위한 밀착형 고정장치
CN205539924U (zh) 利用多棱镜扫描技术进行曝光的pcb曝光设备
CN102160187A (zh) 用于太阳能电池的载体和制造太阳能电池总成的方法
JPS62100346A (ja) 枠体の位置決め装置
US20140166823A1 (en) Cable clamp
CN206270370U (zh) 一种芯片测试用假片
CN215933535U (zh) 刻蚀设备
CN213026054U (zh) 一种高速传输线定位治具
CN211184471U (zh) 一种高效刮锡贴片治具
KR970077467A (ko) 수평식핸들러의 소자이송방법
JPH04277699A (ja) 半導体装置搬送治具
CN209151118U (zh) 一种石英晶体陶瓷基座结构
JPH01206644A (ja) 基板吸着構造
JPS632317A (ja) 縦型処理装置およびその治具
CN207800581U (zh) 一种自检大尺寸半导体底座组件
TW200634966A (en) Common change kit in test handler for bga packages
JPH0461320A (ja) 篭形ボート
JPS6016542U (ja) 半導体ウエ−ハ用ボ−ト
TWI288962B (en) Multi-specimen fixture
JPH0138912Y2 (https=)