JP7789088B2 - 複数の半導体チップへのブリッジのボンディング - Google Patents

複数の半導体チップへのブリッジのボンディング

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Publication number
JP7789088B2
JP7789088B2 JP2023570344A JP2023570344A JP7789088B2 JP 7789088 B2 JP7789088 B2 JP 7789088B2 JP 2023570344 A JP2023570344 A JP 2023570344A JP 2023570344 A JP2023570344 A JP 2023570344A JP 7789088 B2 JP7789088 B2 JP 7789088B2
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Prior art keywords
chip
handler
bridge
terminals
bridge member
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Japanese (ja)
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JP2024520311A (ja
JP2024520311A5 (https=
JPWO2022249077A5 (https=
Inventor
晃啓 堀部
敬仁 渡邊
豊広 青木
隆史 久田
裕幸 森
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International Business Machines Corp
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International Business Machines Corp
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Publication of JPWO2022249077A5 publication Critical patent/JPWO2022249077A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/616Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips
    • H10W70/618Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/011Apparatus therefor
    • H10W72/0113Apparatus for manufacturing die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/401Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/016Manufacture or treatment of strap connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07125Means for controlling the bonding environment, e.g. valves or vacuum pumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07141Means for applying energy, e.g. ovens or lasers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07178Means for aligning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07188Apparatus chuck
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07202Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207Temporary substrates, e.g. removable substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07221Aligning
    • H10W72/07227Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • H10W72/227Multiple bumps having different sizes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/877Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2023570344A 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング Active JP7789088B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/303,333 US11735575B2 (en) 2021-05-27 2021-05-27 Bonding of bridge to multiple semiconductor chips
US17/303,333 2021-05-27
PCT/IB2022/054874 WO2022249077A1 (en) 2021-05-27 2022-05-25 Bonding of bridge to multiple semiconductor chips

Publications (4)

Publication Number Publication Date
JP2024520311A JP2024520311A (ja) 2024-05-24
JP2024520311A5 JP2024520311A5 (https=) 2024-07-31
JPWO2022249077A5 JPWO2022249077A5 (https=) 2024-07-31
JP7789088B2 true JP7789088B2 (ja) 2025-12-19

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JP2023570344A Active JP7789088B2 (ja) 2021-05-27 2022-05-25 複数の半導体チップへのブリッジのボンディング

Country Status (7)

Country Link
US (2) US11735575B2 (https=)
JP (1) JP7789088B2 (https=)
CN (1) CN117397025A (https=)
DE (1) DE112022001645B4 (https=)
GB (1) GB2622173A (https=)
TW (1) TWI824443B (https=)
WO (1) WO2022249077A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips
US12300660B2 (en) * 2022-01-27 2025-05-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a bonded semiconductor structure
KR102737071B1 (ko) * 2024-01-02 2024-12-03 엘지이노텍 주식회사 회로기판 및 이를 포함하는 반도체 패키지 기판
CN118156222B (zh) * 2024-05-13 2024-08-06 日月新半导体(威海)有限公司 一种半导体芯片的封装模块及其制备方法
WO2026059959A1 (en) * 2024-09-16 2026-03-19 Kulicke And Soffa Industries, Inc. Systems for bonding a semiconductor element to a substrate using reducing gas and related methods

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004259917A (ja) 2003-02-26 2004-09-16 Toray Eng Co Ltd ボンディング方法および装置
JP2006032556A (ja) 2004-07-14 2006-02-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2006261311A (ja) 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2007229776A (ja) 2006-03-02 2007-09-13 Shinko Seiki Co Ltd 固着材およびバンプ形成方法
JP2012529770A (ja) 2009-06-24 2012-11-22 インテル・コーポレーション マルチチップパッケージおよび、マルチチップパッケージのダイからダイへのインターコネクトを提供する方法
US20190164806A1 (en) 2017-11-29 2019-05-30 International Business Machines Corporation Non-embedded silicon bridge chip for multi-chip module
US20200176383A1 (en) 2018-12-04 2020-06-04 International Business Machines Corporation Multiple chip carrier for bridge assembly
US20200243479A1 (en) 2019-01-24 2020-07-30 International Business Machines Corporation Precision alignment of multi-chip high density interconnects

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882546B2 (en) 2001-10-03 2005-04-19 Formfactor, Inc. Multiple die interconnect system
US7348666B2 (en) 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
JP4484831B2 (ja) * 2006-03-02 2010-06-16 パナソニック株式会社 電子部品内蔵モジュールおよび電子部品内蔵モジュールの製造方法
JP4991495B2 (ja) * 2007-11-26 2012-08-01 東京エレクトロン株式会社 検査用保持部材及び検査用保持部材の製造方法
JP5645592B2 (ja) 2010-10-21 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101740483B1 (ko) 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9142532B2 (en) 2012-04-24 2015-09-22 Bondtech Co., Ltd. Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
WO2015023232A1 (en) 2013-08-14 2015-02-19 Orion Systems Integration Pte Ltd Apparatus And Method For Bonding A Plurality Of Semiconductor Chips Onto A Substrate
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
TWI652778B (zh) 2016-01-27 2019-03-01 Amkor Technology, Inc. 半導體封裝以及其製造方法
US10170428B2 (en) * 2016-06-29 2019-01-01 Intel Corporation Cavity generation for embedded interconnect bridges utilizing temporary structures
US10490503B2 (en) 2018-03-27 2019-11-26 Intel Corporation Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same
US10535608B1 (en) 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
US10991635B2 (en) 2019-07-20 2021-04-27 International Business Machines Corporation Multiple chip bridge connector
US11164817B2 (en) * 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11094637B2 (en) 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US12159840B2 (en) * 2020-06-23 2024-12-03 Intel Corporation Scalable and interoperable PHYLESS die-to-die IO solution
US11735575B2 (en) * 2021-05-27 2023-08-22 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004259917A (ja) 2003-02-26 2004-09-16 Toray Eng Co Ltd ボンディング方法および装置
JP2006032556A (ja) 2004-07-14 2006-02-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2006261311A (ja) 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2007229776A (ja) 2006-03-02 2007-09-13 Shinko Seiki Co Ltd 固着材およびバンプ形成方法
JP2012529770A (ja) 2009-06-24 2012-11-22 インテル・コーポレーション マルチチップパッケージおよび、マルチチップパッケージのダイからダイへのインターコネクトを提供する方法
US20190164806A1 (en) 2017-11-29 2019-05-30 International Business Machines Corporation Non-embedded silicon bridge chip for multi-chip module
US20200176383A1 (en) 2018-12-04 2020-06-04 International Business Machines Corporation Multiple chip carrier for bridge assembly
US20200243479A1 (en) 2019-01-24 2020-07-30 International Business Machines Corporation Precision alignment of multi-chip high density interconnects

Also Published As

Publication number Publication date
JP2024520311A (ja) 2024-05-24
DE112022001645B4 (de) 2024-06-06
US11735575B2 (en) 2023-08-22
TWI824443B (zh) 2023-12-01
US20230299067A1 (en) 2023-09-21
TW202247723A (zh) 2022-12-01
DE112022001645T5 (de) 2024-01-04
US12142603B2 (en) 2024-11-12
GB2622173A (en) 2024-03-06
GB202318919D0 (en) 2024-01-24
US20220384412A1 (en) 2022-12-01
CN117397025A (zh) 2024-01-12
WO2022249077A1 (en) 2022-12-01

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