JP2024512844A - Display panel, its driving method, and display device - Google Patents

Abstract

The present invention provides a display panel, a method for driving the same, and a display device. The display panel (1) includes a gate drive circuit (10), the gate drive circuit (10) includes sequentially arranged multi-stage shift registers, and the sequentially arranged multi-stage shift registers are combined to form N sets of gates. The shift registers of the N sets of gate drive subcircuits are each connected in cascade, and the gate drive subcircuit of the mth set of the N sets of gate drive subcircuits is connected to the shift register of the mth stage cascaded. , an m+L*N stage shift register, where m is an integer of 1 or more and N or less, L is an integer of 1 or more, and N is an even number of 2 or more. The display panel can clearly display the H-1Line screen, has no misalignment problems, meets industry CM value test standards, and improves the performance of display products.

Description

This disclosure claims priority to Chinese Patent Application No. 202110381834.1 filed on April 9, 2021, and all contents disclosed in the above-mentioned Chinese Patent Application are incorporated herein by reference. It is incorporated as.

Embodiments of the present disclosure relate to a display panel, a driving method thereof, and a display device.

In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel typically includes multiple rows of gate scanning signal lines and multiple columns of data lines that intersect with the gate scanning signal lines. and, including. Driving for the gate scan signal line may be performed by a bound integrated drive circuit. In recent years, with the continuous development of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, gate scanning signal line drive circuits are directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array). It also becomes possible to drive scanning signal lines. For example, an on-off state voltage signal (scanning signal) is supplied using multiple rows of gate scanning signal lines including GOAs of multiple shift register units connected in cascade as a pixel array, and controlling, for example, multiple rows of gate scanning signal lines. The gray voltage required to display each gray scale of the image at each pixel unit is determined by sequentially turning on the pixel units and by supplying data signals to the pixel units in the corresponding rows of the pixel array through the data lines. is formed and one frame of image is displayed.

At least one embodiment of the present disclosure is a display panel including a gate drive circuit, the display panel comprising:
The gate drive circuit includes sequentially arranged multi-stage shift registers, the sequentially arranged multi-stage shift registers are combined into N sets of gate drive subcircuits, and the N sets of gate drive subcircuits include: The shift registers are each cascaded,
The mth set of gate drive subcircuits of the N sets of gate drive subcircuits includes an mth stage shift register and an m+L*N stage shift register that are cascade-connected;
A display panel is provided in which m is an integer greater than or equal to 1 and less than or equal to N, L is an integer greater than or equal to 1, and N is an even number greater than or equal to 2.

For example, the display panel according to at least one embodiment of the present disclosure further includes N trigger signal lines each connected to the N sets of gate drive subcircuits,
The m-th trigger signal line among the N trigger signal lines is connected to the input terminal of the m-th stage shift register.

For example, a display panel according to at least one embodiment of the present disclosure further includes 4K clock signal lines,
The 4K clock signal lines include first to fourth K clock signal lines that are each connected to a clock signal terminal of the multi-stage shift register and supply a clock signal,
K is an integer of 1 or more.

For example, in the display panel according to at least one embodiment of the present disclosure, when K=1, the 4K clock signal lines are a first clock signal line, a second clock signal line, and a third clock signal line. , a fourth clock signal line,
The first clock signal line is connected to the clock signal terminal of the 4n-3 stage shift register, the second clock signal line is connected to the clock signal terminal of the 4n-2 stage shift register, and the third clock signal line is connected to the clock signal terminal of the 4n-2 stage shift register. the signal line is connected to a clock signal terminal of a 4n-1 stage shift register, the fourth clock signal line is connected to a clock signal terminal of a 4n stage shift register,
n is an integer of 1 or more.

For example, in the display panel according to at least one embodiment of the present disclosure, when K=3, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. Signal line, 5th clock signal line, 6th clock signal line, 7th clock signal line, 8th clock signal line, 9th clock signal line, 10th clock signal line, 11th clock signal line, 12th clock signal line including;
The first clock signal line is connected to the clock signal terminal of the 12n-11th stage shift register, the second clock signal line is connected to the clock signal terminal of the 12n-10th stage shift register, and the third clock signal line is connected to the clock signal terminal of the 12n-11th stage shift register. The signal line is connected to the clock signal terminal of the 12n-9 stage shift register, the fourth clock signal line is connected to the clock signal terminal of the 12n-8 stage shift register, and the fifth clock signal line is connected to the clock signal terminal of the 12n-8 stage shift register. The sixth clock signal line is connected to the clock signal terminal of the 12n-7 stage shift register, the sixth clock signal line is connected to the clock signal terminal of the 12n-6 stage shift register, and the seventh clock signal line is connected to the 12n-5 stage shift register. The eighth clock signal line is connected to the clock signal terminal of the 12n-4th stage shift register, and the ninth clock signal line is connected to the clock signal terminal of the 12n-3th stage shift register. The tenth clock signal line is connected to a clock signal terminal of a 12n-2 stage shift register, and the eleventh clock signal line is connected to a clock signal terminal of a 12n-1 stage shift register. The twelfth clock signal line is connected to a clock signal terminal of a 12nth stage shift register, where n is an integer of 1 or more.

For example, in the display panel according to at least one embodiment of the present disclosure, when N=2, the N trigger signal lines include a first trigger signal line and a second trigger signal line;
The first trigger signal line is connected to the input terminals of the first K odd-numbered shift registers to supply a first trigger signal, and the input terminals of each of the remaining odd-numbered shift registers are connected to this and K-1. connected to the output terminal of the upper shift register that is separated by an odd number of stages.
The second trigger signal line is connected to the input terminals of the first K even stage shift registers to supply a second trigger signal, and the input terminals of each of the remaining even stage shift registers are connected to this and K-1. It is connected to the output terminal of the upper stage shift register which is separated by an even number of stages.

For example, a display panel according to at least one embodiment of the present disclosure further includes a clock controller;
The clock controller is connected to the 4K clock signal lines,
When supplying a clock signal to a clock signal line connected to an odd number of gate drive subcircuits among the N sets of gate drive subcircuits, the gates of an even number of the N sets of gate drive subcircuits are supplied. not supplying the clock signal to the clock signal line connected to the drive sub-circuit, or supplying an invalid clock signal to the clock signal line connected to the even-numbered set of gate drive sub-circuits;
When the clock signal is supplied to the clock signal line connected to the even-numbered set of gate drive sub-circuits, the clock signal is not supplied to the clock signal line connected to the odd-numbered set of gate drive sub-circuits, or The invalid clock signal is configured to be supplied to a clock signal line connected to the odd-numbered set of gate drive subcircuits.

For example, in a display panel according to at least one embodiment of the present disclosure, the time difference between the clock signals received by two adjacent clock signal lines connected to the odd set of gate drive subcircuits is 2T;
a time difference between clock signals received by two adjacent clock signal lines connected to the even set of gate drive subcircuits is 2T;
T is the charging time of one row of sub-pixels.

For example, in a display panel according to at least one embodiment of the present disclosure, the clock controller is further connected to the N trigger signal lines,
When supplying a valid trigger signal to the trigger signal line connected to the odd-numbered set of gate drive sub-circuits, an invalid trigger signal is supplied to the trigger signal line connected to the even-numbered set of gate drive sub-circuits, or not providing the valid trigger signal;
When supplying the valid trigger signal to the trigger signal lines connected to the even-numbered sets of gate drive sub-circuits, supply the invalid trigger signal to the trigger signal lines connected to the odd-numbered sets of gate drive sub-circuits; , or configured not to provide the valid trigger signal.

For example, a display panel according to at least one embodiment of the present disclosure further includes a pixel array connected to the gate drive circuit,
The pixel array includes sub-pixels in multiple rows and multiple columns,
Odd-numbered sets of gate drive sub-circuits among the N sets of gate drive sub-circuits are each connected to sub-pixels in odd-numbered rows,
Even-numbered sets of gate drive sub-circuits among the N sets of gate drive sub-circuits are respectively connected to sub-pixels in even-numbered rows.

For example, a display panel according to at least one embodiment of the present disclosure further includes a data driving circuit and a plurality of data lines,
The plurality of data lines are electrically connected to the plurality of columns of subpixels and configured to transmit data signals supplied by the data drive circuit to the plurality of columns of subpixels,
The data driving circuit includes:
When driving the pixel array to display the screen of the x-th frame, supplying a data signal having a first level to the plurality of data lines;
When driving the pixel array to display the x+1 frame screen, the pixel array is configured to supply a data signal having a second level to the plurality of data lines,
x is an integer of 1 or more.

For example, in a display panel according to at least one embodiment of the present disclosure, the gate drive circuit is located on one side of the pixel array.

For example, in the display panel according to at least one embodiment of the present disclosure, the gate drive circuits are located on both sides of the pixel array, and the shift registers at the same stage in the gate drive circuits located on both sides drive sub-pixels in the same row. drive

For example, in the display panel according to at least one embodiment of the present disclosure, the sequentially arranged multi-stage shift registers include a plurality of dummy shift registers, and the input of the N-stage dummy shift registers among the plurality of dummy shift registers. Each terminal is connected to the N trigger signal lines to receive a trigger signal.

At least one embodiment of the present disclosure also provides a display device that includes a display panel according to any embodiment of the present disclosure.

At least one embodiment of the present disclosure also provides:
The display panel includes a pixel array and a plurality of gate scanning signal lines, the pixel array includes subpixels arranged in multiple rows and columns, and each of the plurality of gate scanning signal lines is connected to the plurality of rows of subpixels. ,
When driving the pixel array to display the screen of the x-th frame, the odd-numbered gate scanning signal lines of the plurality of gate scanning signal lines output gate scanning signals, and Outputting an invalid gate scanning signal or not outputting the gate scanning signal from an even-numbered gate scanning signal line among the lines;
When driving the pixel array to display the x+1 frame screen, the even-numbered gate scanning signal lines output the gate scanning signal, and the odd-numbered gate scanning signal lines output the invalid gate scanning signal. or not outputting the gate scanning signal,
A display panel driving method is provided in which x is an odd number of 1 or more.

For example, in the driving method according to at least one embodiment of the present disclosure, the odd-numbered rows of gate scanning signal lines are further connected to odd-numbered sets of gate drive subcircuits, and the even-numbered rows of gate scanning signal lines are further connected to even-numbered sets of gate drive subcircuits. connected to the subcircuit,
When driving the pixel array to display the screen of the x-th frame, a clock signal is supplied to the clock signal line connected to the odd-numbered set of gate drive sub-circuits, and the clock signal line connected to the even-numbered set of gate drive sub-circuits is supplied. not supplying the clock signal to the clock signal line, or supplying an invalid clock signal to the clock signal line;
When driving the pixel array to display the screen of the The clock signal is not supplied to the clock signal line that is used, or the invalid clock signal is supplied to the clock signal line.

For example, in the driving method according to at least one embodiment of the present disclosure, when driving the pixel array to display the x-th frame screen, two adjacent clocks connected to the odd-numbered set of gate drive subcircuits The time difference between the clock signals supplied by the signal line is 2T,
When driving the pixel array to display the screen of the ,
T is the charging time of one row of sub-pixels.

For example, in the driving method according to at least one embodiment of the present disclosure, when driving the pixel array to display the screen of the providing an invalid trigger signal or not providing a valid trigger signal to trigger signal lines connected to the even set of gate drive subcircuits;
When driving the pixel array to display the screen of the The method further includes the step of supplying an invalid trigger signal or not supplying a valid trigger signal to the trigger signal line that is used.

For example, in the driving method according to at least one embodiment of the present disclosure, the display panel further includes a data line electrically connected to the plurality of columns of sub-pixels,
The method includes the step of supplying a first level to the plurality of data lines when driving the pixel array to display the screen of the x-th frame;
The method further includes the step of supplying a second level to the plurality of data lines when driving the pixel array to display the screen of the x+1 frame.

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings of the embodiments will be briefly described below, but obviously the drawings in the following description are not applicable to some embodiments of the present invention. However, it is not intended to limit the present invention.

It is a timing schematic diagram of H-1 Line. FIG. 2 is a schematic diagram of line deviation timing of H-1 Line. FIG. 2 is a schematic diagram of a display screen of H-1Line in an ideal state. FIG. 2 is a schematic diagram of line deviation on the H-1 Line display screen in an actual state. 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. FIG. 1 is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. FIG. 3 is a schematic diagram of another gate drive circuit according to at least one embodiment of the present disclosure. FIG. 1 is a schematic diagram of a display panel including 4 CLK (K=1) according to at least one embodiment of the present disclosure; FIG. 1 is a schematic diagram of a display panel including 8 CLK (K=2) according to at least one embodiment of the present disclosure; FIG. 1 is a schematic diagram of a display panel including 12 CLK (K=3) according to at least one embodiment of the present disclosure; FIG. 1 is a schematic diagram of a display panel including 16 CLK (K=4) according to at least one embodiment of the present disclosure; FIG. FIG. 6 is a timing diagram corresponding to an xth frame display screen according to at least one embodiment of the present disclosure; FIG. 3 is a schematic diagram of a display screen for an xth frame according to at least one embodiment of the present disclosure. FIG. 6 is a timing schematic diagram corresponding to a display screen of the x+1 frame according to at least one embodiment of the present disclosure; FIG. 3 is a schematic diagram of a display screen of an x+1 frame according to at least one embodiment of the present disclosure. FIG. 3 is a schematic diagram of the positional relationship of a gate drive circuit according to at least one embodiment of the present disclosure. FIG. 3 is a schematic diagram of the positional relationship of another gate drive circuit according to at least one embodiment of the present disclosure. 1 is a schematic diagram of a combined bright and dark line display screen according to at least one embodiment of the present disclosure; FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. FIG. 3 is a flowchart of a method for driving a display panel according to at least one embodiment of the present disclosure.

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be explained clearly and completely with reference to the drawings of the embodiments of the present invention. Explain. Obviously, the described embodiments are some but not all embodiments of the invention. All other embodiments that a person skilled in the art can obtain without any creative effort based on the described embodiments of the invention fall within the patentable scope of the invention.

Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by those of ordinary skill in the art. The use of "first," "second," and similar terms in this disclosure do not imply any order, quantity or importance, but rather distinguish between different components. Similarly, terms such as "a", "one", or "the" are not limiting in number, but rather indicate the presence of at least one. Terms such as "comprising" or "include" mean that the elements or articles listed before the term cover the elements or articles listed after the term and their equivalents, but do not exclude other elements or articles. refers to Terms such as "coupling" or "coupling" are not limited to physical or mechanical coupling, but include electrical coupling, whether direct or indirect. "Top", "bottom", "left", "right", etc. only represent relative positional relationships, and when the absolute position of the object to be explained changes, the relative positional relationship also changes accordingly.

Hereinafter, the present disclosure will be explained with some specific examples. In order to keep the following description of embodiments of the invention clear and unambiguous, detailed descriptions of known features and components may be omitted. When any element of an embodiment of the invention appears in more than one drawing, that element is designated by the same reference numeral in each drawing.

8K resolution + 5G communication is a hot topic in the current development of science and technology, and each TV manufacturer is releasing products with 8K resolution (hereinafter referred to as "8K products"), and each panel factory is also responding to market demand. The company is responding quickly to these requests and rapidly deploying human resources to research and development. Products with 8K resolution are required to have a high pixel count as high-end display products, as well as a high refresh rate. Products that combine 8K resolution with a 120 hertz (Hz) refresh rate (hereinafter referred to as "8K, 120Hz products") have become standard equipment for high-end display products. However, in 8K, 120Hz products, the charging time for one row of pixels is only 1/120Hz/4500 rows = 1.85 μs (microseconds), so the gate scanning signal delay and data signal delay This can have a significant impact on time. Also, based on energy efficiency standards for home appliances, the transmittance of an 8K, 120Hz product must be the same as a product with a 60Hz refresh rate to meet power consumption requirements. Therefore, the load on gate scanning signal lines and data lines of 8K, 120Hz products cannot be reduced even if the line width is increased. Therefore, when displaying an H-1 line screen (Pattern), in 8K, 120 Hz products, the delay of the gate scanning signal is large and the data signal is inverted for each row, resulting in the problem of line misalignment.

There are industry-wide test standards for misalignment issues. For example, a test is performed using a CM (Contrast Modulation) value. The CM value is the value of the black and white line luminance difference between phases on the display screen in H-1Line mode and V-1Line mode. For example, a customer can judge the performance of a displayed product based on the CM value of H-1Line or V-1Line. For example, the higher the CM value, the greater the difference in brightness between black and white lines (see FIG. 1C), indicating that the performance of the display product is better. For example, the International Committee for Display Metrology (ICDM) requires that commercials for 8K products account for 50% or more.

For example, the CM value may be expressed by the following expression.

Here, Lw represents the luminance of the white line, and Lk represents the luminance of the black line.

For example, in the case of 8K products, there is no problem with line misalignment with V-1Line, but with H-1Line, due to the special nature of the image, there are high and low jumps in the data signal, and if the gate scan signal has a large delay, the gate scan Since the level of the signal does not change over time, the data signal is inverted before the data writing transistor of the pixel circuit is turned off in a timely manner, causing a misalignment in the H-1 line.

FIG. 1A is a schematic timing diagram of H-1Line, FIG. 1B is a schematic diagram of line deviation timing of H-1Line, FIG. 1C is a schematic diagram of the display screen of H-1Line in an ideal state, and FIG. 1D is a schematic diagram of the H-1Line display screen in an ideal state. FIG. 2 is a schematic diagram of line deviation on the H-1 Line display screen in an actual state.

For example, the level settings for Figure 1A are shown below:

For example, as shown in FIGS. 1A and 1B, the level of the data signal Datan is inverted once (eg, from a high level to a low level) every time one row of sub-pixels is charged. For example, when the data signal Datan corresponding to the sub-pixel in the current row (for example, the first row R1) is at a high level, the data signal Datan corresponding to the sub-pixel in the next row (for example, the second row R2) is at a low level. It is. After the charging of the sub-pixel Vpixel in the current row by the data signal Datan (for example, high level H) of the current row is completed, the gate scanning signal is still at a valid level because the delay of the falling edge of the gate scanning signal Gn is large. As a result, before the data writing transistor of the pixel circuit is turned off, the data signal (for example, Low level L) of the sub-pixel in the next row is input to the current sub-pixel and charged, thereby causing the current row The data signal (Low level L) of the data of the next row is input to the sub-pixel Vpixel. Therefore, the charge level of the sub-pixel Vpixel in the current row changes from the ideal state to the actual state, for example from the broken line to the solid line in FIG. H-1Line display screen (for example, as shown in Figure 1C, the black line displays only black and the white line only displays white), but the black line is sufficiently black as shown in Figure 1D. Instead, the white line will not be white enough, and line deviation will occur on the H-1 Line screen. If the line misalignment is severe, all lines on the H-1line screen will be lit.

At least one embodiment of the present disclosure is a display panel that includes a gate drive circuit, the gate drive circuit includes sequentially arranged multi-stage shift registers, and the sequentially arranged multi-stage shift registers are combined. to form N sets of gate drive subcircuits, the shift registers of the N sets of gate drive subcircuits are each connected in cascade, and the mth set of gate drive subcircuits in the N sets of gate drive subcircuits are connected in cascade. Provided is a display panel including an m-th stage shift register and an m+L*N-stage shift register, where m is an integer from 1 to N, L is an integer from 1 to N, and N is an even number from 2 to 2. do.

In the display panel of the embodiment of the present disclosure, by detecting the H-1Line screen of the display product, the odd-numbered frames cooperate with the data signal to display the odd-numbered lines, and the even-numbered frames cooperate with the data signal to display the even-numbered lines. The H-1Line screen can be displayed clearly, eliminate line shift problems, meet industry CM value test standards, and improve the performance of display products.

Hereinafter, embodiments of the present disclosure and some examples thereof will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. For example, the display panel may be a display panel with a resolution of 8K and a refresh rate of 120Hz, but of course may be a display panel with other resolutions or refresh rates, and embodiments of the present disclosure Not limited. For example, as shown in FIG. 2, in some examples the display panel 1 includes a gate drive circuit 10. For example, as shown in FIG. 2, in some other examples, the display panel 1 further includes a display area 40, the display area 40 includes a pixel array connected to the gate drive circuit 10, and the pixel array It includes sub-pixels 410 in multiple rows and multiple columns. For example, in some other examples, the display panel 1 may further include a data drive circuit 30 and a plurality of data lines DL. The plurality of data lines DL are electrically connected to the plurality of columns of sub-pixels 410 and are configured to transmit data signals supplied by the data drive circuit 30 to the plurality of columns of sub-pixels 410.

For example, data drive circuit 30 is for providing data signals to the pixel array, and gate drive circuit 10 is for providing gate scanning signals to the pixel array. The data drive circuit 30 is electrically connected to the sub-pixel 410 via the data line DL, and the gate drive circuit 10 is electrically connected to the sub-pixel 410 via the gate scanning signal line GL.

For example, the gate drive circuit drives a display panel, such as a liquid crystal display panel or an organic light emitting diode display panel, and sequentially supplies scanning signals to a plurality of gate scanning signal lines of the display panel, so that the display panel operates in one frame. This is to perform progressive scanning, interlaced scanning, etc. during the period when the screen is displayed.

FIG. 3A is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure, and FIG. 3B is a schematic diagram of another gate drive circuit according to at least one embodiment of the present disclosure. Hereinafter, a gate driving circuit according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 3A and 3B.

For example, as shown in FIGS. 3A and 3B, the gate drive circuit 10 includes sequentially arranged multi-stage shift registers. For example, as shown in FIGS. 3A and 3B, the multi-stage shift registers arranged in order include a first stage shift register GOA1, a second stage shift register GOA2, a third stage shift register GOA3, etc., which are sequentially cascaded. including. For example, in the case of an 8K resolution display panel, the multi-stage shift registers arranged in order include a first stage shift register GOA1, a second stage shift register GOA2, a third stage shift register GOA3, and a third stage shift register GOA3. ..., a 4320th stage shift register, a 4322nd stage shift register, a 4324th stage shift register, a more multistage shift register, etc., but the embodiments of the present disclosure are not limited thereto.

Note that for clarity and brevity, only 12 stages of shift registers arranged in sequence are shown in FIG. 3A, and only 16 stages of shift registers arranged in sequence are shown in FIG. 3B. However, of course, a plurality of shift register units sequentially connected in cascade may be included, and the embodiments of the present disclosure are not limited to this. may be referred to, and will not be discussed in detail here. The number of stages of the shift register is merely an example, and may be specifically determined depending on the actual situation, and the embodiments of the present disclosure are not limited thereto.

For example, sequentially arranged multi-stage shift registers are combined into N sets of gate drive subcircuits, and the shift registers of the N sets of gate drive subcircuits are each cascaded. For example, in some examples, as shown in FIG. circuit and a second set of gate drive subcircuits. For example, in some other examples, as shown in FIG. a drive subcircuit, a second set of gate drive subcircuits, a third set of gate drive subcircuits, and a fourth set of gate drive subcircuits.

For example, an m-th gate drive sub-circuit of N sets of gate drive sub-circuits includes an m-th stage shift register and an m+L*N stage shift register that are cascade-connected, where m is an integer between 1 and N inclusive. , L is an integer of 1 or more, and N is an even number of 2 or more.

Hereinafter, the gate drive circuits shown in FIGS. 3A and 3B will be explained as examples, that is, N=2 (including 2 sets of gate drive subcircuits) and N=4 (including 4 sets of gate drive subcircuits). will be described as an example, but the embodiments of the present disclosure are not limited thereto.

For example, as shown in FIG. 3A, when N=2, the first set of gate drive subcircuits (i.e., when m=1) includes an odd number of stages of shift registers that are cascaded, e.g. The odd-numbered shift registers (white rectangular frames shown in FIG. 3A) are cascade-connected 1st (m), 3rd (L=1, m+L*N=3), and 5th (L=2, m+L*N= 5), 7 (L=3, m+L*N=7), 9 (L=4, m+L*N=9), 11 (L=5, m+L*N=11)... stage shift registers GOA1, GOA3 , GOA5, GOA7, GOA9, GOA11, etc., and the second set of gate drive subcircuits (i.e., when m=2) includes cascaded even-numbered shift registers, e.g. The stage shift registers (hatched rectangular frames shown in FIG. 3A) are cascade-connected 2nd (m), 4th (L=1, m+L*N=4), 6th (L=2, m+L*N=6), 8 (L=3, m+L*N=8), 10 (L=4, m+L*N=10), 12 (L=5, m+L*N=12)... stage shift registers GOA2, GOA4, GOA6, This includes GOA8, GOA10, GOA12, etc., but the disclosed embodiments are not limited thereto.

For example, as shown in FIG. 3B, when N=4, the first set of gate drive subcircuits (i.e., when m=1) includes an odd number of stages of shift registers that are cascaded, e.g. The odd-numbered shift registers include cascaded first, fifth, ninth, thirteenth...stage shift registers GOA1, GOA5, GOA9, GOA13, etc., and a second set of gate drive subcircuits (i.e., m= 2) includes cascade-connected even-numbered stage shift registers, for example, the cascade-connected even-numbered stage shift registers include cascade-connected 2nd, 6th, 10th, 14th... stage shift registers GOA2, GOA6, GOA10, GOA14, etc., and the third set of gate drive subcircuits (i.e., when m=3) includes cascaded odd stages of shift registers, e.g. The registers include cascaded third, seventh, 11th, 15th... stages of shift registers GOA3, GOA7, GOA11, GOA15, etc., and the fourth set of gate drive subcircuits (i.e., when m=4) are cascaded. For example, the cascade-connected even-stage shift registers include cascade-connected 4th, 8th, 12th, 16th... stage shift registers GOA4, GOA8, GOA12, GOA16, etc. However, the disclosed embodiments are not limited thereto.

For example, as described above, an odd set of gate drive subcircuits (e.g., a first set of gate drive subcircuits shown in FIG. 3A or a first set of gate drive subcircuits shown in FIG. 3B, and a third set of gate drive subcircuits) The subcircuits (including the cascaded odd stages of shift registers) all include the cascaded odd stages of shift registers and the even sets of gate drive subcircuits (e.g., the second set of gate drive subcircuits shown in FIG. 3A). The circuit or the second set of gate drive subcircuits shown in FIG. include. For example, the shift registers of each set of gate drive subcircuits are each cascaded to form a separate cascade relationship, and the gate drive subcircuits of each set are not cascaded to each other, thereby ensuring that the odd frame In the case of a display of , the sub-pixels in an odd numbered row can be driven individually, or in the case of a display of an even numbered frame, the subpixels in an even numbered row can be driven individually.

For example, the display panel 1 further includes N trigger signal lines each connected to N sets of gate drive subcircuits.

For example, in some examples, the sequentially arranged multi-stage shift registers are combined into two sets of gate drive subcircuits (i.e., a first set of gate drive subcircuits and a second set of gate drive subcircuits), as shown in FIG. (gate drive subcircuits), the display panel includes two trigger signal lines each connected to two sets of gate drive subcircuits. For example, in some other examples, sequentially arranged multi-stage shift registers may be combined into four sets of gate drive subcircuits (i.e., a first set of gate drive subcircuits, a first set of (two sets of gate drive subcircuits, a third set of gate drive subcircuits, and a fourth set of gate drive subcircuits), the display panel has four sets of gate drive subcircuits each connected to four sets of gate drive subcircuits. Contains trigger signal line.

For example, the m-th trigger signal line of the N trigger signal lines is connected to the input terminal Input of the m-th stage shift register. That is, the first trigger signal line STV1 is connected to the input terminal Input of the first stage shift register of the first set of gate drive subcircuits, and the second trigger signal line STV2 is connected to the second stage shift register (i.e. The third trigger signal line is connected to the input terminal Input of the third stage shift register (i.e., the first shift register of the third set of gate drive subcircuits). The fourth trigger signal line is connected to the input terminal Input of the fourth stage shift register (that is, the first shift register of the fourth set of gate drive subcircuits). Ru.

In addition to being connected to the first stage shift register of each set of gate drive subcircuits, each trigger signal line may be connected to other stages of shift registers; specifically, It may be determined according to the actual situation, and more specifically, it may be set according to the number of clock signal lines.For specific connection relationships, refer to designs in this field, so we will not discuss them here. Don't explain in detail.

Hereinafter, a case where the display panel includes two sets of gate drive subcircuits and two trigger signal lines (a first trigger signal line STV1 and a second trigger signal line STV2) will be described as an example. The examples are not limiting. Since the connection relationships of the other sets of gate drive subcircuits are similar to this, they will not be described in detail here.

For example, in some examples, the display panel further includes 4K clock signal lines. For example, the 4K clock signal lines include a first clock signal line to a fourth K clock signal line that are each connected to a clock signal terminal CLK of a multi-stage shift register and supply a clock signal, where K is an integer of 1 or more. 4K is less than the number of stages of a multi-stage shift register. For example, K may be 1, 2, 3, 4, 5, etc. For example, the number of clock signal lines is an integer multiple of 4, such as 4CLK (4 clock signal lines, K=1), 8CLK (8 clock signal lines, K=2), 12CLK (12 clock signal lines, signal lines, K=3), 16CLK (16 clock signal lines, K=4), etc., and the embodiments of the present disclosure are not limited thereto.

FIG. 4 is a schematic diagram of a display panel including 4CLKs (K=1) according to at least one embodiment of the present disclosure, and FIG. 5 is a schematic diagram of a display panel including 8CLKs (K=2) according to at least one embodiment of the present disclosure. FIG. 6A is a schematic diagram of a display panel including 12 CLKs (K=3) according to at least one embodiment of the present disclosure, and FIG. 6B is a schematic diagram of a display panel including 16 CLKs (K=3) according to at least one embodiment of the present disclosure. FIG. 4) is a schematic diagram of a display panel including FIG.

For example, when K=1, as shown in FIG. 4, the 4K clock signal lines connect the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 include.

For example, as shown in FIG. 4, the first clock signal line CLK1 is connected to the clock signal terminal CLK of the 4n-3 (n is an integer of 1 or more) stage shift register, and the second clock signal line CLK2 is connected to the clock signal terminal CLK of the 4n-3 (n is an integer greater than or equal to 1) stage shift register. The third clock signal line CLK3 is connected to the clock signal terminal CLK of the -2nd stage shift register, the third clock signal line CLK3 is connected to the clock signal terminal CLK of the 4n-1th stage shift register, and the fourth clock signal line CLK4 is connected to the clock signal terminal CLK of the 4nth stage shift register. Connected to the clock signal terminal CLK of the shift register.

For example, in the case of K=3, as shown in FIG. 6A, the 4K clock signal lines are the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, Fifth clock signal line CLK5, sixth clock signal line CLK6, seventh clock signal line CLK7, eighth clock signal line CLK8, ninth clock signal line CLK9, tenth clock signal line CLK10, eleventh clock signal line CLK11, 12 clock signal lines CLK12.

For example, as shown in FIG. 6A, the first clock signal line CLK1 is connected to the clock signal terminal of the 12n-11th stage shift register, and the second clock signal line CLK2 is connected to the clock signal terminal of the 12n-10th stage shift register. The third clock signal line CLK3 is connected to the clock signal terminal of the 12n-9th stage shift register, and the fourth clock signal line CLK4 is connected to the clock signal terminal of the 12n-8th stage shift register. , the fifth clock signal line CLK5 is connected to the clock signal terminal of the 12n-7th stage shift register, the sixth clock signal line CLK6 is connected to the clock signal terminal of the 12n-6th stage shift register, and the seventh clock signal line CLK5 is connected to the clock signal terminal of the 12n-6th stage shift register. The signal line CLK7 is connected to the clock signal terminal of the 12n-5th stage shift register, the 8th clock signal line CLK8 is connected to the clock signal terminal of the 12n-4th stage shift register, and the 9th clock signal line CLK9 is connected to the clock signal terminal of the 12n-5th stage shift register. The 10th clock signal line CLK10 is connected to the clock signal terminal of the 12n-3 stage shift register, the 11th clock signal line CLK11 is connected to the clock signal terminal of the 12n-1 stage shift register, and the 11th clock signal line CLK11 is connected to the clock signal terminal of the 12n-1 stage shift register. The twelfth clock signal line CLK12 is connected to the clock signal terminal of the shift register of the 12nth stage, where n is an integer of 1 or more.

In addition, in the case of other numbers of clock signal lines, the connection method with the shift register unit is similar to that shown in FIGS. 4 and 6A, so it will not be explained in detail here, and of course other connection methods may be adopted. However, the embodiments of the present disclosure are not limited thereto.

For example, as shown in FIGS. 4 to 6B, when N=2, the N trigger signal lines include a first trigger signal line STV1 and a second trigger signal line STV2.

For example, the first trigger signal line STV1 is connected to the input terminal Input of the first K odd-numbered shift registers to supply the first trigger signal, and the input terminal Input of each of the remaining odd-numbered shift registers is connected to this input terminal. The second trigger is The line STV2 is connected to the input terminal Input of the first K even stage shift registers to provide the second trigger signal, and the input terminal Input of each remaining even stage shift register is connected to this and K-1 shift registers. is connected to the output terminal OUT of an upper stage shift register that is separated by an even number of stages, or to the output terminal OUT of an upper stage shift register that is separated from this by an even number of stages.

For example, as shown in FIG. 4, when four clock signal lines (K=1) are included, for the first set of gate drive subcircuits, the first trigger signal line STV1 is the first trigger signal line of the gate drive circuit. It is connected to the input terminal Input of the odd stage shift register (i.e., the first stage shift register A1) to supply the first trigger signal, and the input terminal Input of each of the remaining odd stage shift registers is connected to this and 0. connected to the output terminal OUT of the upper shift register that is separated by an odd number of stages (i.e., connected to the output terminal OUT of an adjacent upper stage shift register), or separated by one stage from this Connected to the output terminal OUT of the upper stage shift register. For example, although the third stage shift register will be described as an example of the remaining odd-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the third stage shift register A3 is connected to the output terminal OUT of the adjacent upper odd stage shift register (i.e., the first stage shift register A1), or (that is, the second stage shift register A2 is apart) from the upper stage shift register (that is, the first stage shift register A1).

For example, as shown in FIG. 4, for a second set of gate drive subcircuits that includes four (K=1) clock signal lines, the second trigger line STV2 is the first even-stage shift register. (That is, the second stage shift register A2) is connected to the input terminal Input to supply the second trigger signal, and the input terminal Input of each of the remaining even stage shift registers is separated from this by 0 even stages. connected to the output terminal OUT of the upper shift register (i.e., connected to the output terminal OUT of the upper even-numbered shift register adjacent to it), or of the upper shift register that is one stage away from it. Connected to the output terminal OUT. For example, a fourth stage shift register will be described as an example of the remaining even-numbered stage shift registers, but the embodiments of the present disclosure are not limited to this. For example, the input terminal Input of the fourth stage shift register A4 is connected to the output terminal OUT of the upper even stage shift register (i.e., the second stage shift register A2) adjacent thereto, or one stage is connected to this. (i.e., the third stage shift register A3 is separated from the upper stage shift register A2).

For example, as shown in FIG. 5, when eight (K=2) clock signal lines are included, for the first set of gate drive subcircuits, the first trigger signal line STV1 is the first trigger signal line STV1 of the gate drive circuit. It is connected to the input terminals Input of two odd-stage shift registers (i.e., the first-stage shift register A1 and the third-stage shift register A3) to supply the first trigger signal, and supplies the first trigger signal to each of the remaining odd-stage shift registers. The input terminal Input of is connected to the output terminal OUT of the upper shift register which is separated by one odd stage from this, or is connected to the output terminal OUT of the upper stage shift register which is separated by three stages from this. For example, although the fifth stage shift register will be described as an example of the remaining odd-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the fifth stage shift register A5 is connected to the upper stage shift register (i.e., the first stage shift register A1) which is separated from it by one odd stage (i.e., the third stage shift register A3). ), or separated from it by three stages (i.e., separated by the second stage shift register A2, third stage shift register A3, and fourth stage shift register A4). (ie, the first stage shift register A1).

For example, as shown in FIG. 5, when eight (K=2) clock signal lines are included, for the second set of gate drive subcircuits, the second trigger line STV2 is connected to the first two even-numbered stages. The input terminal Input of each of the remaining even-numbered shift registers is connected to the input terminal Input of the shift register (i.e., the second stage shift register A2 and the fourth stage shift register A4) to supply the second trigger signal. , connected to the output terminal OUT of an upper stage shift register which is separated from this by one even number stage, or connected to the output terminal OUT of an upper stage shift register which is separated by three stages from this. For example, a sixth stage shift register will be described as an example of each of the remaining even-numbered stage shift registers, but the embodiments of the present disclosure are not limited to this. For example, the input terminal Input of the sixth stage shift register A6 is separated from the input terminal Input of the upper stage shift register (i.e., the second stage) which is separated by one even stage (i.e., the fourth stage shift register A4 is apart). is connected to the output terminal OUT of the shift register A2 of It is connected to the output terminal OUT of a distant upper stage shift register (ie, second stage shift register A2).

For example, as shown in FIG. 6A, when 12 (K=3) clock signal lines are included, for the first set of gate drive subcircuits, the first trigger signal line STV1 is the first trigger signal line of the gate drive circuit. connected to input terminals Input of three odd-stage shift registers (i.e., first-stage shift register A1, third-stage shift register A3, and fifth-stage shift register A5) to supply a first trigger signal; The input terminal Input of each of the remaining odd-numbered stages is connected to the output terminal OUT of the upper-stage shift register that is separated by 2 (K-1 = 2) odd-numbered stages, or 5 (2K -1=5) is connected to the output terminal OUT of the upper stage shift register which is separated by a stage. For example, although the seventh stage shift register will be described as an example of the remaining odd-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the seventh stage shift register A7 is the upper stage shift register (i.e. , the upper stage shift register (A1) is connected to the output terminal OUT of the first stage shift register A1), or is separated from it by five stages (i.e., the second stage shift register A2 to the sixth stage shift register A6). That is, it is connected to the output terminal OUT of the first stage shift register A1).

For example, as shown in FIG. 6A, when including 12 (K=3) clock signal lines, for the second set of gate drive subcircuits, the second trigger line STV2 is connected to the first three even-numbered stages. of the shift registers (i.e., the second stage shift register A2, the fourth stage shift register A4, and the sixth stage shift register A6) to supply the second trigger signal, and supply the second trigger signal to each of the remaining even numbers. The input terminal Input of the shift register of a stage is connected to the output terminal OUT of the shift register of the upper stage which is separated by two even stages from this, or to the output terminal OUT of the shift register of the upper stage which is separated by five stages from this. Connected. For example, although the eighth stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the eighth stage shift register A8 is separated by two even stages (that is, the fourth stage shift register A4 and the sixth stage shift register A6). Connected to the output terminal OUT of the shift register (i.e., the second stage shift register A2), or separated from it by five stages (i.e., the third stage shift register A3 to the seventh stage shift register A7) It is connected to the output terminal OUT of a distant upper stage shift register (ie, second stage shift register A2).

For example, as shown in FIG. 6B, when 16 clock signal lines (K=4) are included, for the first set of gate drive subcircuits, the first trigger signal line STV1 is the first trigger signal line of the gate drive circuit. is connected to the input terminal Input of four odd-numbered shift registers (i.e., first-stage shift register A1, third-stage shift register A3, fifth-stage shift register A5, and seventh-stage shift register A7). The input terminal Input of each remaining odd-numbered shift register is connected to the output terminal OUT of the upper shift register separated by three odd-numbered stages, or connected to the output terminal OUT of the upper shift register separated by three odd-numbered stages. It is connected to the output terminal OUT of the upper stage shift register which is separated by the same distance as the output terminal OUT. For example, although the ninth stage shift register will be described as an example of the remaining odd-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the ninth stage shift register A9 is separated by three odd stages (i.e., the third stage shift register A3, the fifth stage shift register A5, and the seventh stage shift register A7). connected to the output terminal OUT of the upper stage shift register (i.e., the first stage shift register A1), or connected to the output terminal OUT of the upper stage shift register (i.e., the shift register A1 of the first stage), or connected to the output terminal OUT of the upper stage shift register (i.e., the shift register A2 of the second stage to the eighth stage). It is connected to the output terminal OUT of the upper stage shift register (that is, the first stage shift register A1) which is separated by the register A8.

For example, as shown in FIG. 6B, when including 16 (K=4) clock signal lines, for the second set of gate drive subcircuits, the second trigger line STV2 is connected to the first four even stages. (i.e., the second stage shift register A2, the fourth stage shift register A4, the sixth stage shift register A6, and the eighth stage shift register A8). , and the input terminal Input of each of the remaining even-numbered stages is connected to the output terminal OUT of the upper-stage shift register that is separated by three even-numbered stages from this, or the upper stage that is separated by seven stages from this is connected to the output terminal OUT of the shift register. For example, although the tenth stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the input terminal Input of the 10th stage shift register A10 is separated by three even stages (i.e., the 4th stage shift register A4, the 6th stage shift register A6, and the 8th stage shift register A8). connected to the output terminal OUT of the upper stage shift register (i.e., second stage shift register A2), which is separated by seven stages (i.e., third stage shift register A3 to ninth stage shift register It is connected to the output terminal OUT of the upper stage shift register (that is, the second stage shift register A2) which is separated by the register A9.

For example, in the example shown in FIGS. 4 and 5, when K=1 or 2, the reset terminals Reset of each of the remaining odd-stage shift registers other than the last K odd-stage shift registers are connected to this and 2K- Connected to the output terminal OUT of the lower shift register separated by two odd-numbered shift registers, or connected to the output terminal OUT of the lower shift register separated by 4K-3 stages, and the last K Except for the even-stage shift registers, the reset terminal Reset of each of the remaining even-stage shift registers is connected to the output terminal OUT of the lower-stage shift register that is separated by 2K-2 even-stage shift registers. , or to the output terminal OUT of a lower stage shift register which is separated from this by 4K-3 stages.

For example, as shown in FIG. 4, when four (K=1) clock signal lines are included, the reset terminal Reset of each of the remaining odd-numbered shift registers except the last odd-numbered shift register is It is connected to the output terminal OUT of a lower stage shift register which is separated by an odd number of stages of shift registers, or is connected to the output terminal OUT of a lower stage shift register which is separated from this by one stage. For example, the first stage shift register will be described as an example of the remaining odd-numbered stage shift registers, but the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the first stage shift register A1 is connected to the output terminal OUT of the lower stage shift register (i.e., the third stage shift register A3) which is separated by 0 odd stage shift registers. or connected to the output terminal OUT of a lower stage shift register (that is, the third stage shift register A3) which is separated by one stage (that is, the second stage shift register A2).

For example, as shown in FIG. 4, when four (K=1) clock signal lines are included, the reset terminals Reset of each of the remaining even-stage shift registers except for the last even-stage shift register are It is connected to the output terminal OUT of a lower shift register that is separated by even-numbered shift registers, or to the output terminal OUT of a lower shift register that is separated by one stage. For example, although the second stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the second stage shift register A2 is connected to the output terminal OUT of the lower stage shift register (i.e., the fourth stage shift register A4) which is separated by 0 even stage shift registers. or connected to the output terminal OUT of a lower stage shift register (that is, the fourth stage shift register A4) which is separated by one stage (that is, the third stage shift register A3).

For example, as shown in FIG. 5, when eight (K=2) clock signal lines are included, the reset terminal Reset of each of the remaining odd-numbered shift registers except the last two odd-numbered shift registers is and the output terminal OUT of a lower shift register separated by two odd-numbered shift registers, or connected to the output terminal OUT of a lower shift register separated by five stages. For example, the first stage shift register will be described as an example of the remaining odd-numbered stage shift registers, but the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the first stage shift register A1 is separated by two odd stage shift registers (that is, the third stage shift register A3 and the fifth stage shift register A5). connected to the output terminal OUT of the lower-stage shift register (i.e., seventh-stage shift register A7), or separated by five stages (i.e., second-stage shift register A2 to sixth-stage shift register A6). It is connected to the output terminal OUT of the lower stage shift register (that is, the seventh stage shift register A7).

For example, as shown in FIG. 5, when eight (K=2) clock signal lines are included, the reset terminal Reset of each of the remaining even-numbered shift registers, except for the last two even-numbered shift registers, is and is connected to the output terminal OUT of a lower shift register separated by two even-numbered shift registers, or to the output terminal OUT of a lower shift register separated by five stages. For example, although the second stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the second stage shift register A2 is separated by two even stage shift registers (that is, the fourth stage shift register A4 and the sixth stage shift register A6). connected to the output terminal OUT of the lower stage shift register (i.e., the eighth stage shift register A8), or separated by five stages (i.e., the third stage shift register A3 to the seventh stage shift register A7). It is connected to the output terminal OUT of the lower stage shift register (ie, the eighth stage shift register A8).

For example, in some other examples, K=3 (i.e., including 12 clock signal lines as shown in FIG. 6A) or 4 (i.e., including 16 clock signal lines as shown in FIG. 6B). ), for example, in the example shown in FIG. 6A, except for the last K odd-stage shift registers, the reset terminal Reset of each of the remaining odd-stage shift registers is connected only to this and the K odd-stage shift registers. It is connected to the output terminal OUT of the lower shift register which is separated from this, or is connected to the output terminal OUT of the lower shift register which is separated by 2K+1 stages, and is connected to the output terminal OUT of the lower stage shift register which is separated from this by 2K+1 stages. The reset terminal Reset of each even-numbered shift register is connected to the output terminal OUT of a lower-stage shift register that is separated from it by K even-numbered shift registers, or is connected to the output terminal OUT of a lower-stage shift register that is separated from it by 2K+1 stages. For example, in the example shown in FIG. 6B, except for the last K odd-stage shift registers, the reset terminal Reset of each of the remaining odd-stage shift registers is connected to the output terminal OUT of the register. It is connected to the output terminal OUT of a lower shift register that is separated by a stage shift register, or to the output terminal OUT of a lower stage shift register that is separated from this by 2K+1 stages. Except for the last K even-stage shift registers, the reset terminal Reset of each of the remaining even-stage shift registers is connected to the output terminal OUT of the lower-stage shift register that is separated from this by the K even-stage shift registers. or connected to the output terminal OUT of a lower stage shift register which is separated from this by 2K+1 stages.

For example, as shown in FIG. 6A, when 12 (K=3) clock signal lines are included, the reset terminal Reset of each of the remaining odd-numbered shift registers except the last three odd-numbered stage shift registers is and the output terminal OUT of a lower shift register separated by 3 (K=3) odd-numbered stages, or the output of a lower shift register separated by 7 (2K+1=7) stages from this. Connected to terminal OUT. For example, the first stage shift register will be described as an example of the remaining odd-numbered stage shift registers, but the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the first stage shift register A1 is connected to this and four odd stage shift registers (i.e., the third stage shift register A3, the fifth stage shift register A5, and the seventh stage shift register A7). connected to the output terminal OUT of the lower stage shift register (i.e., the ninth stage shift register A9), which is separated by the seventh stage (i.e., the second stage shift register A2 to the eighth stage) It is connected to the output terminal OUT of the lower stage shift register (that is, the ninth stage shift register A9) which is separated by the ninth stage shift register A8.

For example, as shown in FIG. 6A, when 12 (K=3) clock signal lines are included, the reset terminal Reset of each of the remaining even-stage shift registers except the last three even-stage shift registers is is connected to the output terminal OUT of a lower stage shift register which is separated by three even stages, or to the output terminal OUT of a lower stage shift register which is separated from this by seven stages. For example, although the second stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the second stage shift register A2 is connected to this and three even stage shift registers (i.e., the fourth stage shift register A4, the sixth stage shift register A6, and the eighth stage shift register A8). OUT of the lower shift register (i.e., shift register A10 of the 10th stage), which is separated by a distance of It is connected to the output terminal OUT of the lower shift register (ie, the 10th stage shift register A10) which is separated by the shift register A9).

For example, as shown in FIG. 6B, when 16 (K=4) clock signal lines are included, the reset terminal Reset of each of the remaining odd-numbered shift registers except the last four odd-numbered stage shift registers is and is connected to the output terminal OUT of a lower shift register separated by four odd-numbered shift registers, or to the output terminal OUT of a lower shift register separated by nine stages. For example, the first stage shift register will be described as an example of the remaining odd-numbered stage shift registers, but the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the first stage shift register A1 is connected to this and four odd stage shift registers (i.e., the third stage shift register A3, the fifth stage shift register A5, and the seventh stage shift register A7). , the ninth stage shift register A9), or connected to the output terminal OUT of the lower stage shift register (i.e., the eleventh stage shift register A11) which is separated by the ninth stage shift register A9 (separated by the ninth stage shift register A9); It is connected to the output terminal OUT of the lower shift register (ie, the 11th stage shift register A11) which is separated by the distance from the shift register A2 to the shift register A10 of the 10th stage.

For example, as shown in FIG. 6B, when 16 (K=4) clock signal lines are included, the reset terminal Reset of each of the remaining even-stage shift registers except the last four even-stage shift registers is and is connected to the output terminal OUT of a lower stage shift register separated by four even stages, or to the output terminal OUT of a lower stage shift register separated from this by nine stages. For example, although the second stage shift register will be described as an example of the remaining even-numbered stage shift registers, the embodiments of the present disclosure are not limited thereto. For example, the reset terminal Reset of the second stage shift register A2 is connected to this and four even stage shift registers (i.e., the fourth stage shift register A4, the sixth stage shift register A6, and the eighth stage shift register A8). , the 10th stage shift register A10) is connected to the output terminal OUT of the lower stage shift register (i.e., the 12th stage shift register A12), or is connected to the output terminal OUT of the 9th stage (i.e., the 3rd stage shift register It is connected to the output terminal OUT of the lower shift register (ie, the 12th stage shift register A12) which is separated by the distance from the shift register A3 to the 11th stage shift register A11.

For example, the reset terminals Reset of the last K (ie, K stages) odd-numbered shift registers are connected to a reset signal line (not shown) to receive a reset signal.

For example, a multi-stage shift register arranged in order includes a plurality of dummy shift registers, and input terminals of N dummy shift registers among the plurality of dummy shift registers are connected to N trigger signal lines. Connected to receive trigger signal.

Due to factors such as the possibility that the output of the shift register unit directly connected to the trigger signal line is unstable, the shift register connected to the trigger signal line may be a dummy shift register. The dummy register is connected to a sub-pixel or to a dummy sub-pixel, which is not used for e.g. to emit light, ie no data signal is written to it.

For example, in the example of FIG. 4, the 8K resolution display may include 4320 rows of sub-pixels and a 4322-stage shift register connected to the 4320 rows of sub-pixels, and connected to the first trigger signal line STV1. The first stage shift register A1 connected to the second trigger signal line STV2 and the second stage shift register A2 connected to the second trigger signal line STV2 are not connected to sub-pixels as dummy shift registers, or the 8K resolution display has 4322 rows. It may include sub-pixels and a shift register connected to the sub-pixels in the 4322nd row, where the sub-pixels in the 4320th row (e.g., 3rd to 4320th rows) are for display, and the remaining 2 rows (e.g., , the first row, and the second row) (connected to the first to second stage dummy shift registers) are dummy sub-pixels and are not used for display (for example, no data signal is input).

For example, in the example shown in FIG. 5, the 8K resolution display may include 4320 rows of sub-pixels and a 4324-stage shift register connected to the 4320 rows of sub-pixels. The first stage shift register A1, the third stage shift register A3, and the second stage shift register A2 and fourth stage shift register A4 connected to the second trigger signal line STV2 are used as sub-dummy shift registers. A display with no pixel connection or 8K resolution may include 4324 rows of sub-pixels and a shift register connected to the 4324 rows of sub-pixels, with 4320 rows (e.g., rows 3 through 4320 The subpixels in the rows) are for display, and the subpixels set in the remaining four rows (for example, the first to fourth rows) (connected to the dummy shift registers in the first to fourth stages) are As a dummy sub-pixel, it is not used for display (for example, no data signal is input).

For example, in the example shown in FIG. 6A, the 8K resolution display may include 4320 rows of sub-pixels and a 4326-stage shift register connected to the 4320 rows of sub-pixels, and the first trigger signal line STV1 is connected to the first trigger signal line STV1. The first stage shift register A1, the third stage shift register A3, and the fifth stage shift register A5 are connected, and the second stage shift register A2 and the fourth stage shift register A2 are connected to the second trigger signal line STV2. Shift register A4 and the sixth stage shift register are dummy shift registers that are not connected to sub-pixels, or in the case of an 8K resolution display, 4326-row sub-pixels and shift registers that are connected to 4326-row sub-pixels. The sub-pixels in 4320 rows (for example, 7th to 4320th rows) are for display, and the sub-pixels set in the remaining 6 rows (for example, 1st to 6th rows) The dummy sub-pixels (connected to the first to sixth dummy shift registers) are not used for display (for example, no data signal is input).

FIG. 6B is similar to FIG. 6A, and the dummy shift registers included in the 8K resolution display are the first to eighth stage shift registers, or the dummy sub-pixels included therein are from the first row to the eighth shift register. This is the 8th line and will not be explained in detail here.

Note that the number of dummy shift registers and the number of rows of dummy sub-pixels may be increased or decreased depending on actual needs, and FIGS. 4 to 6B are only examples of the respective numbers, and the embodiments of the present disclosure do not incorporate this. Not limited.

Hereinafter, dummy shift registers and dummy sub-pixels (that is, multiple rows of sub-pixels connected to this shift register are driven for display by gate scanning signals output from a multi-stage shift register connected to the trigger signal line) Although a case will be described as an example in which no is provided, the embodiments of the present disclosure are not limited to this.

For example, as shown in FIGS. 4 to 6B, the display panel 1 further includes a clock controller 300, and the clock controller 300 is connected to 4K clock signal lines, and the clock controller 300 is connected to an odd number of N sets of gate drive subcircuits. When a clock signal is supplied to a clock signal line connected to a set of gate drive subcircuits, a clock signal is supplied to a clock signal line connected to an even number of gate drive subcircuits among the N sets of gate drive subcircuits. When supplying an invalid clock signal to a clock signal line connected to an even numbered set of gate drive subcircuits and supplying a clock signal to a clock signal line connected to an even numbered set of gate drive subcircuits, The clock signal line connected to the odd set of gate drive subcircuits is configured not to supply a clock signal, or the clock signal line connected to the odd set of gate drive subcircuits is configured to supply an invalid clock signal.

FIG. 7A is a timing schematic diagram corresponding to a display screen of the xth frame according to at least one embodiment of the present disclosure, and FIG. 7B is a schematic diagram of a display screen of the xth frame according to at least one embodiment of the present disclosure. , FIG. 8A is a timing schematic diagram corresponding to a display screen of the x+1 frame according to at least one embodiment of the present disclosure, and FIG. 8B is a schematic diagram of a display screen of the x+1 frame according to at least one embodiment of the present disclosure. be. 7A and 8A are signal timing diagrams corresponding to the gate drive circuit shown in FIG. 4, and the signal timings of the remaining gate drive circuits can be explained in detail with reference to FIGS. 7A to 7B, so they will not be described in detail here. .

For example, if the xth frame (x is an integer greater than or equal to 1) is an odd frame, the x+1st frame is an even frame, and if the xth frame is an even frame, the x+1st frame is an odd frame. Hereinafter, a case will be described in which the x-th frame is an odd-numbered frame and the x+1-th frame is an even-numbered frame, but the embodiments of the present disclosure are not limited to this.

For example, STV1 represents both the first trigger signal line and the first trigger signal, STV2 represents both the second trigger signal line and the second trigger signal, and CLK1 represents both the first clock signal line and the first clock signal. CLK2 represents both the second clock signal line and the second clock signal, CLK3 represents both the third clock signal line and the third clock signal, and CLK4 represents the fourth clock signal line and the fourth clock signal. , G1-Gn represent both the gate scanning signal line and the gate scanning signal connected to the multi-stage shift register arranged in order, Datan represents the data signal, H represents the valid level, and L represents the invalid level.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the x-th frame, the clock signal line (for example, the clock signal line (for example, the 1 clock signal CLK1 and a third clock signal line CLK3), whereby the odd-numbered gate scanning signal lines G1 and G3 of the plurality of gate scanning signal lines output gate scanning signals, For example, output a valid level H and apply a clock signal to the clock signal lines (for example, the second clock signal CLK2 and the fourth clock signal line CLK4) connected to the even numbered set (for example, the second set) of gate drive subcircuits. By supplying an invalid clock signal (for example, a low-level L signal) to the clock signal lines connected to the even-numbered sets of gate drive subcircuits, the even-numbered rows of the plurality of gate scanning signal lines The gate scanning signal lines G2 and G4 output an invalid gate scanning signal (for example, output invalid level L) or do not output the gate scanning signal and are connected to the gate scanning signal lines G1 and G3 of odd-numbered rows. The data transistor in the sub-pixel becomes conductive in response to the valid level H of the gate scanning signal, realizing the writing of the data signal Datan (for example, having a high level), thereby causing even numbers in the screen of the x+1 frame to become conductive. The row sub-pixels are displayed completely white.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the x+1 frame, the clock signal line (for example, the A clock signal is supplied to the second clock signal CLK2 and the fourth clock signal line CLK4), whereby the gate scanning signal lines G2 and G4 of the even numbered rows output a gate scanning signal, for example, output a valid level H, and the gate scanning signal lines G2 and G4 of the even numbered rows output a gate scanning signal. No clock signal is supplied to the clock signal lines (for example, the first clock signal CLK1 and the third clock signal line CLK3) connected to the gate drive subcircuits of the set (for example, the first set), or the clock signal is not supplied to the gate drive subcircuits of the odd number of sets. An invalid clock signal is supplied to the clock signal line connected to the sub-circuit, so that the gate scanning signal lines of odd rows output an invalid gate scanning signal or do not output a gate scanning signal, for example, at an invalid level L. The data transistors connected to the even-numbered gate scanning signal lines G2 and G4 become conductive in response to the effective level H of the gate scanning signal, and write the data signal Datan (for example, having a low level). As a result, sub-pixels in even-numbered rows in the screen of the x+1 frame display completely black.

For example, an invalid level is a signal that prevents a transistor from conducting, and a valid level is a signal that causes a transistor to conduct.

For example, as shown in FIG. 7A, between clock signals (e.g., a first clock signal CLK1 and a third clock signal CLK3) received by two adjacent clock signal lines connected to an odd set of gate drive subcircuits. 8A, and the clock signal received by two adjacent clock signal lines connected to an even set of gate drive subcircuits (e.g., , the second clock signal CLK2 and the fourth clock signal CLK4) have a time difference of 2T. For example, T is the charging time of one row of subpixels.

For example, as shown in FIGS. 4-6B, the clock controller 300 is further connected to the N trigger signal lines and trigger signal lines (eg, first trigger signal line) connected to the odd numbered sets of gate drive subcircuits. STV1), an invalid trigger signal is supplied to the trigger signal line (for example, the second trigger signal line STV2) connected to an even set of gate drive subcircuits, or a valid trigger signal is supplied to the trigger signal line (for example, the second trigger signal line STV2). When supplying an effective trigger signal to the trigger signal line (for example, the second trigger signal line STV2) connected to the even-numbered gate drive sub-circuits, the trigger connected to the odd-numbered gate drive sub-circuits. The signal line (for example, the first trigger signal line STV1) is configured to supply an invalid trigger signal or not to supply a valid trigger signal.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the x-th frame, an effective trigger signal is supplied to the first trigger signal line STV1, thereby causing the outputs a gate scanning signal for every odd row, and supplies an invalid trigger signal or no valid trigger signal to the second trigger signal line STV2, so that the second set of gate drive subcircuits is not activated. In other words, the gate scanning signal is not output.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the x+1 frame, an effective trigger signal is supplied to the second trigger signal line STV2, and thereby outputs a gate scanning signal for every even row, and supplies an invalid trigger signal or no valid trigger signal to the first trigger signal line STV1, so that the first set of gate drive subcircuits is not activated. In other words, the gate scanning signal is not output.

For example, in some examples, an odd number of the N sets of gate drive subcircuits (e.g., the first set of gate drive subcircuits of FIG. 3A or the first set of gate drive subcircuits of FIG. 3B circuit and a second set of gate drive subcircuits) are respectively connected to the subpixels in the odd rows and supply gate scanning signals to the subpixels in the odd rows, and the gate drive subcircuits in the even set of the N gate drive subcircuits The gate drive subcircuits (e.g., the second set of gate drive subcircuits in FIG. 3A or the second set and fourth set of gate drive subcircuits in FIG. 3B) each connect to an even row of subpixels. and supplies gate scanning signals to even-numbered sub-pixels.

For example, in some examples, when driving the pixel array to display the screen of the When driven to display the screen of the x+1 frame, the configuration is such that data signals having the second level are supplied to the plurality of data lines.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the , if the odd row sub-pixels are charged in response to the odd row gate drive signals (e.g. G1, G3, etc.), a data signal having a first level is written and the odd row sub-pixels (e.g. G1, G3, etc.) The first row of sub-pixels R1 and the third row of sub-pixels R3) display completely white, and a specific display screen is shown in FIG. 7B, for example.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the , if the even row subpixels are charged in response to the even row gate drive signals (e.g., G2, G4, etc.), the data signal having the second level is written, and the even row subpixels (e.g., G2, G4, etc.) are written. The sub-pixel R2 in the second row and the sub-pixel R4 in the fourth row display completely black, and a specific display screen is shown in FIG. 8B, for example.

Note that when driving the pixel array to display the screen of the If a sub-pixel is charged in response to an odd-numbered row gate drive signal (e.g., G1, G3, etc.), a data signal having a second level is written to the odd-numbered row sub-pixel (e.g., first row sub-pixel). The pixel R1 and the sub-pixel R3 in the third row display completely black, and a specific display screen is shown in FIG. 8B, for example. When driving the pixel array to display the screen of the When charged in response to the gate drive signals (e.g., G2, G4, etc.) of the sub-pixels of the even rows (e.g., the sub-pixels R2 of the second row and the fourth The sub-pixel R4) of the row displays completely white, and the specific display screen is shown in FIG. The rows may be displayed as an alternating black and white display screen, and the embodiments of the present disclosure are not limited thereto.

For example, based on the above driving, it is possible to obtain a display screen in the x-th frame in which the sub-pixels in odd-numbered rows display all white, and a display screen in the x+1-th frame in which the sub-pixels in even-numbered rows display all black. Of course, the display screen may be the x-th frame in which the sub-pixels in even-numbered rows display all white, and the display screen in the x+1-th frame in which the sub-pixels in odd-numbered rows display all black.

According to the human visual persistence effect, the display screen of the x-th frame in which the sub-pixels in the odd-numbered rows display completely white as shown in FIG. 7B and the display screen in the x+1 frame in which the sub-pixels in the even-numbered rows display completely black as shown in FIG. 8B. Based on this, the human eye sees a clear H-1line screen shown in Figure 1C, whereby the odd frames cooperate with the data signal to display the odd lines, and the even frames cooperate with the data signal to display the even lines. H-1Line screen can be displayed clearly, there is no line shift problem, and it meets industry CM value test standards, improving the performance of display products.

For example, in the embodiment of the present disclosure, when outputting an odd/even gate scanning signal, H-1 Line is realized by combining it with the level of the data signal Datan and supplying it to a white/black screen. For example, in an odd-numbered frame: the first level of the first trigger signal line STV1 + the gate scanning signal output of the odd-numbered rows + the data signal Datan is supplied to the white screen, the sub-pixels of the odd-numbered rows display white, and after this frame ends, the even-numbered The sub-pixels in the row retain the previous data, and even frame: the second level of the second trigger signal line STV2 + the gate scanning signal output of the even-numbered rows + the second level of the data signal Datan is supplied to the black screen, and the sub-pixels of the even-numbered row After the pixel displays black and this frame ends, the sub-pixels in the odd rows retain their previous data. By combining even frame data and odd frame data, the subpixel can clearly display the H-1 line screen shown in FIG. 1C.

FIG. 9A is a schematic diagram of the positional relationship of gate drive circuits according to at least one embodiment of the present disclosure, and FIG. 9B is a schematic diagram of the positional relationship of another gate drive circuit according to at least one embodiment of the present disclosure.

For example, in some examples, as shown in FIG. 9A, the gate drive circuit 10 is located on one side of a pixel array (e.g., within the display area 40), and each stage of shift register units each has a row of sub-pixels. The sub-pixels in the row are connected to the sub-pixels in order to drive the sub-pixels in the row (for example, write a data signal).

For example, in some other examples, as shown in FIG. 9B, the gate drive circuit 10 is located on both sides of the pixel array to achieve dual-side drive, and embodiments of the present disclosure The arrangement method is not limited. For example, shift registers located in the same stage among gate drive circuits located on both sides drive sub-pixels in the same row. For example, as shown in FIG. 9B, gate drive circuits located on both sides have the same structure and operating principle, and shift registers located at the same stage drive sub-pixels in the same row. For example, the first-stage shift register units GOA1 located on both sides are both connected to the sub-pixels in the first row and drive the first-stage sub-pixels, and the second-stage shift register units GOA1 located on both sides are connected to the sub-pixels in the first row. are both connected to the second row of sub-pixels and drive the second row of sub-pixels, thereby making an analogy. Thereby, the driving load on the gate scanning signal line can be reduced and the driving ability of the gate driving circuit can be increased.

For example, the structure and operation principle of the shift register and the sub-pixel may adopt the design in this field, for example, the sub-pixel includes a pixel driving circuit and a light-emitting element, the pixel driving circuit may be 4T1C, 4T2C, 7T1C, etc., the light-emitting element may be an organic light-emitting diode or a quantum dot light-emitting diode, etc., which will not be described in detail here. The embodiments of the present disclosure are not limited thereto.

In embodiments of the present disclosure, an odd numbered set of trigger signal lines (e.g., first trigger signal line STV1) is connected to an odd numbered set of gate drive subcircuits (e.g., first clock signal line CLK1 or third trigger signal line STV1). It operates in cooperation with the clock signal line CLK3), thereby realizing the on/off of the shift register of even rows, and in cooperation with the first level or second level of the data signal Datan, the odd rows of the entire frame are turned on and off. All-black or all-white display is displayed, and even-numbered sets of trigger signal lines (e.g., second trigger signal line STV2) are connected to even-numbered sets of gate drive subcircuits (e.g., second clock signal line CLK2 or second trigger signal line). It operates in cooperation with the 4 clock signal line CLK4) to turn on and off the shift registers in the odd rows, and in cooperation with the second level or first level of the data signal Datan, the even rows of the entire frame are completely white. Or display all black, that is, the high level and low level of the data signal Datan corresponding to the odd and even frames are opposite, thereby achieving the CM value of the H-1 Line display screen ≒ 100%, Meets industry testing standards. That is, by using the signal framing display technology, odd frames display odd lines, and even frames display even lines, thus avoiding the problem of line shift on the display screen that combines bright and dark lines.

Note that in the display panel according to the embodiment of the present disclosure, the framing drive technique (for example, the technique of displaying odd lines in the above-mentioned odd frames and displaying even lines in the even frames) is effective in preventing line deviations on the H-1 Line display screen. It is not limited to solving the problem, but may be used to solve all problems of display screens that combine bright and dark lines (see Figure 9C), and if a line-like display screen is detected, the block Framing through ranking (e.g., blanking even rows in odd frames and blanking odd rows in even frames) doubles the pixel charging time and solves the line shift problem. It is also possible to lower the resolution of the display panel and improve the refresh rate of the display panel. For example, according to this framing display, when two sets of gate drive subcircuits are included, in driving the display screen for each frame, In response to the trigger signals on the two trigger signal lines, the two gate scanning signal lines simultaneously output gate scanning signals to drive two rows of sub-pixels, thereby improving the refresh rate of the display panel. For example, the resolution of the display panel can be lowered from 8K to 4K and the refresh rate can be increased from 120Hz to 240Hz, so that the odd row data signal Datan (e.g., in Figure 7A According to this framing technique, the data signal Datan (e.g., the high level shown in FIG. 8A) of the even row is displayed as an odd frame, and the data signal Datan (e.g., the low level shown in FIG. 8A) of the even row is displayed as an even frame. This solves the problem of H-1 line misalignment in products with a short charging time T for sub-pixels in one row, such as those with a resolution of 4K and a refresh rate of 240Hz, making it possible to increase the number of applications for display panels.

FIG. 9C is a schematic diagram of a combined bright and dark line display screen according to at least one embodiment of the present disclosure. For example, as shown in FIG. 9C, the original image can be obtained by combining the odd frame display screen and the even frame display screen, and the specific driving timing is similar to the driving timing according to FIGS. 7A and 8A. Therefore, I will not explain it in detail here.

For example, at least one embodiment of the present disclosure also provides a display device. FIG. 10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. For example, as shown in FIG. 10, the display device 100 includes a display panel 1 according to any embodiment of the present disclosure.

Note that the display device 100 of this embodiment can be any device having a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet, a laptop, a digital frame, a navigator, etc. It may be a product or a member. The display device 100 may include other common components such as a display panel, and the embodiments of the present disclosure are not limited thereto.

For the technical effects of the display device 100 according to the embodiments of the present disclosure, please refer to the corresponding description of the display panel in the above embodiments, and therefore will not be described in detail here.

Note that for clarity and brevity, all structures of the display device 100 are not shown. In order to realize the essential functions of the display device, those skilled in the art may install other structures not shown according to the specific application scene, and the embodiments of the present disclosure do not limit this.

At least one embodiment of the present disclosure also provides a method of driving a display panel, for example, the display panel may be the display panel shown in FIG. 2 or any other display panel in the art. Well, the embodiments of this disclosure are not limiting.

Hereinafter, a method for driving the display panel shown in FIG. 2 will be described as an example, but methods for driving display panels having other structures are similar to this, and therefore will not be described in detail here.

For example, as shown in FIG. 2, the display panel 1 includes a pixel array (located in the display area 40, for example) and a plurality of gate scanning signal lines GL, and the pixel array includes sub-pixels arranged in multiple rows and multiple columns. 410, a plurality of gate scanning signal lines GL are connected to a plurality of rows of sub-pixels 410.

FIG. 11 is a flowchart of a method for driving a display panel according to at least one embodiment of the present disclosure. For example, as shown in FIG. 11, the driving method includes step S110 and step S120.

Step S110: When driving the pixel array to display the screen of the The even-numbered gate scan signal lines among the lines output invalid gate scan signals or do not output the gate scan signals.

For example, in some examples, as shown in FIGS. 4-6B, odd rows of gate scan signal lines (e.g., gate scan signal lines G1, G3, G5, etc.) also have odd sets of gate drive subcircuits (e.g., , the first set of gate drive subcircuits), and the even rows of gate scan signal lines (e.g., gate scan signal lines G2, G4, G6, etc.) are also connected to the even numbered gate drive subcircuits (e.g., the second set of gate drive subcircuits). gate drive subcircuit).

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the x-th frame, the clock signal line (for example, the clock signal line (for example, the 1 clock signal CLK1 and a third clock signal line CLK3), whereby the odd-numbered gate scanning signal lines G1 and G3 of the plurality of gate scanning signal lines output gate scanning signals, For example, output a valid level H and apply a clock signal to the clock signal lines (for example, the second clock signal CLK2 and the fourth clock signal line CLK4) connected to the even numbered set (for example, the second set) of gate drive subcircuits. By supplying an invalid clock signal (for example, a low-level L signal) to the clock signal lines connected to the even-numbered sets of gate drive subcircuits, the even-numbered rows of the plurality of gate scanning signal lines The gate scanning signal lines G2 and G4 output an invalid gate scanning signal (for example, output invalid level L) or do not output the gate scanning signal and are connected to the gate scanning signal lines G1 and G3 of odd-numbered rows. The data transistor in the sub-pixel becomes conductive in response to the valid level H of the gate scanning signal to realize the writing of the data signal Datan (for example, having a high level), thereby causing the odd number in the screen of the The row sub-pixels are displayed completely white.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the (For example, the time difference between the first clock signal CLK1 and the third clock signal CLK3) is 2T (T=t1 or t2), and for example, T is the charging time of one row of sub-pixels.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the A valid trigger signal is supplied to the trigger signal line STV1), and an invalid trigger signal is supplied to the trigger signal line (for example, a second trigger signal line STV2) connected to an even number of gate drive subcircuits, or a valid trigger signal is supplied to the trigger signal line STV1). The method further includes the step of not supplying.

For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the x-th frame, an effective trigger signal is supplied to the first trigger signal line STV1, and thereby The sub-circuit outputs a gate scanning signal (for example, the first row G1, the third row G3) for every odd row, and supplies an invalid trigger signal to the second trigger signal line STV2 or does not supply a valid trigger signal. , thereby causing the second set of gate drive subcircuits to be inactive, ie, not outputting gate scanning signals.

For example, when the display panel 1 further includes data lines electrically connected to multiple columns of sub-pixels, the driving method may be used to drive the pixel array to display the screen of the x-th frame. The method further includes providing a first level to the line. For example, as shown in FIG. 7A, when driving the pixel array to display the screen of the , if the odd row sub-pixels are charged in response to the odd row gate drive signals (e.g. G1, G3, etc.), a data signal having a first level is written and the odd row sub-pixels (e.g. G1, G3, etc.) The first row of sub-pixels R1 and the third row of sub-pixels R3) display completely white, and a specific display screen is shown in FIG. 7B, for example.

Step S120: When driving the pixel array to display the screen of the , or do not output the gate scanning signal.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the x+1 frame, the clock signal line (for example, the A clock signal is supplied to the second clock signal CLK2 and the fourth clock signal line CLK4), whereby the gate scanning signal lines G2 and G4 of the even numbered rows output a gate scanning signal, for example, output a valid level H, and the gate scanning signal lines G2 and G4 of the even numbered rows output a gate scanning signal. No clock signal is supplied to the clock signal lines (for example, the first clock signal CLK1 and the third clock signal line CLK3) connected to the gate drive subcircuits of the set (for example, the first set), or the clock signal is not supplied to the gate drive subcircuits of the odd number of sets. An invalid clock signal is supplied to the clock signal line connected to the sub-circuit, so that the gate scanning signal line in the odd rows outputs an invalid gate scanning signal or does not output a gate scanning signal, for example, at an invalid level. As a result, the data transistors in the sub-pixels connected to the even-numbered gate scanning signal lines G2 and G4 become conductive in response to the valid level H of the gate scanning signal, and the data signal Datan (for example, As a result, the sub-pixels in even-numbered rows in the screen of the x+1th frame display completely black.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the (For example, the time difference between the second clock signal CLK2 and the fourth clock signal CLK4) is 2T.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the A valid trigger signal is supplied to the trigger signal line STV2), and an invalid trigger signal is supplied to the trigger signal line (for example, the first trigger signal line STV1) connected to the odd set of gate drive subcircuits, or a valid trigger signal is supplied to the trigger signal line STV2); The method further includes the step of not providing a signal.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the x+1 frame, an effective trigger signal is supplied to the second trigger signal line STV2, and thereby starts outputting a gate scanning signal (for example, the second row G2, the fourth row G4) every even numbered rows, and supplies an invalid trigger signal to the first trigger signal line STV1 or does not supply a valid trigger signal, As a result, the first set of gate drive subcircuits are inactive, ie, do not output gate scanning signals.

For example, when the display panel 1 further includes data lines electrically connected to multiple columns of sub-pixels, the driving method may be used to drive the pixel array to display the screen of the x+1 frame. The method further includes providing a second level to the line.

For example, as shown in FIG. 8A, when driving the pixel array to display the screen of the , if the even row subpixels are charged in response to the even row gate drive signals (e.g., G2, G4, etc.), the data signal having the second level is written, and the even row subpixels (e.g., G2, G4, etc.) are written. The second row of sub-pixels R2 and the fourth row of sub-pixels R4) display completely black, and a specific display screen is shown in FIG. 8B, for example.

For example, based on the above driving, it is possible to obtain a display screen in the x-th frame in which the sub-pixels in odd-numbered rows display all white, and a display screen in the x+1-th frame in which the sub-pixels in even-numbered rows display all black. Of course, the display screen may be the x-th frame in which the sub-pixels in even-numbered rows display all white, and the display screen in the x+1st frame in which the sub-pixels in odd-numbered rows display all black. It may be determined accordingly, and the odd-numbered rows and even-numbered rows of the display screen of two adjacent frames may be displayed as a display screen in which black and white are alternated, and the embodiments of the present disclosure are not limited to this.

According to the human visual persistence effect, the display screen of the x-th frame in which the sub-pixels in the odd-numbered rows display completely white as shown in FIG. 7B and the display screen in the x+1 frame in which the sub-pixels in the even-numbered rows display completely black as shown in FIG. 8B. Based on this, the human eye sees a clear H-1line screen shown in Figure 1C, whereby the odd frames cooperate with the data signal to display the odd lines, and the even frames cooperate with the data signal to display the even lines. H-1Line screen can be displayed clearly, there is no line shift problem, and it meets industry CM value test standards, improving the performance of display products.

The technical effects and working principles of the display panel driving method according to the embodiments of the present disclosure can be explained in detail with reference to the corresponding description of the display panel in the embodiments above, and will not be described in detail here.

Additionally, the following should be explained:
(1) The drawings of the embodiments of the present disclosure relate only to structures according to the embodiments of the present disclosure, and other structures may refer to conventional designs.
(2) Unless there is a contradiction, the embodiments of the present disclosure and the features of the embodiments can be combined with each other to obtain new embodiments.

The foregoing are exemplary embodiments of the present disclosure and do not limit the patentable scope of the present disclosure, which is defined by the appended claims.

Claims (20)

A display panel including a gate drive circuit,
The gate drive circuit includes sequentially arranged multi-stage shift registers, the sequentially arranged multi-stage shift registers are combined into N sets of gate drive subcircuits, and the N sets of gate drive subcircuits include: The shift registers are each cascaded,
The mth set of gate drive subcircuits of the N sets of gate drive subcircuits includes an mth stage shift register and an m+L*N stage shift register that are cascade-connected;
m is an integer greater than or equal to 1 and less than or equal to N; L is an integer greater than or equal to 1; and N is an even number greater than or equal to 2. further comprising N trigger signal lines each connected to the N sets of gate drive subcircuits;
2. The display panel according to claim 1, wherein the mth trigger signal line among the N trigger signal lines is connected to an input terminal of an mth stage shift register. Further includes 4K clock signal lines,
The 4K clock signal lines include first to fourth K clock signal lines that are each connected to a clock signal terminal of the multi-stage shift register and supply a clock signal,
3. The display panel according to claim 2, wherein K is an integer of 1 or more. When K=1, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line,
The first clock signal line is connected to the clock signal terminal of the 4n-3 stage shift register, the second clock signal line is connected to the clock signal terminal of the 4n-2 stage shift register, and the third clock signal line is connected to the clock signal terminal of the 4n-2 stage shift register. the signal line is connected to a clock signal terminal of a 4n-1 stage shift register, the fourth clock signal line is connected to a clock signal terminal of a 4n stage shift register,
4. The display panel according to claim 3, wherein n is an integer of 1 or more. When K=3, the 4K clock signal lines are a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line. , a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line,
The first clock signal line is connected to the clock signal terminal of the 12n-11th stage shift register, the second clock signal line is connected to the clock signal terminal of the 12n-10th stage shift register, and the third clock signal line is connected to the clock signal terminal of the 12n-11th stage shift register. The signal line is connected to the clock signal terminal of the 12n-9 stage shift register, the fourth clock signal line is connected to the clock signal terminal of the 12n-8 stage shift register, and the fifth clock signal line is connected to the clock signal terminal of the 12n-8 stage shift register. The sixth clock signal line is connected to the clock signal terminal of the 12n-7 stage shift register, the sixth clock signal line is connected to the clock signal terminal of the 12n-6 stage shift register, and the seventh clock signal line is connected to the 12n-5 stage shift register. The eighth clock signal line is connected to the clock signal terminal of the 12n-4th stage shift register, and the ninth clock signal line is connected to the clock signal terminal of the 12n-3th stage shift register. The tenth clock signal line is connected to a clock signal terminal of a 12n-2 stage shift register, and the eleventh clock signal line is connected to a clock signal terminal of a 12n-1 stage shift register. connected, the twelfth clock signal line is connected to a clock signal terminal of a 12nth stage shift register,
4. The display panel according to claim 3, wherein n is an integer of 1 or more. When N=2, the N trigger signal lines include a first trigger signal line and a second trigger signal line,
The first trigger signal line is connected to the input terminals of the first K odd stage shift registers to supply the first trigger signal, and the input terminals of each of the remaining odd stage shift registers are connected to this and K-1. connected to the output terminal of the upper shift register that is separated by an odd number of stages.
The second trigger signal line is connected to the input terminals of the first K even stage shift registers to supply a second trigger signal, and the input terminals of each of the remaining even stage shift registers are connected to this and K-1. 6. The display panel according to claim 3, wherein the display panel is connected to an output terminal of an upper stage shift register that is separated by an even number of stages. further includes a clock controller;
The clock controller is connected to the 4K clock signal lines,
When supplying a clock signal to a clock signal line connected to an odd number of gate drive subcircuits among the N sets of gate drive subcircuits, the gate drive of an even number of the N sets of gate drive subcircuits is performed. not supplying the clock signal to the clock signal line connected to the sub-circuit, or supplying an invalid clock signal to the clock signal line connected to the even-numbered set of gate drive sub-circuits;
When supplying the clock signal to the clock signal line connected to the even-numbered set of gate drive sub-circuits, the clock signal is not supplied to the clock signal line connected to the odd-numbered set of gate drive sub-circuits, or 7. The display panel according to claim 6, configured to supply the invalid clock signal to clock signal lines connected to the odd-numbered sets of gate drive subcircuits. a time difference between clock signals received by two adjacent clock signal lines connected to the odd set of gate drive subcircuits is 2T;
a time difference between clock signals received by two adjacent clock signal lines connected to the even set of gate drive subcircuits is 2T;
8. The display panel according to claim 7, wherein T is a charging time of one row of sub-pixels. The clock controller is further connected to the N trigger signal lines,
When supplying a valid trigger signal to the trigger signal line connected to the odd-numbered set of gate drive sub-circuits, an invalid trigger signal is supplied to the trigger signal line connected to the even-numbered set of gate drive sub-circuits, or not providing the valid trigger signal;
When supplying the valid trigger signal to the trigger signal lines connected to the even-numbered sets of gate drive sub-circuits, supply the invalid trigger signal to the trigger signal lines connected to the odd-numbered sets of gate drive sub-circuits; 9. The display panel according to claim 7 or 8, wherein the display panel is configured to provide no valid trigger signal. further comprising a pixel array connected to the gate drive circuit,
The pixel array includes sub-pixels in multiple rows and multiple columns,
Odd-numbered sets of gate drive sub-circuits among the N sets of gate drive sub-circuits are each connected to sub-pixels in odd-numbered rows,
10. The display panel according to claim 1, wherein even-numbered sets of gate drive sub-circuits among the N sets of gate drive sub-circuits are respectively connected to sub-pixels in even-numbered rows. further including a data drive circuit and multiple data lines;
The plurality of data lines are electrically connected to the plurality of columns of subpixels and configured to transmit data signals supplied by the data drive circuit to the plurality of columns of subpixels,
The data driving circuit includes:
When driving the pixel array to display the screen of the x-th frame, supplying a data signal having a first level to the plurality of data lines;
When driving the pixel array to display the x+1 frame screen, the pixel array is configured to supply a data signal having a second level to the plurality of data lines,
The display panel according to claim 10, wherein x is an integer of 1 or more. 12. The display panel according to claim 10, wherein the gate drive circuit is located on one side of the pixel array. 12. The display panel according to claim 10, wherein the gate drive circuits are located on both sides of the pixel array, and shift registers at the same stage in the gate drive circuits located on both sides drive sub-pixels in the same row. The multi-stage shift registers arranged in order include a plurality of dummy shift registers, and the input terminals of the N-stage dummy shift registers among the plurality of dummy shift registers are each connected to the N trigger signal lines for triggering. The display panel according to any one of claims 2 to 13, which receives a signal. A display device comprising the display panel according to claim 1. The display panel includes a pixel array and a plurality of gate scanning signal lines, the pixel array includes subpixels arranged in multiple rows and columns, and each of the plurality of gate scanning signal lines is connected to the plurality of rows of subpixels. ,
When driving the pixel array to display the screen of the x-th frame, the odd-numbered gate scanning signal lines of the plurality of gate scanning signal lines output gate scanning signals, Outputting an invalid gate scanning signal or not outputting the gate scanning signal from an even-numbered gate scanning signal line among the lines;
When driving the pixel array to display the x+1 frame screen, the even-numbered gate scanning signal lines output the gate scanning signal, and the odd-numbered gate scanning signal lines output the invalid gate scanning signal. or not outputting the gate scanning signal,
A display panel driving method in which x is an odd number of 1 or more. The odd-numbered rows of gate scanning signal lines are further connected to odd-numbered sets of gate drive subcircuits, and the even-numbered rows of gate scanning signal lines are further connected to even-numbered sets of gate drive subcircuits;
When driving the pixel array to display the screen of the x-th frame, a clock signal is supplied to the clock signal line connected to the odd-numbered set of gate drive sub-circuits, and the clock signal line connected to the even-numbered set of gate drive sub-circuits is supplied. not supplying the clock signal to the clock signal line, or supplying an invalid clock signal to the clock signal line;
When driving the pixel array to display the screen of the 17. The driving method according to claim 16, wherein the clock signal is not supplied to the clock signal line that is used, or the invalid clock signal is supplied to the clock signal line. When driving the pixel array to display the screen of the x-th frame, the time difference between the clock signals supplied by two adjacent clock signal lines connected to the odd-numbered sets of gate drive subcircuits is 2T. ,
When driving the pixel array to display the screen of the ,
18. The driving method according to claim 17, wherein T is a charging time of one row of sub-pixels. When driving the pixel array to display the screen of the x-th frame, an effective trigger signal is supplied to a trigger signal line connected to the odd-numbered set of gate drive sub-circuits, and connected to the even-numbered set of gate drive sub-circuits. supplying an invalid trigger signal or not supplying a valid trigger signal to the trigger signal line that is
When driving the pixel array to display the screen of the 19. The driving method according to claim 17 or 18, further comprising the step of supplying an invalid trigger signal or not supplying a valid trigger signal to the trigger signal line. The display panel further includes a data line electrically connected to the plurality of columns of sub-pixels,
When driving the pixel array to display the screen of the x-th frame, supplying a first level to the plurality of data lines;
20. The driving according to claim 16, further comprising the step of supplying a second level to the plurality of data lines when driving the pixel array to display the screen of the x+1 frame. Method.

Images