JP2009103914A - Driving circuit of liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit of a liquid crystal display device capable of inexpensively performing interlace/progressive conversion without using a frame memory or a line memory. <P>SOLUTION: The original image data of television broadcast are transmitted as interlaced. The interlaced image data are transmitted as divided into image data in odd-numbered frames and image data in even-numbered frames. A driving circuit of a liquid crystal display device receiving the interlaced image data displays image data of odd-numbered frames by scanning only odd-numbered lines in odd-numbered frames, and displays image data of even-numbered frames by scanning only even-numbered lines in even-numbered frames. Each pixel of the liquid crystal display device includes a memory element (e.g. a storage capacitor) for holding the written image data, and its memory effect is used for interlace/progressive conversion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drive circuit for a liquid crystal display device, and more particularly to a drive circuit for a liquid crystal display device having an interlace / progressive conversion function.

  The scanning method of television broadcasting is performed by an interlace method in which a plurality of horizontal scanning lines constituting a screen are operated by skipping at a predetermined interval. By the way, in the liquid crystal display device, the video signal is displayed by the progressive method. Therefore, when displaying an interlaced video signal on a liquid crystal display device, it is necessary to convert the interlaced video signal into a progressive video signal.

Conventionally, when interlace / progressive conversion is performed, a method of using a frame memory as a memory having a large storage capacity is known (Patent Document 1). Further, a method of performing double speed scanning using a line memory is known (Patent Document 2).
JP 2007-108287 A JP 2005-286746 A

  However, the method using a frame memory as described above and the method of performing double speed scanning using a line memory cause a cost increase.

The present invention relates to a driving circuit for a liquid crystal display device in which a plurality of pixels having memory elements for holding image data are arranged in a matrix to form a plurality of lines and receive and display interlaced image data. ,
A scanning circuit is provided that outputs scanning signals to even lines in even frames and outputs scanning signals to odd lines in odd frames.

  According to the present invention, it is possible to perform interlace / progressive conversion at low cost without using a frame memory or a line memory.

  Embodiments of the present invention will be described below with reference to the drawings. First, the basic configuration of the present invention will be described with reference to FIG.

  As shown in FIG. 1A, the original image data of the television broadcast is interlaced and transmitted. The interlaced image data is divided into the odd frame image data shown in FIG. 1B and the even frame image data shown in FIG. 1C and transmitted.

  As shown in FIG. 1D, the liquid crystal display device that has received such interlaced image data scans and displays only odd-numbered lines in odd-numbered frames. Further, as shown in FIG. 1E, for even frame image data, only even lines are scanned and displayed in the even frame. The odd lines correspond to the pixel rows arranged on the odd-numbered lines (first line, third line, fifth line,...) On the liquid crystal panel, and the even-numbered lines (second line, fourth line). , 6th line,...) Corresponds to pixel columns arranged in even-numbered lines on the liquid crystal panel.

  Each pixel of the liquid crystal display device is provided with a memory element (for example, a storage capacitor) that holds written image data, and the memory effect is used for interlace / progressive conversion. That is, in the odd-numbered frame, the image that has been scanned and written in the previous even-numbered frame remains on the even-numbered line that has not been scanned due to the memory effect. Since an image scanned and written in the immediately preceding odd-numbered frame remains due to the memory effect, interlace / progressive conversion is performed as shown in FIG. Thus, since the liquid crystal display device itself is used as a memory, a frame memory and a line memory are not necessary.

  Next, a specific configuration of the driving circuit of the liquid crystal display device according to the embodiment of the present invention will be described. As shown in FIG. 2, source lines SL1 and SL2 and gate lines GL1 to GL3 are provided, and a plurality of pixels PX are arranged in a matrix corresponding to their intersections. In this example, only the matrix portion of 3 rows × 2 columns is shown, but in an actual liquid crystal panel, a larger number of pixels PX are arranged in the same configuration. Each pixel PX includes a TFT 10 that is a switching element and a storage capacitor 11 that is an example of a “memory element”.

  The source 10 s of the TFT 10 is connected to the corresponding source lines SL 1 and SL 2, the gate is connected to the corresponding gate lines GL 1 to GL 3, and the drain 10 d is connected to the pixel electrode 13. The storage capacitor 11 is connected between the pixel electrode 13 and the common electrode 14, has the pixel electrode 13 and the common electrode 14 as capacitor electrodes, and has a capacitor insulating film formed between these electrodes. Instead of such a storage capacitor 11, a static memory may be used.

  The common electrode 14 is formed on the surface of a counter substrate (not shown) provided to face the TFT substrate on which the TFT 10 is formed. Further, the liquid crystal 12 is disposed between the pixel electrode 13 and the common electrode 14. A common potential signal MOUT is applied to the common electrode 14.

  The gate driver 20 that is a scanning circuit outputs scanning signals 1, 2, and 3 to the gate lines GL1 to GL3, respectively. In the present invention, only scan signals 1, 3, 5,... Corresponding to odd lines are generated in odd frames, and scan signals 2, 4, 6,... Corresponding to even lines are generated in even frames.・ Only generate. Since the scanning of the gate driver 20 is sequential scanning, a shift register as shown in FIG. 3 is used. Specifically, shift registers SR1 to SR5 are connected in series, a vertical start pulse STV is input to the first-stage shift register SR1, and a vertical clock VCLK is input to each shift register SR1 to SR5 as a shift clock. Then, in synchronization with the rising edge of the vertical clock VCLK, the vertical start pulse STV is sequentially shifted (transferred) to the next shift register.

  A mask circuit is used to provide an invalid period for invalidating all the scanning signals when the scanning lines are switched. That is, AND circuits 21 to 25 are provided corresponding to the shift registers SR1 to SR5, and output signals (shift signals of the vertical start pulse STV) of the corresponding shift registers SR1 to SR5 are input to the AND circuits 21 to 25. The inverted signal of the mask signal GOEX is input in common. The AND circuits 21 to 25 output scanning signals 1, 2, and 3 (in this case, vertical scanning signals) corresponding to the gate lines GL1 to GL3. The mask signal GOEX is a pulse signal, and during the generation period of the mask signal GOEX, the outputs of the AND circuits 21 to 25 are at the L level, and all the scanning signals are invalidated.

  In addition, the source driver 30 sequentially outputs image data Vsig (image data interlaced in the present invention) coming from the outside to the source lines SL1 and SL2. Therefore, a shift register is used for the source driver 30. That is, the horizontal start pulse STH is sequentially shifted (transferred) in synchronization with the rising edge of the horizontal clock HCLK, which is a shift clock. Further, a horizontal switch is provided for each of the source lines SL1 and SL2, and the horizontal switch is turned on according to a scanning signal (in this case, a horizontal scanning signal) from the shift register, so that the image data Vsig is supplied to the source lines SL1 and SL2. It will be output sequentially.

  The operation of the source driver 30 described above is dot sequential scanning, but line sequential scanning can also be adopted. Line sequential scanning is a scanning method in which image data Vsig for one line is temporarily stored by a latch circuit or the like and is simultaneously output to the source lines SL1 and SL2.

  The timing controller 40 generates the vertical start pulse STV, the vertical clock VCLK, the mask signal GOEX, the horizontal start pulse STH, the horizontal clock HCLK, and the common potential signal MOUT. The gate driver 20, the source driver 30, and the timing controller 40 may be formed on the TFT substrate together with the plurality of pixels PX, or may be incorporated in an LSI different from the TFT substrate.

  In the present invention, the scan by the gate driver 20 scans the odd lines in the odd frames, and scans the even lines in the even frames. In the odd frames, the even lines are scanned during the invalid period of the scan signal. Odd line scanning is performed during the invalid period of the scanning signal. This is realized by shifting the data of the shift registers SR1 to SR5 during the invalid period.

  The invalid period is set to the same time as normal sequential scanning, and the invalid period is controlled to be shifted in a shorter time (within the invalid period) than the normal timing, thereby reducing the writing time of the image data to the pixel PX. Without reduction, double speed scanning and the accompanying line memory are not required.

  Hereinafter, the driving circuit scanning method according to the present invention will be described in detail while comparing with a normal scanning method. FIG. 5 is a diagram showing a normal scanning method, and FIG. 4 is a diagram showing a scanning method according to the invention. In the normal scanning method, as shown in FIG. 5, the vertical start pulse STV is shifted in synchronization with the rising edge of the vertical clock VCLK, and an output signal having a constant pulse width is obtained from each of the shift registers SR1 to SR5. The vertical clock VCLK is a clock that repeats the H level and the L level at a constant cycle. Then, before and after the transition of the output signals of the shift registers SR1 to SR5, an invalid period is set by the generation of the mask signal GOEX. Thereby, the scanning signals 1, 2, 3, 4, 5 are set so as not to overlap each other. A corresponding line is selected in accordance with the scanning signals 1, 2, 3, 4, and 5, and display is performed by the image data Vsig being written by the source driver 30 to the pixel PX of the selected line. .

  According to the scanning method of the present invention, as shown in FIG. 4, the waveform of the vertical clock VCLK is different from the normal scanning method. The vertical clock VCLK includes a first clock having a short pulse width (the H level period is relatively short) and a second clock having a pulse width longer than the first clock (the H level period is relatively long). The first clock and the second clock are alternately repeated at the same cycle. The H level period of the first clock is included in the invalid period.

In the odd-numbered frame, as shown in FIG. 4A, the vertical start pulse STV is generated after the rise of the first clock and before the rise of the second clock. (See the arrow in the figure)
Then, the vertical start pulse STV is shifted based on the rising edge of the second clock, and the shifted signal appears as an output signal of the shift register SR1. The output signal of the shift register SR1 is shifted based on the rising edge of the first clock by the shift register SR2 at the next stage. Since the H level of the first clock is included in the invalid period, the output signal of the shift register SR2 (H level pulse signal) is included in the invalid period. The output signal of the shift register SR2 is shifted based on the rising edge of the second clock by the shift register SR3 at the next stage. The following is this repetition.

  According to the scanning method described above, all the output signals of the even-numbered shift registers SR2, SR4,... Are included in the invalid period. The output signals of the even-numbered shift registers SR2, SR4,... Are masked by the AND circuits 22, 24,. Therefore, in the odd frame, only the scanning signals 1, 3, 5,... Corresponding to the odd lines are generated, so that only the odd lines are scanned. A corresponding line is selected according to the scanning signals 1, 3, and 5, and display is performed by the image data Vsig being written by the source driver 30 to the pixel PX of the selected line.

  On the other hand, in the even frame, as shown in FIG. 4B, the vertical start pulse STV is generated before the rising of the first clock. As a result, the vertical start pulse STV is shifted based on the rising edge of the first clock, and the shifted signal appears as an output signal of the shift register SR1. Since the H level of the first clock is included in the invalid period, the output signal (H level pulse signal) of the shift register SR1 is included in the invalid period. The output signal of the shift register SR1 is shifted based on the rising edge of the second clock by the shift register SR2 at the next stage.

  The output signal of the shift register SR2 is shifted based on the rising edge of the first clock by the shift register SR3 at the next stage. Since the H level of the first clock is included in the invalid period, the output signal of the shift register SR3 (H level pulse signal) is included in the invalid period. The output signal of the shift register SR3 is shifted based on the rising edge of the second clock by the shift register SR4 at the next stage. The following is a repetition of this.

According to the above scanning method, the output signals of the odd-numbered shift registers SR1, SR3,... Are all included in the invalid period. The output signals of the odd-numbered shift registers SR1, SR3,... Are masked by the AND circuits 21, 23,. Therefore, in the even frame, only the scanning signals 2, 4, 6,... Corresponding to the even lines are generated, so that only the even lines are scanned.

A corresponding line is selected according to the scanning signals 2, 4, and 6, and display is performed by the image data Vsig being written by the source driver 30 to the pixel PX of the selected line.

It is a figure explaining the interlace / progressive conversion by embodiment of this invention. It is a figure which shows the structure of the drive circuit of the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of a gate driver. It is a figure which shows the scanning method of the drive circuit of the liquid crystal display device by embodiment of this invention. It is a figure which shows the scanning method of the drive circuit of the conventional liquid crystal display device.

Explanation of symbols

10 TFT
10s source 10d drain 11 holding capacitor 12 liquid crystal 13 pixel electrode 14 common electrode 20 gate driver 21-25 AND circuit 30 source driver 40 timing controller SL1, SL2 source line GL1-GL4 gate line PX pixel SR1-SR5 shift register

Claims (4)

In a driving circuit of a liquid crystal display device that receives and displays interlaced image data, a plurality of pixels having memory elements that hold image data are arranged in a matrix to form a plurality of lines.
A driving circuit for a liquid crystal display device, comprising: a scanning circuit that outputs scanning signals to even lines in even frames and outputs scanning signals to odd lines in odd frames. The scanning circuit shifts a start pulse based on a shift clock, and outputs a plurality of shift signals in time series, and a shift register;
A mask circuit for masking scanning signals of the plurality of shift registers according to a mask signal,
The scanning circuit masks the scanning signal by generating a scanning signal corresponding to an odd line from the shift register during the generation period of the mask signal in the even frame.
2. The liquid crystal display device according to claim 1, wherein in an odd frame, the scanning signal is masked by generating a scanning signal corresponding to an even line from the shift register during the generation period of the mask signal. Drive circuit. The shift clock includes a first clock having a short pulse width;
3. The driving circuit for a liquid crystal display device according to claim 2, comprising a second clock having a pulse width longer than that of the first clock, wherein the first clock is included in a generation period of the mask signal.   The drive circuit of a liquid crystal display device according to claim 1, wherein the memory element is a capacitive element.

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