JP2024502642A5 - - Google Patents
Info
- Publication number
- JP2024502642A5 JP2024502642A5 JP2023542527A JP2023542527A JP2024502642A5 JP 2024502642 A5 JP2024502642 A5 JP 2024502642A5 JP 2023542527 A JP2023542527 A JP 2023542527A JP 2023542527 A JP2023542527 A JP 2023542527A JP 2024502642 A5 JP2024502642 A5 JP 2024502642A5
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- input
- coupled
- dtc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163136243P | 2021-01-12 | 2021-01-12 | |
| US63/136,243 | 2021-01-12 | ||
| US17/573,323 | 2022-01-11 | ||
| US17/573,323 US11632116B2 (en) | 2021-01-12 | 2022-01-11 | Calibration of parametric error of digital-to-time converters |
| PCT/US2022/012085 WO2022155176A1 (en) | 2021-01-12 | 2022-01-12 | Calibration of parametric error of digital-to-time converters |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024502642A JP2024502642A (ja) | 2024-01-22 |
| JP2024502642A5 true JP2024502642A5 (https=) | 2025-01-21 |
Family
ID=82322134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023542527A Pending JP2024502642A (ja) | 2021-01-12 | 2022-01-12 | デジタル・時間変換器のパラメトリック誤差の較正 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11632116B2 (https=) |
| EP (1) | EP4278439A4 (https=) |
| JP (1) | JP2024502642A (https=) |
| CN (1) | CN116671015A (https=) |
| WO (1) | WO2022155176A1 (https=) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022115650A1 (en) * | 2020-11-26 | 2022-06-02 | Rambus Inc. | Low jitter clock multiplier circuit and method with arbitary frequency acquisition |
| US11632116B2 (en) * | 2021-01-12 | 2023-04-18 | Texas Instruments Incorporated | Calibration of parametric error of digital-to-time converters |
| US11683048B2 (en) * | 2021-04-21 | 2023-06-20 | Avago Technologies International Sales Pte. Limited | Systems for and methods of fractional frequency division |
| US12278643B2 (en) * | 2021-09-22 | 2025-04-15 | Intel Corporation | Calibration for DTC fractional frequency synthesis |
| KR20230079723A (ko) * | 2021-11-29 | 2023-06-07 | 삼성전자주식회사 | 위상 쉬프터를 포함하는 분수 분주기 및 이를 포함하는 분수 분주형 위상 고정 루프 |
| US12381567B2 (en) | 2022-12-30 | 2025-08-05 | Texas Instruments Incorporated | Digital-to-time converter calibration |
| US11923857B1 (en) * | 2023-01-26 | 2024-03-05 | Xilinx, Inc. | DTC nonlinearity correction |
| CN120693792A (zh) * | 2023-08-04 | 2025-09-23 | 华为技术有限公司 | 分频校正电路及其控制方法、芯片、电子设备 |
| US12603655B1 (en) * | 2024-04-02 | 2026-04-14 | Cadence Design Systems, Inc. | Subranging digital to time converter-based fractional phase locked loop architecture |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511589B2 (en) * | 2006-08-05 | 2009-03-31 | Tang System | DFY of XtalClkChip: design for yield of trimming-free crystal-free precision reference clock osillator IC chip |
| KR100800150B1 (ko) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | 지연 고정 루프 장치 |
| US7548123B2 (en) * | 2007-07-13 | 2009-06-16 | Silicon Laboratories Inc. | Dividerless PLL architecture |
| US8081936B2 (en) * | 2009-01-22 | 2011-12-20 | Mediatek Inc. | Method for tuning a digital compensation filter within a transmitter, and associated digital compensation filter and associated calibration circuit |
| US7999586B2 (en) * | 2009-12-23 | 2011-08-16 | Intel Corporation | Digital phase locked loop with closed loop linearization technique |
| US8497716B2 (en) * | 2011-08-05 | 2013-07-30 | Qualcomm Incorporated | Phase locked loop with phase correction in the feedback loop |
| US9225562B2 (en) * | 2012-02-27 | 2015-12-29 | Intel Deutschland Gmbh | Digital wideband closed loop phase modulator with modulation gain calibration |
| US8860514B2 (en) | 2012-12-21 | 2014-10-14 | Silicon Laboratories Inc. | Time-interleaved digital-to-time converter |
| US8994573B2 (en) | 2013-03-15 | 2015-03-31 | Intel Mobile Communications GmbH | Digital-to-time converter and calibration of digital-to-time converter |
| EP2782255A1 (en) * | 2013-03-19 | 2014-09-24 | Imec | Fractional-N frequency synthesizer using a subsampling pll and method for calibrating the same |
| WO2016029058A1 (en) * | 2014-08-20 | 2016-02-25 | Zaretsky, Howard | Fractional-n frequency synthesizer incorporating cyclic digital-to-time and time -to-digital circuit pair |
| US9531394B1 (en) | 2015-06-22 | 2016-12-27 | Silicon Laboratories Inc. | Calibration of digital-to-time converter |
| US9678481B1 (en) | 2016-06-17 | 2017-06-13 | Integrated Device Technologies, Inc. | Fractional divider using a calibrated digital-to-time converter |
| EP3618281B1 (en) * | 2018-09-03 | 2023-05-10 | IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik | Parallel fractional-n phase locked loop circuit |
| US10511315B1 (en) * | 2018-09-21 | 2019-12-17 | Silicon Laboratories Inc. | Adaptive jitter and spur adjustment for clock circuits |
| US10594329B1 (en) | 2018-12-07 | 2020-03-17 | Si-Ware Systems S.A.E. | Adaptive non-linearity identification and compensation using orthogonal functions in a mixed signal circuit |
| US10826507B1 (en) * | 2019-05-06 | 2020-11-03 | Silicon Laboratories Inc. | Fractional divider with error correction |
| US10895850B1 (en) * | 2019-07-25 | 2021-01-19 | Si-Ware Systems S.A.E. | Mixed-domain circuit with differential domain-converters |
| US10819353B1 (en) * | 2019-10-04 | 2020-10-27 | Silicon Laboratories Inc. | Spur cancellation in a PLL system with an automatically updated target spur frequency |
| US11271584B2 (en) * | 2020-07-08 | 2022-03-08 | Korean Advanced Institute Of Science And Technology | Integrated circuit, electronic device including the same, and operating method thereof |
| KR102481711B1 (ko) * | 2020-08-20 | 2022-12-27 | 한국과학기술원 | 디지털 위상 고정 루프 회로, 이를 포함하는 시스템 온 칩 및 이의 동작 방법 |
| US11201626B1 (en) * | 2020-09-21 | 2021-12-14 | Samsung Electronics Co., Ltd. | Phase locked loop device and method of operating ihe same |
| US11784649B2 (en) * | 2021-01-12 | 2023-10-10 | Texas Instruments Incorporated | High gain detector techniques for high bandwidth low noise phase-locked loops |
| US11632116B2 (en) * | 2021-01-12 | 2023-04-18 | Texas Instruments Incorporated | Calibration of parametric error of digital-to-time converters |
| US11387833B1 (en) * | 2021-09-03 | 2022-07-12 | Qualcomm Incorporated | Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection |
| CN114710154B (zh) * | 2022-06-07 | 2022-08-30 | 绍兴圆方半导体有限公司 | 基于时分复用增益校准的开环小数分频器和时钟系统 |
-
2022
- 2022-01-11 US US17/573,323 patent/US11632116B2/en active Active
- 2022-01-12 CN CN202280008712.0A patent/CN116671015A/zh active Pending
- 2022-01-12 EP EP22739961.5A patent/EP4278439A4/en active Pending
- 2022-01-12 WO PCT/US2022/012085 patent/WO2022155176A1/en not_active Ceased
- 2022-01-12 JP JP2023542527A patent/JP2024502642A/ja active Pending
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