JP2024502642A - デジタル・時間変換器のパラメトリック誤差の較正 - Google Patents

デジタル・時間変換器のパラメトリック誤差の較正 Download PDF

Info

Publication number
JP2024502642A
JP2024502642A JP2023542527A JP2023542527A JP2024502642A JP 2024502642 A JP2024502642 A JP 2024502642A JP 2023542527 A JP2023542527 A JP 2023542527A JP 2023542527 A JP2023542527 A JP 2023542527A JP 2024502642 A JP2024502642 A JP 2024502642A
Authority
JP
Japan
Prior art keywords
output
circuit
input
coupled
dtc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023542527A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024502642A5 (https=
Inventor
ヘンダーソン ペロット ミカエル
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by テキサス インスツルメンツ インコーポレイテッド filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2024502642A publication Critical patent/JP2024502642A/ja
Publication of JP2024502642A5 publication Critical patent/JP2024502642A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electromechanical Clocks (AREA)
JP2023542527A 2021-01-12 2022-01-12 デジタル・時間変換器のパラメトリック誤差の較正 Pending JP2024502642A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163136243P 2021-01-12 2021-01-12
US63/136,243 2021-01-12
US17/573,323 2022-01-11
US17/573,323 US11632116B2 (en) 2021-01-12 2022-01-11 Calibration of parametric error of digital-to-time converters
PCT/US2022/012085 WO2022155176A1 (en) 2021-01-12 2022-01-12 Calibration of parametric error of digital-to-time converters

Publications (2)

Publication Number Publication Date
JP2024502642A true JP2024502642A (ja) 2024-01-22
JP2024502642A5 JP2024502642A5 (https=) 2025-01-21

Family

ID=82322134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023542527A Pending JP2024502642A (ja) 2021-01-12 2022-01-12 デジタル・時間変換器のパラメトリック誤差の較正

Country Status (5)

Country Link
US (1) US11632116B2 (https=)
EP (1) EP4278439A4 (https=)
JP (1) JP2024502642A (https=)
CN (1) CN116671015A (https=)
WO (1) WO2022155176A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022115650A1 (en) * 2020-11-26 2022-06-02 Rambus Inc. Low jitter clock multiplier circuit and method with arbitary frequency acquisition
US11632116B2 (en) * 2021-01-12 2023-04-18 Texas Instruments Incorporated Calibration of parametric error of digital-to-time converters
US11683048B2 (en) * 2021-04-21 2023-06-20 Avago Technologies International Sales Pte. Limited Systems for and methods of fractional frequency division
US12278643B2 (en) * 2021-09-22 2025-04-15 Intel Corporation Calibration for DTC fractional frequency synthesis
KR20230079723A (ko) * 2021-11-29 2023-06-07 삼성전자주식회사 위상 쉬프터를 포함하는 분수 분주기 및 이를 포함하는 분수 분주형 위상 고정 루프
US12381567B2 (en) 2022-12-30 2025-08-05 Texas Instruments Incorporated Digital-to-time converter calibration
US11923857B1 (en) * 2023-01-26 2024-03-05 Xilinx, Inc. DTC nonlinearity correction
CN120693792A (zh) * 2023-08-04 2025-09-23 华为技术有限公司 分频校正电路及其控制方法、芯片、电子设备
US12603655B1 (en) * 2024-04-02 2026-04-14 Cadence Design Systems, Inc. Subranging digital to time converter-based fractional phase locked loop architecture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140176201A1 (en) * 2012-12-21 2014-06-26 Silicon Laboratories Inc. Time-interleaved digital-to-time converter
JP2014527755A (ja) * 2011-08-05 2014-10-16 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ フィードバックループにおける位相補正を備えた位相ロックドループ
US20170364034A1 (en) * 2016-06-17 2017-12-21 Integrated Device Technology, Inc. Fractional divider using a calibrated digital-to-time converter

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511589B2 (en) * 2006-08-05 2009-03-31 Tang System DFY of XtalClkChip: design for yield of trimming-free crystal-free precision reference clock osillator IC chip
KR100800150B1 (ko) * 2006-06-30 2008-02-01 주식회사 하이닉스반도체 지연 고정 루프 장치
US7548123B2 (en) * 2007-07-13 2009-06-16 Silicon Laboratories Inc. Dividerless PLL architecture
US8081936B2 (en) * 2009-01-22 2011-12-20 Mediatek Inc. Method for tuning a digital compensation filter within a transmitter, and associated digital compensation filter and associated calibration circuit
US7999586B2 (en) * 2009-12-23 2011-08-16 Intel Corporation Digital phase locked loop with closed loop linearization technique
US9225562B2 (en) * 2012-02-27 2015-12-29 Intel Deutschland Gmbh Digital wideband closed loop phase modulator with modulation gain calibration
US8994573B2 (en) 2013-03-15 2015-03-31 Intel Mobile Communications GmbH Digital-to-time converter and calibration of digital-to-time converter
EP2782255A1 (en) * 2013-03-19 2014-09-24 Imec Fractional-N frequency synthesizer using a subsampling pll and method for calibrating the same
WO2016029058A1 (en) * 2014-08-20 2016-02-25 Zaretsky, Howard Fractional-n frequency synthesizer incorporating cyclic digital-to-time and time -to-digital circuit pair
US9531394B1 (en) 2015-06-22 2016-12-27 Silicon Laboratories Inc. Calibration of digital-to-time converter
EP3618281B1 (en) * 2018-09-03 2023-05-10 IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Parallel fractional-n phase locked loop circuit
US10511315B1 (en) * 2018-09-21 2019-12-17 Silicon Laboratories Inc. Adaptive jitter and spur adjustment for clock circuits
US10594329B1 (en) 2018-12-07 2020-03-17 Si-Ware Systems S.A.E. Adaptive non-linearity identification and compensation using orthogonal functions in a mixed signal circuit
US10826507B1 (en) * 2019-05-06 2020-11-03 Silicon Laboratories Inc. Fractional divider with error correction
US10895850B1 (en) * 2019-07-25 2021-01-19 Si-Ware Systems S.A.E. Mixed-domain circuit with differential domain-converters
US10819353B1 (en) * 2019-10-04 2020-10-27 Silicon Laboratories Inc. Spur cancellation in a PLL system with an automatically updated target spur frequency
US11271584B2 (en) * 2020-07-08 2022-03-08 Korean Advanced Institute Of Science And Technology Integrated circuit, electronic device including the same, and operating method thereof
KR102481711B1 (ko) * 2020-08-20 2022-12-27 한국과학기술원 디지털 위상 고정 루프 회로, 이를 포함하는 시스템 온 칩 및 이의 동작 방법
US11201626B1 (en) * 2020-09-21 2021-12-14 Samsung Electronics Co., Ltd. Phase locked loop device and method of operating ihe same
US11784649B2 (en) * 2021-01-12 2023-10-10 Texas Instruments Incorporated High gain detector techniques for high bandwidth low noise phase-locked loops
US11632116B2 (en) * 2021-01-12 2023-04-18 Texas Instruments Incorporated Calibration of parametric error of digital-to-time converters
US11387833B1 (en) * 2021-09-03 2022-07-12 Qualcomm Incorporated Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection
CN114710154B (zh) * 2022-06-07 2022-08-30 绍兴圆方半导体有限公司 基于时分复用增益校准的开环小数分频器和时钟系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014527755A (ja) * 2011-08-05 2014-10-16 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ フィードバックループにおける位相補正を備えた位相ロックドループ
US20140176201A1 (en) * 2012-12-21 2014-06-26 Silicon Laboratories Inc. Time-interleaved digital-to-time converter
US20170364034A1 (en) * 2016-06-17 2017-12-21 Integrated Device Technology, Inc. Fractional divider using a calibrated digital-to-time converter

Also Published As

Publication number Publication date
CN116671015A (zh) 2023-08-29
US20220224344A1 (en) 2022-07-14
US11632116B2 (en) 2023-04-18
EP4278439A4 (en) 2024-07-31
WO2022155176A1 (en) 2022-07-21
EP4278439A1 (en) 2023-11-22

Similar Documents

Publication Publication Date Title
JP2024502642A (ja) デジタル・時間変換器のパラメトリック誤差の較正
US9838026B2 (en) Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators
Gupta et al. A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration
US7884655B2 (en) Control circuitry
Hsu et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma $ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
US9490818B2 (en) Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter
US9941891B2 (en) Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit
Vercesi et al. A dither-less all digital PLL for cellular transmitters
US11316522B2 (en) Correction for period error in a reference clock signal
US11418199B1 (en) Phase locked loop with parallel phase detection circuits
KR102418966B1 (ko) 디지털 위상 고정 루프 및 그의 구동방법
JP2024502642A5 (https=)
US7327820B2 (en) Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers
US11437980B2 (en) Frequency to digital converter, asynchronous phase sampler and digitally controlled oscillator methods
Ho et al. A fractional-N DPLL with calibration-free multi-phase injection-locked TDC and adaptive single-tone spur cancellation scheme
Elmallah et al. A 3.2-GHz 405 fs rms jitter–237.2 dB FoM JIT ring-based fractional-N synthesizer
US12381567B2 (en) Digital-to-time converter calibration
US10715158B1 (en) Phase-locked loop (PLL) with calibration circuit
Jiang et al. A 2.3-3.9 GHz fractional-N frequency synthesizer with charge pump and TDC calibration for reduced reference and fractional spurs
JP2008515344A (ja) シグマデルタベースのフェーズロックループ
Wu et al. A quantization error minimization method using DDS-DAC for wideband fractional-N frequency synthesizer
Bruss et al. A 5-GHz CMOS Type-II PLL With Low $ K_ {\rm VCO} $ and Extended Fine-Tuning Range
Hati et al. A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation
Yang et al. A 3-to-6-GHzFractional-N Charge-Pump PLL Featuring Bimodal-Like MASH-SR and Charge-Pump-Bleed Calibration Achieving Worst Case In-Band Fractional Spur of− 73 dBc
Nguyen et al. Inductorless 5.405 GHz Fractional-N PLL for RF Synthesis with 5.6 mW Power Consumption

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250110

A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20250110

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20251219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20260204