CN116671015A - 数字到时间转换器的参数误差校准 - Google Patents
数字到时间转换器的参数误差校准 Download PDFInfo
- Publication number
- CN116671015A CN116671015A CN202280008712.0A CN202280008712A CN116671015A CN 116671015 A CN116671015 A CN 116671015A CN 202280008712 A CN202280008712 A CN 202280008712A CN 116671015 A CN116671015 A CN 116671015A
- Authority
- CN
- China
- Prior art keywords
- output
- input
- circuit
- coupled
- dtc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010354 integration Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 39
- 239000003990 capacitor Substances 0.000 description 12
- 238000009825 accumulation Methods 0.000 description 11
- 238000012937 correction Methods 0.000 description 11
- 238000001228 spectrum Methods 0.000 description 6
- 238000001914 filtration Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Analogue/Digital Conversion (AREA)
- Electromechanical Clocks (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163136243P | 2021-01-12 | 2021-01-12 | |
| US63/136,243 | 2021-01-12 | ||
| US17/573,323 | 2022-01-11 | ||
| US17/573,323 US11632116B2 (en) | 2021-01-12 | 2022-01-11 | Calibration of parametric error of digital-to-time converters |
| PCT/US2022/012085 WO2022155176A1 (en) | 2021-01-12 | 2022-01-12 | Calibration of parametric error of digital-to-time converters |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116671015A true CN116671015A (zh) | 2023-08-29 |
Family
ID=82322134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280008712.0A Pending CN116671015A (zh) | 2021-01-12 | 2022-01-12 | 数字到时间转换器的参数误差校准 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11632116B2 (https=) |
| EP (1) | EP4278439A4 (https=) |
| JP (1) | JP2024502642A (https=) |
| CN (1) | CN116671015A (https=) |
| WO (1) | WO2022155176A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12603655B1 (en) * | 2024-04-02 | 2026-04-14 | Cadence Design Systems, Inc. | Subranging digital to time converter-based fractional phase locked loop architecture |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022115650A1 (en) * | 2020-11-26 | 2022-06-02 | Rambus Inc. | Low jitter clock multiplier circuit and method with arbitary frequency acquisition |
| US11632116B2 (en) * | 2021-01-12 | 2023-04-18 | Texas Instruments Incorporated | Calibration of parametric error of digital-to-time converters |
| US11683048B2 (en) * | 2021-04-21 | 2023-06-20 | Avago Technologies International Sales Pte. Limited | Systems for and methods of fractional frequency division |
| US12278643B2 (en) * | 2021-09-22 | 2025-04-15 | Intel Corporation | Calibration for DTC fractional frequency synthesis |
| KR20230079723A (ko) * | 2021-11-29 | 2023-06-07 | 삼성전자주식회사 | 위상 쉬프터를 포함하는 분수 분주기 및 이를 포함하는 분수 분주형 위상 고정 루프 |
| US12381567B2 (en) | 2022-12-30 | 2025-08-05 | Texas Instruments Incorporated | Digital-to-time converter calibration |
| US11923857B1 (en) * | 2023-01-26 | 2024-03-05 | Xilinx, Inc. | DTC nonlinearity correction |
| CN120693792A (zh) * | 2023-08-04 | 2025-09-23 | 华为技术有限公司 | 分频校正电路及其控制方法、芯片、电子设备 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511589B2 (en) * | 2006-08-05 | 2009-03-31 | Tang System | DFY of XtalClkChip: design for yield of trimming-free crystal-free precision reference clock osillator IC chip |
| KR100800150B1 (ko) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | 지연 고정 루프 장치 |
| US7548123B2 (en) * | 2007-07-13 | 2009-06-16 | Silicon Laboratories Inc. | Dividerless PLL architecture |
| US8081936B2 (en) * | 2009-01-22 | 2011-12-20 | Mediatek Inc. | Method for tuning a digital compensation filter within a transmitter, and associated digital compensation filter and associated calibration circuit |
| US7999586B2 (en) * | 2009-12-23 | 2011-08-16 | Intel Corporation | Digital phase locked loop with closed loop linearization technique |
| US8497716B2 (en) * | 2011-08-05 | 2013-07-30 | Qualcomm Incorporated | Phase locked loop with phase correction in the feedback loop |
| US9225562B2 (en) * | 2012-02-27 | 2015-12-29 | Intel Deutschland Gmbh | Digital wideband closed loop phase modulator with modulation gain calibration |
| US8860514B2 (en) | 2012-12-21 | 2014-10-14 | Silicon Laboratories Inc. | Time-interleaved digital-to-time converter |
| US8994573B2 (en) | 2013-03-15 | 2015-03-31 | Intel Mobile Communications GmbH | Digital-to-time converter and calibration of digital-to-time converter |
| EP2782255A1 (en) * | 2013-03-19 | 2014-09-24 | Imec | Fractional-N frequency synthesizer using a subsampling pll and method for calibrating the same |
| WO2016029058A1 (en) * | 2014-08-20 | 2016-02-25 | Zaretsky, Howard | Fractional-n frequency synthesizer incorporating cyclic digital-to-time and time -to-digital circuit pair |
| US9531394B1 (en) | 2015-06-22 | 2016-12-27 | Silicon Laboratories Inc. | Calibration of digital-to-time converter |
| US9678481B1 (en) | 2016-06-17 | 2017-06-13 | Integrated Device Technologies, Inc. | Fractional divider using a calibrated digital-to-time converter |
| EP3618281B1 (en) * | 2018-09-03 | 2023-05-10 | IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik | Parallel fractional-n phase locked loop circuit |
| US10511315B1 (en) * | 2018-09-21 | 2019-12-17 | Silicon Laboratories Inc. | Adaptive jitter and spur adjustment for clock circuits |
| US10594329B1 (en) | 2018-12-07 | 2020-03-17 | Si-Ware Systems S.A.E. | Adaptive non-linearity identification and compensation using orthogonal functions in a mixed signal circuit |
| US10826507B1 (en) * | 2019-05-06 | 2020-11-03 | Silicon Laboratories Inc. | Fractional divider with error correction |
| US10895850B1 (en) * | 2019-07-25 | 2021-01-19 | Si-Ware Systems S.A.E. | Mixed-domain circuit with differential domain-converters |
| US10819353B1 (en) * | 2019-10-04 | 2020-10-27 | Silicon Laboratories Inc. | Spur cancellation in a PLL system with an automatically updated target spur frequency |
| US11271584B2 (en) * | 2020-07-08 | 2022-03-08 | Korean Advanced Institute Of Science And Technology | Integrated circuit, electronic device including the same, and operating method thereof |
| KR102481711B1 (ko) * | 2020-08-20 | 2022-12-27 | 한국과학기술원 | 디지털 위상 고정 루프 회로, 이를 포함하는 시스템 온 칩 및 이의 동작 방법 |
| US11201626B1 (en) * | 2020-09-21 | 2021-12-14 | Samsung Electronics Co., Ltd. | Phase locked loop device and method of operating ihe same |
| US11784649B2 (en) * | 2021-01-12 | 2023-10-10 | Texas Instruments Incorporated | High gain detector techniques for high bandwidth low noise phase-locked loops |
| US11632116B2 (en) * | 2021-01-12 | 2023-04-18 | Texas Instruments Incorporated | Calibration of parametric error of digital-to-time converters |
| US11387833B1 (en) * | 2021-09-03 | 2022-07-12 | Qualcomm Incorporated | Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection |
| CN114710154B (zh) * | 2022-06-07 | 2022-08-30 | 绍兴圆方半导体有限公司 | 基于时分复用增益校准的开环小数分频器和时钟系统 |
-
2022
- 2022-01-11 US US17/573,323 patent/US11632116B2/en active Active
- 2022-01-12 CN CN202280008712.0A patent/CN116671015A/zh active Pending
- 2022-01-12 EP EP22739961.5A patent/EP4278439A4/en active Pending
- 2022-01-12 WO PCT/US2022/012085 patent/WO2022155176A1/en not_active Ceased
- 2022-01-12 JP JP2023542527A patent/JP2024502642A/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12603655B1 (en) * | 2024-04-02 | 2026-04-14 | Cadence Design Systems, Inc. | Subranging digital to time converter-based fractional phase locked loop architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| US20220224344A1 (en) | 2022-07-14 |
| US11632116B2 (en) | 2023-04-18 |
| EP4278439A4 (en) | 2024-07-31 |
| WO2022155176A1 (en) | 2022-07-21 |
| JP2024502642A (ja) | 2024-01-22 |
| EP4278439A1 (en) | 2023-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11632116B2 (en) | Calibration of parametric error of digital-to-time converters | |
| US9838026B2 (en) | Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators | |
| US11070168B2 (en) | Oscillator circuit | |
| Vercesi et al. | A dither-less all digital PLL for cellular transmitters | |
| Vaucher et al. | Architectures for RF frequency synthesizers | |
| US8571161B2 (en) | Electronic device for generating a fractional frequency | |
| US7884655B2 (en) | Control circuitry | |
| US11316522B2 (en) | Correction for period error in a reference clock signal | |
| CN113169738A (zh) | 使用混合信号电路中的正交函数的自适应非线性识别与补偿 | |
| EP1982410B1 (en) | Oscillator gain equalization | |
| KR102418966B1 (ko) | 디지털 위상 고정 루프 및 그의 구동방법 | |
| US10862427B1 (en) | Advanced multi-gain calibration for direct modulation synthesizer | |
| US7327820B2 (en) | Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers | |
| Elmallah et al. | A 3.2-GHz 405 fs rms jitter–237.2 dB FoM JIT ring-based fractional-N synthesizer | |
| US10715158B1 (en) | Phase-locked loop (PLL) with calibration circuit | |
| US12381567B2 (en) | Digital-to-time converter calibration | |
| US8456204B2 (en) | Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops | |
| KR101242670B1 (ko) | 시그마-델타 기반 위상 고정 루프 | |
| CN119298905A (zh) | 一种低杂散低抖动的频率综合器电路 | |
| Wu et al. | A quantization error minimization method using DDS-DAC for wideband fractional-N frequency synthesizer | |
| Bruss et al. | A 5-GHz CMOS Type-II PLL With Low $ K_ {\rm VCO} $ and Extended Fine-Tuning Range | |
| Hati et al. | A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation | |
| CN223348663U (zh) | 一种低杂散低抖动的频率综合器电路 | |
| CN121791862A (zh) | 开环时域小数分频时钟合成方法及电路 | |
| CN121263959A (zh) | 锁相环系统以及用于调谐振荡器的方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |