JP2023549713A - 混合パッドサイズおよびパッド設計 - Google Patents

混合パッドサイズおよびパッド設計 Download PDF

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Publication number
JP2023549713A
JP2023549713A JP2023526401A JP2023526401A JP2023549713A JP 2023549713 A JP2023549713 A JP 2023549713A JP 2023526401 A JP2023526401 A JP 2023526401A JP 2023526401 A JP2023526401 A JP 2023526401A JP 2023549713 A JP2023549713 A JP 2023549713A
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JP
Japan
Prior art keywords
pads
solder resist
package
pad
pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023526401A
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English (en)
Japanese (ja)
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JP2023549713A5 (https=
Inventor
ウェン・イン
ヨンハオ・アン
マニュエル・アルドレーテ
Original Assignee
クアルコム，インコーポレイテッド
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Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2023549713A publication Critical patent/JP2023549713A/ja
Publication of JP2023549713A5 publication Critical patent/JP2023549713A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
JP2023526401A 2020-11-13 2021-10-11 混合パッドサイズおよびパッド設計 Pending JP2023549713A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/097,327 2020-11-13
US17/097,327 US11804428B2 (en) 2020-11-13 2020-11-13 Mixed pad size and pad design
PCT/US2021/054406 WO2022103539A1 (en) 2020-11-13 2021-10-11 Mixed pad size and pad design

Publications (2)

Publication Number Publication Date
JP2023549713A true JP2023549713A (ja) 2023-11-29
JP2023549713A5 JP2023549713A5 (https=) 2024-10-04

Family

ID=78650050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023526401A Pending JP2023549713A (ja) 2020-11-13 2021-10-11 混合パッドサイズおよびパッド設計

Country Status (7)

Country Link
US (1) US11804428B2 (https=)
EP (1) EP4244888A1 (https=)
JP (1) JP2023549713A (https=)
KR (1) KR20230104615A (https=)
CN (1) CN116325146A (https=)
TW (1) TWI907542B (https=)
WO (1) WO2022103539A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102741172B1 (ko) * 2019-12-06 2024-12-11 삼성전자주식회사 테스트 범프들을 포함하는 반도체 패키지
US12400944B2 (en) 2022-01-03 2025-08-26 Mediatek Inc. Board-level pad pattern for multi-row QFN packages
US12532758B2 (en) 2022-01-03 2026-01-20 Mediatek Inc. Board-level pad pattern for multi-row QFN packages
US12309921B2 (en) * 2022-01-03 2025-05-20 Mediatek Inc. Board-level pad pattern for multi-row QFN packages
US12362307B2 (en) * 2022-08-30 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with ball grid array connection having improved reliability
CN115763418A (zh) * 2022-12-07 2023-03-07 武汉光谷信息光电子创新中心有限公司 一种垂直互连结构及电子封装器件

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340352A (ja) * 1998-05-22 1999-12-10 Matsushita Electric Ind Co Ltd 実装構造体
JP2000269270A (ja) * 1999-03-15 2000-09-29 Nec Corp 半導体装置の製造方法
JP2004327958A (ja) * 2003-04-28 2004-11-18 Endicott Interconnect Technologies Inc 強化導電パッドを装備した電子パッケージ、及びこれを使用した情報処理装置
JP2006294656A (ja) * 2005-04-06 2006-10-26 Matsushita Electric Ind Co Ltd 半導体装置
JP2010123602A (ja) * 2008-11-17 2010-06-03 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2012015648A (ja) * 2010-06-29 2012-01-19 Toshiba Corp 画像処理装置、表示装置、および画像処理方法
JP2012015468A (ja) * 2010-07-05 2012-01-19 Panasonic Corp 半導体装置
JP2012119648A (ja) * 2010-12-03 2012-06-21 Stats Chippac Ltd フリップチップ半導体ダイのパッドレイアウトを形成する半導体素子および方法
JP2019511832A (ja) * 2016-02-01 2019-04-25 クアルコム，インコーポレイテッド オープンパッシベーションボールグリッドアレイパッド
JP2020087987A (ja) * 2018-11-16 2020-06-04 日立オートモティブシステムズ株式会社 電子制御基板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787918B1 (en) 2000-06-02 2004-09-07 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
US6819001B2 (en) * 2003-03-14 2004-11-16 General Electric Company Interposer, interposer package and device assembly employing the same
JP5185885B2 (ja) 2009-05-21 2013-04-17 新光電気工業株式会社 配線基板および半導体装置
US8927878B2 (en) 2011-10-31 2015-01-06 Mediatek Singapore Pte. Ltd Printed circuit board and electronic apparatus thereof
US20180053740A1 (en) * 2016-08-22 2018-02-22 Qualcomm Incorporated Land grid based multi size pad package
KR20180095371A (ko) 2017-02-17 2018-08-27 엘지전자 주식회사 이동 단말기 및 인쇄 회로 기판
US10211141B1 (en) * 2017-11-17 2019-02-19 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
KR102109570B1 (ko) * 2018-07-24 2020-05-12 삼성전자주식회사 반도체 패키지 실장 기판
US12278205B2 (en) * 2019-02-01 2025-04-15 Texas Instruments Incorporated Semiconductor device package with improved die pad and solder mask design

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340352A (ja) * 1998-05-22 1999-12-10 Matsushita Electric Ind Co Ltd 実装構造体
JP2000269270A (ja) * 1999-03-15 2000-09-29 Nec Corp 半導体装置の製造方法
JP2004327958A (ja) * 2003-04-28 2004-11-18 Endicott Interconnect Technologies Inc 強化導電パッドを装備した電子パッケージ、及びこれを使用した情報処理装置
JP2006294656A (ja) * 2005-04-06 2006-10-26 Matsushita Electric Ind Co Ltd 半導体装置
JP2010123602A (ja) * 2008-11-17 2010-06-03 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2012015648A (ja) * 2010-06-29 2012-01-19 Toshiba Corp 画像処理装置、表示装置、および画像処理方法
JP2012015468A (ja) * 2010-07-05 2012-01-19 Panasonic Corp 半導体装置
JP2012119648A (ja) * 2010-12-03 2012-06-21 Stats Chippac Ltd フリップチップ半導体ダイのパッドレイアウトを形成する半導体素子および方法
JP2019511832A (ja) * 2016-02-01 2019-04-25 クアルコム，インコーポレイテッド オープンパッシベーションボールグリッドアレイパッド
JP2020087987A (ja) * 2018-11-16 2020-06-04 日立オートモティブシステムズ株式会社 電子制御基板

Also Published As

Publication number Publication date
TWI907542B (zh) 2025-12-11
CN116325146A (zh) 2023-06-23
WO2022103539A1 (en) 2022-05-19
US20220157705A1 (en) 2022-05-19
US11804428B2 (en) 2023-10-31
KR20230104615A (ko) 2023-07-10
EP4244888A1 (en) 2023-09-20
TW202220136A (zh) 2022-05-16

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