Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• This disclosure relates generally to package devices, and more specifically, but not exclusively, to mixed pad size and pad design for devices and fabrication techniques thereof.
• Integrated circuit technology has achieved great strides in advancing computing power through miniaturization of active components.
• the flip-chip devices can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc.
• RF radio frequency
• Flip-chip packaging technology becomes cost-effective in high pin count devices.
• the flip-chip bonding conventionally uses solder-on-pad (SOP) technology for flip-chip substrates.
• At least one aspect includes, an apparatus including a package.
• the package including a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads.
• the apparatus also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.
• SMD solder mask defined
• NSMD non-solder mask defined
• At least one aspect includes, a method for fabricating a package, the method including: forming a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The method also includes forming a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.
• SMD solder mask defined
• FIG. 1 illustrates a partial cross-sectional view of an interconnection of a flip-chip device.
• FIG. 2 illustrates a partial image of a conventional design for a package based on conventional design rules.
• FIG. 3 illustrates a partial image of a design for a package in accordance with some examples of the disclosure.
• FIG. 4 illustrates a partial image of a design for a package in accordance with some examples of the disclosure.
• FIG. 5 illustrates a partial image of a design for a package in accordance with some examples of the disclosure.
• FIG. 6 illustrates components of an integrated device according to one or more aspects of the disclosure.
• FIG. 7 illustrates a flowchart of a method for manufacturing a package in accordance with some examples of the disclosure.
• FIG. 8 illustrates an exemplary mobile device in accordance with some examples of the disclosure.
• FIG. 9 illustrates various electronic devices which may include a mixed pad size in accordance with various examples of the disclosure.
• instances are identified where various component structures and portions of operations can be taken from known, conventional techniques, and then arranged in accordance with one or more exemplary aspects. In such instances, internal details of the known, conventional component structures and/or portions of operations may be omitted to help avoid potential obfuscation of the concepts illustrated in the illustrative aspects disclosed herein.
• connection means any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element unless the connection is expressly disclosed as being directly connected.
• FIG. 1 illustrates an exemplary partial side view of a flip-chip device 100.
• a flip-chip device 100 includes a package 110 having a plurality of insulating layer (171 and 172) and metal layers (161, 162 and 163). The various metal layers 161, 162 and 163 can be interconnected using vias, such as via 116.
• a ball grid array (BGA) connection may include a BGA pad 130 and a solder ball 135 coupled to the BGA pad 130 through an opening in solder resist 132.
• the solder ball 135 can be used to connect to the flip-chip device 100 formed of die 120 (also referred to as “chip”) and package 110 to external devices, circuitry, etc.
• the BGA pad 130 and the BGA configuration may be a mixed pad configuration according to various aspects disclosed herein. Additional details regarding the mixed pad BGA configuration will be provided in the following disclosure.
• a bond pad 114 illustrated as a copper bond pad 114.
• a solder resist layer 112 is formed over the bond pad 114.
• the solder resist layer 112 can be a photosensitive polymer material having a narrow opening to allow for connection to the bond pad 114.
• Solder-on-pad (SOP) 115 is provided to fill the opening to facilitate connection to the bond pad 114 in later operations.
• the SOP 115 can be formed by a solder drop or can be printed with a solder paste and reflow process to fill the opening.
• the SOP is used to prevent voids in the interconnection of the package 110 to the die 120.
• the under bump metallization (UBM) 122 of the die 120 is used for connecting the die 120 to the package 110 with solder bump 125 for flip-chip packages.
• the UBM 122 of the die 120 may be formed of aluminum or copper. It will be appreciated that although only one interconnection between the die 120 and package 110 is illustrated, a plurality of interconnections are used for the flip-chip device 100.
• FIG. 2 illustrates a partial image of a conventional design for a package 200.
• current package designs use uniform BGA pads 210 size and pitch 215 across the whole package 200.
• the uniform BGA pads 210 use uniform solder mask defined (SMD) pad design.
• SMD solder mask defined
• FIG. 3 illustrates a partial image of a package 300 based according to various aspects of the disclosure.
• the package 300 is configured to have a mixed pad pitch and pad design.
• a set of first BGA pads 310 may have a first pitch 315 and a first size (e.g., diameter).
• a set of second BGA pads 320 may have a second pitch 325 and a second size (e.g., diameter).
• the first BGA pads 310 and second BGA pads 320 may be copper (Cu), or other conductive materials with high conductivity such as silver (Ag), gold (Au), aluminum (Al) and other like materials, alloys or combination of materials.
• Cu copper
• the various aspects are not limited to the illustrated patterns or to only two different pitches or sizes, as additional pitches and sizes may be defined in some aspects.
• the first BGA pads 310 are smaller in size (e.g., diameter) in comparison to the second of BGA pads 320.
• the second BGA pads 320 may be on the order of 10% to 100% larger than the first BGA pads 310.
• the second pitch 325 will be larger than the first pitch 315 and may be on the order of 10% to 100% larger than the first pitch. It will be appreciated that there may be a proportional increase in the pitch as the BGA pad size increases.
• various design considerations, such as pad density, pad to pad spacing, bottom routing and signal integrity may impact the ultimate size and pitch for a given design.
• the pad design may be different for each of the first BGA pads 310 (e.g., SMD pad design) and second BGA pads 320 (e.g., non-solder mask defined (NSMD) pad design), as discussed in the following.
• the mixed pad configuration according to the various aspects disclosed allow for variations in at least one of pad size, location or pitch to provide for greater design control.
• the first set of pads and the second set of pads are formed in a first metal layer of the package, which may be on a front side or a back side of the package of the package.
• the package in some aspects, may include a plurality of conductive layers and insulating layers. Further, it will be appreciated that the various aspects disclosed herein may be used in single sided BGA packages and double-sided BGA packages.
• FIG.4 illustrates details of a SMD pad design according to various aspects of the disclosure.
• the solder resist 410 has an overlay over a portion of the BGA pad 420.
• the solder resist opening (SRO) 412 is smaller than the BGA pad 420 and allows access to the BGA pad 420 through the solder resist 410.
• connection structure 430 is coupled to the BGA 420 during fabrication of the package.
• the connection structure 430 may be a solder ball or any suitable conductive structure for forming an electrical connection.
• the solder resist 410 may be any suitable material such as epoxy, liquid photoimageable ink, dry film photoimageable solder mask, and the like.
• the BGA pad 420 may be copper (Cu), or other conductive materials with high conductivity such as silver (Ag), gold (Au), aluminum (Al) and other like materials, alloys or combination of materials.
• Cu copper
• Au gold
• Al aluminum
• FIG. 5 illustrates details of a NSMD pad design 500 according to various aspects of the disclosure.
• the solder resist 510 has no overlay portion over the BGA pad 520.
• the solder resist opening (SRO) 512 is larger than the BGA pad 520.
• the SRO 512 allows access to the BGA pad 520 through the solder resist 510, including access to the sides of the BGA pad 520.
• connection structure 530 is coupled to the BGA 520 during fabrication of the package and in some examples the connection structure 530 can make contact with the entire bottom surface (surface facing the SRO 412) and sides of the BGA pad 520.
• the SRO 412 is smaller than the BGA pad 420.
• connection structure 530 may be a solder ball or any suitable conductive structure for forming an electrical connection.
• solder resist 510 may be any suitable material such as epoxy, liquid photoimageable ink, dry film photoimageable solder mask, and the like.
• the BGA pad 520 may be copper (Cu), or other conductive materials with high conductivity such as silver (Ag), gold (Au), aluminum (Al) and other like materials, alloys or combination of materials. It will be appreciated that these examples are provided solely for illustration and the SRO 512 increase may be greater or less than the example illustrated. Further, it will be appreciated that real world design constraints, such as minimum pitch spacing, number of BGA pads 520 used, fabrication limitations, etc., are design considerations that may impact the size, number, location, pitch, material, etc. of the various components illustrated.
• FIG. 6 illustrates components of an integrated device 600 according to one or more aspects of the disclosure.
• the package 620 may be configured to couple the die 610 to a PCB 690.
• the PCB 690 is also coupled to a power supply 680 (e.g., a power management integrated circuit (PMIC)), which allows the package 620 and the die 610 to be electrically coupled to the PMIC 680.
• PMIC power management integrated circuit
• one or more power supply (VDD) lines 691 and one or more ground (GND) lines 692 may be coupled to the PMIC 680 to distribute power to the PCB 690, package 620 via VDD BGA ball 625 and GND BGA ball 627 and to the die 610 via die bumps 612.
• VDD power supply
• GND ground
• BGA balls may be provided in addition the illustrated BGA balls 625 and 627.
• these BGA balls may be attached to a mixed pad in the package 620, according to one or more aspects disclosed herein.
• the VDD line 691 and GND line 692 each may be formed from traces, shapes or patterns in one or more metal layers of the PCB 690 (e.g., layers 1-6) coupled by one or more vias through insulating layers separating the metal layers 1-6 in the PCB 690.
• the PCB 690 may have one or more PCB capacitors (PCB cap) 695 that can be used to condition the power supply signals, as is known to those skilled in the art. Additional connections and devices may be coupled to and/or pass through the PCB 690 to the package 620 via one or more additional BGA balls (not illustrated) on the package 620. It will be appreciated that the illustrated configuration and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein.
• the PCB 690 may have more or less metal and insulating layers, there may be multiple lines providing power to the various components, etc. Accordingly, the forgoing illustrative examples and associated figures should not be construed to limit the various aspects disclosed and claimed herein.
• At least one aspect includes a package (e.g., 300) including a first set of pads (e.g., 310) having a first size and a first pitch (e.g., 315).
• the first set of pads may be solder mask defined (SMD) pads.
• the package further includes a second set of pads (e.g., 320) having a second size and a second pitch (e.g., 325).
• the second set of pads may be non-solder mask defined (NSMD) pads.
• a package with mixed pad size, spacing and/or pitch allows for package performance and reliability, by providing larger pads (e.g., the second set of pads 320) which may be NSMD pads for power and RF analog signals and still have smaller pads (e.g., first set of pads 310) which may be SMD pads with increased pad density (e.g., smaller pitch 315) for other signaling which is not available in conventional designs.
• larger pads e.g., the second set of pads 320
• first set of pads 310 which may be SMD pads with increased pad density (e.g., smaller pitch 315) for other signaling which is not available in conventional designs.
• FIG. 7 illustrates a flowchart of a method 700 for fabricating a package (e.g., 300 in FIG. 3) in accordance with some examples of the disclosure.
• the partial method 700 may begin in block 702 with forming a first set of pads having a first size and a first pitch, wherein the first set of pads are solder mask defined (SMD) pads.
• the partial method 700 may continue in block 704 with forming a second set of pads having a second size and a second pitch, wherein the second set of pads are non-solder mask defined (NSMD) pads.
• SMD solder mask defined
• the partial method 700 may continue in block 706 with forming a first set of solder resist openings for the first set of pads, wherein each of the first set of solder resist openings are smaller than each of the first set of pads.
• the partial method 700 may optionally continue in block 708 with forming a second set of solder resist openings for the second set of pads, wherein each of the second set of solder resist openings are larger than each of the second set of pads.
• each pad of the second set of pads may be larger than each pad of the first set of pads.
• the various sized pads can be formed using similar fabrication processes and materials. It will be appreciated from the foregoing disclosure that additional processes for fabricating the various aspects disclosed herein will be apparent to those skilled in the art and a literal rendition of the processes discussed above will not be provided or illustrated in the included drawings.
• FIG. 8 illustrates an exemplary mobile device in accordance with some examples of the disclosure.
• mobile device 800 may be configured as a wireless communication device.
• mobile device 800 includes processor 801.
• Processor 801 is shown to comprise instruction pipeline 812, buffer processing unit (BPU) 808, branch instruction queue (BIQ) 811, and throttler 810 as is well known in the art.
• BPU buffer processing unit
• BIQ branch instruction queue
• throttler 810 as is well known in the art.
• Other well-known details e.g., counters, entries, confidence fields, weighted sum, comparator, etc.
• Processor 801 may be communicatively coupled to memory 832 over a link, which may be a die-to-die or chip-to-chip link.
• Mobile device 800 also includes display 828 and display controller 826, with display controller 826 coupled to processor 801 and to display 828.
• FIG. 8 may include coder/decoder (CODEC) 834 (e.g., an audio and/or voice CODEC) coupled to processor 801; speaker 836 and microphone 838 coupled to CODEC 834; and wireless circuit 840, which may include a modem, RF circuitry, filters, etc., which may be implemented using one or more packages with mixed pads, as disclosed herein.
• the mixed pad package may be used in RFFE component(s).
• the wireless circuit 840 is coupled to wireless antenna 842 and to processor 801.
• processor 801, display controller 826, memory 832, CODEC 1234, and wireless circuit 840 can be included in a system-in-package or system-on-chip device 822 which may be implemented in whole or part using the mixed pad package designs disclosed herein.
• Input device 830 e.g., physical or virtual keyboard
• power supply 844 e.g., battery
• display 828 e.g., input device 830, speaker 836, microphone 838, wireless antenna 842, and power supply 844
• display 828 e.g., input device 830, speaker 836, microphone 838, wireless antenna 842, and power supply 844 may be external to system-on-chip device 822 and may be coupled to a component of system-on-chip device 822, such as an interface or a controller.
• FIG. 8 depicts a mobile device, processor, memory and other components may also be integrated into a set top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communications device, a mobile phone, or other similar devices.
• PDA personal digital assistant
• FIG. 9 illustrates various electronic devices that may be integrated with any of the aforementioned devices or semiconductor devices in accordance with various examples of the disclosure.
• a mobile phone device 902, a laptop computer device 904, and a fixed location terminal device 906 may each be consider generally user equipment (UE) and may include a package 900, including a mixed pad design as described herein.
• the package 900 may be, for example, at least part of any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, package-on-package devices described herein.
• the devices 902, 904, 906 illustrated in FIG. 9 are merely exemplary.
• Other electronic devices may also feature the package 900 including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), an Internet of things (loT) device or any other device that stores or retrieves data or computer instructions or any combination thereof.
• a group of devices e.g., electronic devices
• devices that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers
• the foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., register-transfer level (RTL), Geometric Data Stream (GDS) Gerber, and the like) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products may include semiconductor wafers that are then cut into semiconductor die and packaged into an integrated device including on or more dies and packages (e.g., flip-chip package). The packages may then be employed in devices described herein.
• RTL register-transfer level
• GDS Geometric Data Stream
• an apparatus may comprise a means for performing the various functionalities discussed above. It will be appreciated that the aforementioned aspects are merely provided as examples and the various aspects claimed are not limited to the specific references and/or illustrations cited as examples.
• One or more of the components, processes, features, and/or functions illustrated in FIGs. 1-9 may be rearranged and/or combined into a single component, process, feature or function or incorporated in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted that FIGs.
• a device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.
• IC integrated circuit
• IC integrated circuit
• PoP package on package
• the terms “user equipment” may interchangeably refer to any suitable mobile or stationary device that can receive wireless communication and/or navigation signals.
• a music player e.g., a music player, a video player, an entertainment unit, a navigation device, a communications device, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an automotive device in an automotive vehicle, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.).
• communication capabilities e.g., wireless, cellular, infrared, short-range radio, etc.
• These terms are also intended to include devices which communicate with another device that can receive wireless communication and/or navigation signals such as by short-range wireless, infrared, wireline connection, or other connection, regardless of whether satellite signal reception, assistance data reception, and/or position-related processing occurs at the device or at the other device.
• these terms are intended to include all devices, including wireless and wireline communication devices, that are able to communicate with a core network via a radio access network (RAN), and through the core network the UEs can be connected with external networks such as the Internet and with other UEs.
• RAN radio access network
• UEs can be embodied by any of a number of types of devices including but not limited to printed circuit (PC) cards, compact flash devices, external or internal modems, wireless or wireline phones, smartphones, tablets, tracking devices, asset tags, and so on.
• PC printed circuit
• a communication link through which UEs can send signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.).
• a communication link through which the RAN can send signals to UEs is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.).
• a downlink or forward link channel e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.
• traffic channel can refer to either an uplink / reverse or downlink / forward traffic channel.
• the wireless communication between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee/Thread) or other protocols that may be used in a wireless communications network or a data communications network.
• CDMA code division multiple access
• TDMA time division multiple access
• FDMA frequency division multiple access
• OFDM Orthogonal Frequency Division Multiplexing
• GSM Global System for Mobile Communications
• LTE Long Term Evolution
• LTE Long Term Evolution
• BLE Bluetooth Low Energy
• IEEE 802.11 WiFi
• IEEE 802.15.4 Zigbee/Thread
• Bluetooth Low Energy also known as Bluetooth LE, BLE, and Bluetooth Smart
• BLE was merged into the main Bluetooth standard in 2010 with the adoption of the Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.
• exemplary is used herein to mean “serving as an example, instance, or illustration.” Any details described herein as “exemplary” is not to be construed as advantageous over other examples. Likewise, the term “examples” does not mean that all examples include the discussed feature, advantage or mode of operation. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.
• any reference herein to an element using a designation such as “first,” “second,” and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements can comprise one or more elements.
• a block or a component of a device should also be understood as a corresponding method action or as a feature of a method action.
• aspects described in connection with or as a method action also constitute a description of a corresponding block or detail or feature of a corresponding device.
• Some or all of the method actions can be performed by a hardware apparatus (or using a hardware apparatus), such as, for example, a microprocessor, a programmable computer or an electronic circuit. In some examples, some or a plurality of the most important method actions can be performed by such an apparatus.
• Example aspect 1 includes an apparatus comprising a package, the package comprises: a first set of pads having a first size and a first pitch, wherein the first set of pads are solder mask defined (SMD) pads; and a second set of pads having a second size and a second pitch, wherein the second set of pads are nonsolder mask defined (NSMD) pads.
• SMD solder mask defined
• NSMD nonsolder mask defined
• Example aspect 2 which may be combined with the foregoing example aspect 1, includes wherein the first set of pads and the second set of pads are formed in a first metal layer of the apparatus.
• Example aspect 3 which may be combined with the foregoing example aspect 2, includes wherein the apparatus is covered by a solder resist with openings over the first set of pads and the second set of pads.
• Example aspect 4 which may be combined with the foregoing example aspect 3, further comprises: a first set of solder resist openings for the first set of pads, wherein each of the first set of solder resist openings are smaller than each of the first set of pads.
• Example aspect 6 which may be combined with the foregoing example aspects 1 to 5, includes wherein the first size of the first set of pads are generally uniform and smaller than the second size of the second set of pads.
• Example aspect 7 which may be combined with the foregoing example aspect 6, includes wherein each of the second set of pads is between 10% and 100% larger than each of the first set of pads.
• Example aspect 8 which may be combined with the foregoing example aspects 1 to 7, includes wherein the first pitch of the first set of pads are generally uniform and smaller than the second pitch of the second set of pads.
• Example aspect 9 which may be combined with the foregoing example aspect 8, includes wherein the second pitch is between 10% and 100% larger than each of the first pitch.
• Example aspect 10 which may be combined with the foregoing example aspects 1 to 10, includes wherein the apparatus is a single sided ball grid array (BGA) package or a double-sided ball grid array (BGA) package.
• BGA ball grid array
• BGA double-sided ball grid array
• Example aspect 11 which may be combined with the foregoing example aspects 1 to 11, wherein the apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (loT) device, a laptop computer, a server, and a device in an automotive vehicle.
• the apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (loT) device, a laptop computer, a server, and a device in an automotive vehicle.
• the apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a
• Example aspect 12 includes method for fabricating a package, the method comprising: forming a first set of pads having a first size and a first pitch, wherein the first set of pads are solder mask defined (SMD) pads; and forming a second set of pads having a second size and a second pitch, wherein the second set of pads are non-solder mask defined (NSMD) pads.
• SMD solder mask defined
• NSMD non-solder mask defined
• Example aspect 13 which may be combined with the foregoing example aspect 12, includes, wherein the first set of pads and the second set of pads are formed in a first metal layer of the package.
• Example aspect 14 which may be combined with the foregoing example aspects 12 and 13, includes, wherein the package is covered by a solder resist with openings over the first set of pads and the second set of pads.
• Example aspect 15 which may be combined with the foregoing example aspect 14, further comprises: forming a first set of solder resist openings for the first set of pads, wherein each of the first set of solder resist openings are smaller than each of the first set of pads.
• Example aspect 16 which may be combined with the foregoing example aspects 14 and
• Example aspect 17 which may be combined with the foregoing example aspects 12 to
• Example aspect 18 which may be combined with the foregoing example aspect 17, includes wherein each of the second set of pads is between 10% and 100% larger than each of the first set of pads.
• Example aspect 19 which may be combined with the foregoing example aspects 12 to 18, includes wherein the first pitch of the first set of pads are generally uniform and smaller than the second pitch of the second set of pads.
• Example aspect 20 which may be combined with the foregoing example aspect 19, includes wherein each of the second pitch is between 10% and 100% larger than each of the first pitch.
• Example aspect 21 which may be combined with the foregoing example aspects 12 to
• the package is a single sided ball grid array (BGA) package or double-sided ball grid array (BGA) package.
• BGA ball grid array
• BGA double-sided ball grid array
• Example aspect 21 which may be combined with the foregoing example aspects 12 to
• an individual action can be subdivided into a plurality of sub-actions or contain a plurality of sub-actions. Such sub-actions can be contained in the disclosure of the individual action and be part of the disclosure of the individual action.

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• 2020
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