JP2022535022A - 3次元メモリデバイスにおいて階段を形成するための方法および構造 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004020 conductor Substances 0.000 claims abstract description 95
- 230000008569 process Effects 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- -1 amorphous silicon Chemical compound 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000013341 scale-up Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Abstract
Description
102 基板
104 階段
106 導体層
108 誘電体層
110 3Dメモリストリング
112 メモリスタック
114 コンタクト
116 絶縁構造
200 製作プロセス
202 階段構造
202-1 階段
202-2 階段
204 誘電体層
206 犠牲層
208 側面
210 犠牲膜
300 製作方法
302 階段構造
302-1 階段
302-2 階段
304 誘電体層
306 犠牲層
308 側面
310 犠牲膜
312 絶縁層
312-1 絶縁層の第1の部分
312-2 絶縁層の第2の部分
320 導体層
320-1 導体層の頂部
320-2 導体層の底部
Claims (24)
- 交互配置された1つまたは複数の導体層と1つまたは複数の誘電体層とをそれぞれ備える複数の階段を含むメモリスタックを備える3次元(3D)メモリデバイスであって、
前記階段の各々が、前記階段の頂面上に前記導体層のうちの1つを備え、前記導体層のうちの前記1つが、(i)前記誘電体層のうちの1つに接触する底部と、(ii)前記メモリスタックによって露出されて前記底部に接触する頂部とを備え、
前記頂部の横方向の寸法が前記底部の横方向の寸法よりも小さく、
前記メモリスタックから遠位の前記頂部の終端が、ある距離だけ横方向に前記底部を超過する、3Dメモリデバイス。 - 前記頂部によって覆われ、横方向に前記距離を満たす絶縁部分をさらに備え、前記絶縁部分が、(i)前記底部と前記階段の側面における前記1つまたは複数の導体層の残りの部分とを覆い、(ii)それぞれの前記階段の真下の別の階段の頂部と接触する、請求項1に記載の3Dメモリデバイス。
- 前記頂部の頂面がそれぞれの前記階段の直上の第3の階段の底面よりも高い、請求項2に記載の3Dメモリデバイス。
- 前記距離が約0.1nm~約20nmの範囲である、請求項2に記載の3Dメモリデバイス。
- 前記距離が約1nm~約10nmの範囲である、請求項4に記載の3Dメモリデバイス。
- 前記絶縁部分が酸化シリコンまたは高誘電率(high-k)誘電体のうちの少なくとも1つを含む、請求項2に記載の3Dメモリデバイス。
- 前記メモリスタックが位置された絶縁構造と、
前記絶縁構造の中に延在して前記導体層のうちのそれぞれ1つの頂部に接触するコンタクトと
をさらに備える、請求項1から6のいずれか一項に記載の3Dメモリデバイス。 - 交互配置された1つまたは複数の導体層と1つまたは複数の誘電体層とをそれぞれ備える複数の階段を含むメモリスタックを備える3次元(3D)メモリデバイスであって、
前記階段の各々が、前記階段の頂面上に前記導体層のうちの1つを備え、前記導体層のうちの前記1つが、(i)前記誘電体層のうちの1つに接触する底部と、(ii)前記メモリスタックによって露出されて前記底部に接触する頂部とを備え、
前記メモリスタックから遠位の前記頂部の終端は、約0.1nm~約20nmの範囲のある距離だけ横方向に前記底部を超過する、3Dメモリデバイス。 - 前記距離が約1nm~約10nmの範囲である、請求項8に記載の3Dメモリデバイス。
- 前記頂部によって覆われ、横方向に前記距離を満たす絶縁部分をさらに備え、前記絶縁部分が、(i)前記底部と前記階段の側面における前記1つまたは複数の導体層の残りの部分とを覆い、(ii)それぞれの前記階段の真下の別の階段の頂部と接触する、請求項8または9に記載の3Dメモリデバイス。
- 前記頂部の横方向の寸法が前記底部の横方向の寸法よりも小さい、請求項8に記載のメモリデバイス。
- 前記絶縁部分が酸化シリコンまたは高誘電率(high-k)誘電体のうちの少なくとも1つを含む、請求項8に記載の3Dメモリデバイス。
- 前記メモリスタックが位置された絶縁構造と、
前記絶縁構造の中に延在して前記導体層のうちのそれぞれ1つの前記頂部に接触するコンタクトと
をさらに備える、請求項8から11のいずれか一項に記載の3Dメモリデバイス。 - 3次元(3D)メモリデバイスを形成するための方法であって、
交互配置された複数の犠牲層と複数の誘電体層とを備える誘電体スタックを形成するステップと、
前記誘電体スタックにおいて階段を形成するステップであって、前記階段が、前記複数の犠牲層のうちの1つまたは複数の犠牲層と、前記複数の誘電体層のうちの1つまたは複数の誘電体層とを備え、前記階段は、前記犠牲層のうちの1つを頂面に露出させ、前記1つまたは複数の犠牲層を側面に露出させる、ステップと、
前記1つまたは複数の犠牲層を覆うために、前記階段の側面を覆うように、絶縁部分を形成するステップと、
前記階段の前記頂面を覆うために犠牲部分を形成するステップであって、前記犠牲部分が犠牲層のうちの1つと接触する、ステップと、
前記1つまたは複数の犠牲層および前記犠牲部分を1つまたは複数の導体層で置き換えるステップと
を含む方法。 - 前記絶縁部分を形成するステップが、
前記階段を形成して、前記頂面における前記誘電体層のうちの1つを露出させるステップと、
絶縁層を形成して、前記階段の前記頂面および前記側面を覆うステップと、
前記階段の前記頂面における前記絶縁層の一部および前記誘電体層のうちの前記1つを除去して、犠牲層のうちの前記1つを露出させるステップであって、前記階段の前記側面における前記絶縁層の残りの部分が前記絶縁部分を形成する、ステップと
を含む、請求項14に記載の方法。 - 前記絶縁層を形成するステップが原子層堆積(ALD)を実施するステップを含む、請求項15に記載の方法。
- 前記絶縁層の前記一部を除去するステップが異方性エッチングプロセスを実施するステップを含む、請求項15または16に記載の方法。
- 前記絶縁層を形成するステップが酸化シリコンまたは高誘電率(high-k)誘電体のうちの少なくとも1つの層を堆積するステップを含む、請求項16に記載の方法。
- 前記犠牲部分を形成するステップが、
犠牲膜を形成して、前記階段の前記頂面における前記犠牲層のうちの少なくとも前記1つを覆うステップと、
前記階段の前記側面における前記犠牲膜の一部を除去して前記絶縁部分を露出させるステップであって、前記階段の前記頂面における前記犠牲膜の残りの部分が前記犠牲部分を形成する、ステップと
を含む、請求項14から18のいずれか一項に記載の方法。 - 前記絶縁層を形成するステップが、前記犠牲膜の材料とは異なる誘電材料の層を堆積するステップを含む、請求項19に記載の方法。
- 前記犠牲膜の前記一部を除去するステップが等方性エッチングプロセスを実施するステップを含む、請求項19に記載の方法。
- 前記犠牲膜を形成するステップが前記複数の犠牲層の材料と同じ犠牲材料の膜を堆積するステップを含む、請求項21に記載の方法。
- 前記1つまたは複数の犠牲層および前記犠牲部分を1つまたは複数の導体層で置き換えるステップが、
前記1つまたは複数の犠牲層および前記犠牲部分を除去して1つまたは複数の横方向陥凹を形成するステップと、
導体材料を堆積して前記横方向陥凹を埋めて、前記1つまたは複数の導体層を形成するステップと
を含む、請求項14から22のいずれか一項に記載の方法。 - 前記誘電体スタックが絶縁構造の中に収まるように、前記誘電体スタックを囲む絶縁構造を形成するステップと、
前記絶縁スタックの中に延在して前記階段の前記頂面における導体層に接触するコンタクトを形成するステップと
をさらに含む、請求項23に記載の方法。
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WO2022151033A1 (en) * | 2021-01-13 | 2022-07-21 | Yangtze Memory Technologies Co., Ltd. | Methods for forming stairs in three-dimensional memory devices |
CN113013174A (zh) * | 2021-03-26 | 2021-06-22 | 长江存储科技有限责任公司 | 一种三维存储器及其制备方法 |
CN112909005B (zh) * | 2021-03-26 | 2022-12-27 | 长江存储科技有限责任公司 | 一种三维存储器及其制备方法 |
CN113571523A (zh) * | 2021-07-21 | 2021-10-29 | 长江存储科技有限责任公司 | 三维存储器及其制备方法 |
WO2023070616A1 (en) * | 2021-10-30 | 2023-05-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having staircase structure and method for forming the same |
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---|---|
TW202119598A (zh) | 2021-05-16 |
US20210134830A1 (en) | 2021-05-06 |
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US20210249438A1 (en) | 2021-08-12 |
US20230095343A1 (en) | 2023-03-30 |
TWI749434B (zh) | 2021-12-11 |
KR20220002497A (ko) | 2022-01-06 |
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US11950418B2 (en) | 2024-04-02 |
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