JP2022183824A - Gate drive device - Google Patents

Abstract

To provide a gate drive device capable of quickly determining when a gate-drive type switching element is in a short-circuit state when driving a gate-drive type switching element.SOLUTION: A gate drive device that controls on/off by giving a gate drive signal to a gate-drive type semiconductor switching element by a drive circuit, comprises a determination circuit that detects the voltage between main terminals of the semiconductor switching element and determines the short-circuit state of the semiconductor switching element by the increase of the voltage between the main terminals during on drive, and a control circuit that shuts down the semiconductor switching element when the determination circuit determines the semiconductor switching element is in short circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to gate drives.

2. Description of the Related Art Some gate drive devices that drive and control power elements such as MOS transistors, which are gate-driven semiconductor switching elements, have a function of detecting a short circuit. As a method for detecting a short circuit, there is a Desat method. This utilizes the phenomenon that the drain-source voltage Vds does not drop if there is a short circuit at the time of an ON command. It is a judgment.

In the Desat method, a turn-on command increases the gate voltage of the power element, charges the capacitor Cdesat by the constant current Idesat, and increases the voltage at the Desat end, that is, the terminal voltage of the capacitor Cdesat.

In this case, normally, when the power element is turned on, the drain-source voltage Vds drops, so the constant current Idesat flows through the diode to the power element side, and charging of the capacitor Cdesat stops. The voltage at the end becomes lower than the short-circuit threshold and can be determined as normal.

On the other hand, when a short circuit occurs, the drain-source voltage Vds does not drop, so the charging of the capacitor Cdesat with the constant current Idesat continues, and the short circuit threshold value is exceeded before long, and the short circuit can be determined. Then, when a short circuit is determined, the gate driver lowers the gate voltage to cut off the power device.

However, in the Desat method of monitoring the drain-source voltage Vds of the power element and detecting a short circuit in this way, a short circuit determination may be delayed due to the influence of the wiring parasitic inductance Ls included in the current path of the power element. . A delay in short-circuit determination increases the short-circuit energy applied to the power element at the time of short-circuiting. Further, an increase in short-circuit energy leads to an increase in the size of the power element in order to provide resistance to this.

Japanese Patent No. 06525141 JP 2017-212870 A International publication number WO2017/141545A1

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and an object of the present invention is to be able to quickly determine if a short circuit has occurred when driving a gate-driven switching element. To provide a gate drive device capable of avoiding an increase in size by suppressing short-circuit energy.

According to a first aspect of the present invention, there is provided a gate drive device for controlling on/off by applying a gate drive signal to a gate drive type semiconductor switching element from a drive circuit, wherein a gate drive signal is applied between main terminals of the semiconductor switching element. and determines whether the semiconductor switching element is short-circuited based on an increase in the voltage between the main terminals during on-driving; and a control circuit (20) for shutting off the semiconductor switching element when a short-circuit state is determined.

In a configuration in which a semiconductor switching element is connected to the upper and lower arms to supply power to a load, there is wiring parasitic inductance, so if a short circuit occurs during switching operation, the voltage between the main terminals of the semiconductor switching element drops once and then rises again. It has the characteristic of coming. For this reason, in short-circuit determination by the generally used Desat method, there is a delay in the rise of the voltage between the main terminals to the threshold level, resulting in a determination delay.

On the other hand, in the present method, by adopting the above configuration, when the semiconductor switching element is driven, a change in the voltage between the main terminals, which is different between the normal state and the short-circuit state, is detected to determine the state of the short-circuit state. be able to.

That is, normally, the voltage across the main terminals of the semiconductor switching element is held at the lowest voltage in the ON state, but in the event of a short circuit, the voltage across the main terminals of the semiconductor switching element drops once and then rises again. Utilizing such a difference in characteristics, the determination circuit can determine the occurrence of a short circuit based on an increase in the voltage between the main terminals of the semiconductor switching element.

Therefore, unlike the system that waits until the voltage rises to a certain threshold value for detection, the short-circuit state can be determined quickly when the voltage turns to rise, and the semiconductor switching element used as the power element can be made smaller. can be improved.

Electrical configuration diagram showing the first embodiment Effect explanatory drawing which shows 1st Embodiment Electrical configuration diagram showing the second embodiment Timing chart showing the second embodiment Electrical configuration diagram showing the third embodiment Electrical configuration diagram showing the fourth embodiment Effect explanatory drawing which shows 4th Embodiment Electrical configuration diagram showing the fifth embodiment Action explanatory diagram shown for comparison

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 9. FIG.
In FIG. 1, which shows the electrical configuration, for a circuit in which IGBTs (Insulated Gate Bipolar Transistors) 1 as gate-driven semiconductor switching devices, which are power devices, are placed on the upper and lower arms to form a current-carrying path to a load. , the gate drive device 10 has a function to determine whether or not the other IGBT 1 is in a short-circuit state when controlling the ON drive of one IGBT 1 .

The gate drive device 10 includes a control circuit 20, a determination circuit 30, and the like. The control circuit 20 generates a gate drive signal Son based on an ON command signal of an ON/OFF command given from the outside, and applies a gate drive voltage Von to the gate of the IGBT 1 via the drive circuit 21 . As will be described later, the control circuit 20 also has an off-driving function for the IGBT 1, and cuts off the IGBT 1 when a short circuit is detected during on-driving.

The determination circuit 30 includes a bottom hold circuit 40 and a comparison circuit 50 having a comparator with hysteresis. The determination circuit 30 takes in the collector-emitter voltage (hereinafter simply referred to as "collector voltage") Vce of the IGBT 1, detects the presence or absence of a short circuit based on the changing state of this voltage, and outputs it.

The bottom hold circuit 40 has an operational amplifier 41 , a transistor 42 and a capacitor 43 . The operational amplifier 41 has a non-inverting input terminal to which the collector voltage Vce is input, and an inverting input terminal to which the terminal voltage Vbh of the capacitor 43 is input. The output terminal of operational amplifier 41 is connected to the base of transistor 42 .

The emitter of transistor 42 is connected to DC power supply VD through capacitor 43, and the collector is grounded. The terminal voltage Vph of the capacitor 43 is the voltage at the common connection point between the emitter of the transistor 42 and the capacitor 43 . The operational amplifier 41 turns on the transistor 42 during the period when the collector voltage Vce is lower than the bottom hold voltage Vbh, which is the terminal voltage of the capacitor 43 , and discharges the charge in the capacitor 43 .

As a result, when the collector voltage Vce rises after reaching the bottom voltage VB, the output signal of the operational amplifier 41 increases, the transistor 42 turns off, and the charging of the capacitor 43 stops. As a result, the bottom hold voltage Vbh, which is the terminal voltage of the capacitor 43, becomes the bottom voltage VB of the collector voltage Vce, and this voltage is held.

The comparison circuit 50 includes a comparator 51 and a hysteresis power supply 52 that provides a hysteresis voltage Vh. The comparator 51 has a non-inverting input terminal to which the collector voltage Vce is input, and an inverting input terminal to which the bottom hold voltage Vbh, which is the output voltage of the bottom hold circuit 40, is increased by the hysteresis voltage Vh through the hysteresis power supply 52 to obtain a reference voltage Vhys. is entered as

The comparator 51 outputs a determination signal Sd that is high level when the collector voltage Vce is higher than the reference voltage Vhys and low level when it is lower than the reference voltage Vhys. This determination signal Sd is output to the control circuit 20 and the outside.

Next, the operation of the above configuration will be described with reference to FIGS. 2 and 9 as well.
First, the cause of the problem with the Desat method and the detection method of this embodiment will be briefly described with reference to FIG. 9 using a configuration using MOS transistors. In a configuration in which upper and lower arms are provided to supply power to the load L, the wiring parasitic inductance Ls on the current path may adversely affect the detection operation in the Desat method. That is, when the MOS1 is turned on, d(Vds)/dt is generated by the parasitic inductance Ls when the drain voltage Vds changes with time. Due to the generation of this d(Vds)/dt, charge is drawn from the capacitor Cdesat by the junction capacitance of the diode connected to the drain of MOS1 from the detection circuit.

The amount of charge extracted from the capacitor Cdesat by d(Vds)/dt exceeds the amount of charge due to the current flowing from the detection circuit side by the constant current source, and the amount of discharge becomes larger than the amount of charge of the capacitance of Desat. , the Desat voltage may drop as shown. As a result, the Desat voltage rises again due to the charging operation after the charge extracted by d(Vds)/dt is charged, and when it reaches the threshold voltage, a short-circuit determination is made. At time t0, a short-circuit can be determined, but the short-circuit is determined at time t1, which is a delay of time T from when the Desat voltage drops until it returns to the original voltage, resulting in a large detection time delay. was becoming

This embodiment utilizes the fact that the voltage drop occurs due to the time change of the collector voltage Vce under the influence of the wiring parasitic inductance Ls. If a short-circuit state occurs when the IGBT 1 is driven on, it is detected by utilizing the characteristic that the collector voltage Vce drops once and then rises again.

The lower part of FIG. 2 shows how the collector voltage Vce changes after the drive voltage is applied to the gate of the IGBT 1 under normal conditions where no short circuit occurs. At time t0 when the gate voltage reaches the threshold voltage, the collector voltage Vce begins to drop from VCE. When the collector voltage Vce enters the mirror period, the slope of the drop from the voltage V1 becomes steep, and when it reaches the voltage V2, it turns on. That is, the collector voltage Vce of the IGBT 1 decreases to the voltage V2 through the voltage V1 when the gate driving signal is applied and the IGBT 1 starts to be turned on.

The upper and middle parts of FIG. 2 show the collector voltage Vce and the determination signal Sd in the normal state and the short-circuit state, respectively. First, in a normal state, when the control circuit 20 is turned on by an external on/off command, the driving circuit 21 is supplied with the on-driving signal Son, and the gate of the IGBT 1 is supplied with the gate driving voltage Von.

As a result, when the gate voltage Vg of the IGBT 1 reaches the threshold voltage at time t0, the collector voltage Vce drops from the voltage VCE by Ls·dIc/dt due to the time variation of the collector current Ic under the influence of the wiring parasitic inductance Ls. start. After that, when the gate voltage Vg enters the mirror period at time t1 and becomes constant, the collector voltage Vce further sharply drops. When the mirror period ends at time t2 and the collector current Ic reaches the load current, the IGBT1 is turned on and the collector voltage Vce becomes constant at a low voltage of approximately 0V. Since the collector voltage Vce at this time does not drop below this, it becomes the bottom voltage VB.

On the other hand, in the determination circuit 30 , the bottom hold circuit 40 takes in the collector voltage Vce and inputs it to the operational amplifier 41 . The bottom hold circuit 40 lowers the bottom hold voltage Vbh by driving the transistor 42 and charging the capacitor 43 while the collector voltage Vce is dropping. If the collector voltage Vce passes through the bottom voltage VB and is held at that voltage or rises, the transistor 42 is not driven and the bottom hold voltage Vbh is held at the bottom voltage VB.

In the comparison circuit 50 , the bottom hold voltage Vbh is input to the comparator 51 via the hysteresis power supply 52 as the reference voltage Vhys to which the hysteresis voltage Vh is added. Since the collector voltage Vce never exceeds the reference voltage Vhys, the comparator 51 determines that it is normal and outputs a low-level determination signal Sd.

Next, in the event of a short circuit, similarly, when the control circuit 20 is turned on by an on/off command from the outside, an on drive signal Son is given to the drive circuit 21 to apply the gate drive voltage Von to the gate of the IGBT 1. give.

As a result, when the gate voltage Vg of the IGBT 1 reaches the threshold voltage at time t0, the collector voltage Vce temporarily drops from the voltage VCE by Ls·dIc/dt due to the time variation of the collector current Ic under the influence of the wiring parasitic inductance Ls. After that, it rises again after time t1. Therefore, the bottom voltage VB of the collector voltage Vce becomes the voltage at time t1, which has once decreased.

On the other hand, in the determination circuit 30, the bottom hold circuit 40 detects the bottom voltage VB at the time t1 as the bottom hold voltage Vbh, and holds the bottom voltage VB. In the comparison circuit 50 , a reference voltage Vhys obtained by adding the hysteresis voltage Vh to the bottom hold voltage Vbh is input to the comparator 51 . Since the collector voltage Vce becomes higher than the reference voltage Vhys at the time tx in the middle of rising from the bottom voltage VB, the comparator 51 determines that a short circuit occurs and outputs a high-level determination signal Sd. As a result, the control circuit 20 turns off the IGBT 1 when the high-level determination signal Sd is input from the determination circuit 30 to cut off the IGBT 1 .

According to this embodiment, the bottom hold circuit 40 and the comparison circuit 50 are provided as the determination circuit 30, the reference voltage Vhys is generated from the bottom hold voltage of the collector voltage Vce, and the short circuit state is detected by comparison with the collector voltage Vce. Since it is determined, unlike the detection by the conventional Desat method, it is possible to detect a short circuit at an early stage, and it is necessary to use an IGBT 1 that has excessive resistance by shutting off the IGBT 1 early. This contributes to miniaturization of semiconductor switching elements used as power elements.

(Second embodiment)
3 and 4 show the second embodiment, and the differences from the first embodiment will be explained below. In this embodiment, when the bottom hold voltage Vbh of the collector voltage Vce is detected by the bottom hold circuit 40 of the determination circuit 30 as in the first embodiment, the bottom hold voltage Vbh can be reset at each switching.

In FIG. 3, the gate drive device 110 includes a determination circuit 30a instead of the determination circuit 30. FIG. The determination circuit 30 a includes a bottom hold circuit 40 a that replaces the bottom hold circuit 40 . The bottom hold circuit 40a has a configuration in which a reset switch 44 is added. The reset switch 44 is connected to short-circuit between both terminals of the capacitor 43 . Further, the reset switch 44 is turned on when a reset signal Sw is given from the control circuit 20 to short-circuit the terminals of the capacitor 43 to discharge electric charges.

Next, the operation of the above configuration will be described. FIG. 4 shows the changing state of the signal of each part. In this embodiment, the control circuit 20 holds the reset switch 44 in the off state by giving the reset signal Sw of reset release, ie, the low level, during the period when the on command signal is given by the on/off command. During the period in which the command signal is applied, the reset switch 44 is reset, that is, the reset signal Sw of high level is applied to keep it on.

As a result, when an ON command is given at the timing of time t0, the reset signal Sw of the reset switch 44 becomes low level and the reset is released. , the bottom hold voltage VB is output. As a result, the operation of the determination process described above is performed.

After that, when the ON command is switched to the OFF command at time t1, the control circuit 20 outputs a high-level reset signal Sw to the reset switch 44 to perform a reset operation, discharge the charge of the capacitor 43, and restore the bottom hold voltage Vbh. to the voltage VCE. The bottom hold voltage Vbh is held at the voltage VCE during the period in which the OFF command is given.

When the ON command is given again at time t2, the control circuit 20 cancels the reset signal Sw until the OFF command is given at time t3. Thereafter, in the same manner as described above, even when the collector voltage Vce fluctuates due to reset cancellation at each switching, the bottom hold voltage Vbh changes to the bottom voltage VB at that time. It can be operated so that it can follow.

According to the second embodiment, the bottom hold circuit 40a is provided with the reset switch 44 to reset the bottom hold voltage Vbh at each switching. It becomes possible to accurately detect the bottom hold voltage Vbh.

In addition to the above-described embodiment in which the reset is performed while the OFF command is given, it can also be performed in a short period of time immediately after the OFF command is given if there is no adverse effect due to noise or the like.

(Third embodiment)
FIG. 5 shows a third embodiment, and portions different from the first embodiment will be described below. In this embodiment, the gate drive device 120 does not take in the collector voltage Vce of the IGBT 1 directly, but takes in the divided collector voltage Vced via the voltage dividing circuit 2 .

The voltage dividing circuit 2 is formed by connecting voltage dividing resistors 2a and 2b in series. This is the configuration for obtaining the voltage collector voltage Vced.

A high voltage may be applied to the collector depending on how the IGBT 1 is used. In such a case, the gate drive device 120 needs a configuration capable of handling a high voltage even in a configuration in which the high voltage collector voltage Vce is taken in and the determination circuit 30 performs determination. However, by making it possible to handle the divided collector voltage Vced as in this embodiment, it is possible to reduce the size and cost.
The voltage dividing circuit 2 is not limited to the configuration of the voltage dividing resistors 2a and 2b, and may be configured to divide the voltage by two capacitors.

(Fourth embodiment)
FIGS. 6 and 7 show a fourth embodiment, and the differences from the first embodiment will be explained below. In this embodiment, as the gate drive device 130, as shown in FIG. 6, a filter 53 is provided at the output stage of the comparison circuit 50a of the determination circuit 30b. The filter 53 has a function of a low-pass filter for removing noise, and removes noise superimposed on the collector voltage Vce or the like to output the determination signal Sd.

As a result, for example, as shown in FIG. 7, in the determination circuit 30b, the input collector voltage Vce is the one at the time of short circuit, and after the high-level determination signal Sd for determining the short circuit state is output at time tx, , when noise is superimposed on the collector voltage Vce at time ty, there is a possibility that the determination signal Sd temporarily outputs an erroneous detection pulse of low level.

On the other hand, in this embodiment, even if a high-level signal caused by noise is output in the pre-filtered determination signal Sd at time ty, the determination signal Sd output through the filter 53 is noise. Since the high-level signal portion due to is removed, the detection operation is performed without erroneous detection.

(Fifth embodiment)
FIG. 8 shows a fifth embodiment, and portions different from the first embodiment will be described below.
In this embodiment, as shown in FIG. 8, the gate drive device 140 is provided with a variable hysteresis power supply 54 capable of changing the hysteresis voltage Vh instead of the hysteresis power supply 52 as the comparison circuit 50b in the determination circuit 30c. It is configured.

By changing and setting the hysteresis voltage Vh using the variable hysteresis power supply 54, it is possible to set the hysteresis voltage Vh appropriately so as not to cause malfunction due to noise generated in the system. Since the amount of noise varies in the system, the occurrence of malfunctions can be suppressed by adjusting the hysteresis voltage Vh according to the amount of noise.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions can be made.

In each of the above-described embodiments, an IGBT is used as a power element, but the present invention can be applied to any gate-driven semiconductor switching element of a power system such as a SiCMOS transistor, in addition to the IGBT.
Each of the above-described embodiments is based on the first embodiment and shown as an application thereof, but of course it can be applied to other embodiments in a complex manner.

Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 is an IGBT (gate-driven semiconductor switching element), 2 is a voltage dividing circuit, 10, 110, 120, and 130 are gate driving devices, 20 is a control circuit, 21 is a driving circuit, 30, 30a, 30b, 30c is a judgment circuit, 40 and 40a are bottom hold circuits, 41 is an operational amplifier, 42 is a transistor, 43 is a capacitor, 44 is a reset switch, 50, 50a and 50b are comparison circuits, 51 is a comparator, 52 is a hysteresis power supply, and 53 is a hysteresis power supply. Filter 54 is a variable hysteresis power supply.

Claims (5)

A gate drive device for controlling on/off by applying a gate drive signal from a drive circuit to a gate drive type semiconductor switching element,
a determination circuit (30, 30a, 30b, 30c) for detecting a voltage across the main terminals of the semiconductor switching element and determining a short-circuit state of the semiconductor switching element based on an increase in the voltage across the main terminals during on-driving;
and a control circuit (20) for shutting off the semiconductor switching element when the determination circuit determines that the semiconductor switching element is short-circuited. The determination circuit is
a bottom hold circuit (40, 40a) for holding the bottom voltage of the voltage between the main terminals of the semiconductor switching element;
A comparison circuit (50, 50a, 50b) for determining a short-circuit state when the voltage between the main terminals of the semiconductor switching element becomes larger than a reference voltage obtained by adding the hysteresis voltage to the bottom voltage. 2. The gate drive device according to 1. 3. The gate drive device according to claim 2, wherein the bottom hold circuit includes a reset switch (44) that resets holding of the bottom voltage when the semiconductor switching element is turned off. 4. The gate drive device according to claim 2, wherein said comparison circuit comprises a variable hysteresis power supply (54) capable of adjusting said hysteresis voltage. A voltage dividing circuit (2) that divides the voltage between the main terminals of the semiconductor switching element,
5. The gate according to any one of claims 2 to 4, wherein the determination circuit inputs a voltage between main terminals of the semiconductor switching element divided by the voltage dividing circuit to determine a short-circuit state of the semiconductor switching element. drive.

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