JP7427949B2 - gate drive circuit - Google Patents

Description

The technology disclosed herein relates to a gate drive circuit.

The gate drive circuit disclosed in Patent Document 1 turns off the switching element by discharging the gate of the switching element and lowering the gate voltage. This gate drive circuit detects the rate of decrease in gate voltage at the initial stage of turn-off, and changes the electrical resistance of the discharge path according to the rate of decrease. This appropriately controls the surge voltage applied between the main electrodes of the switching element.

JP2009-273071A

In the technique of Patent Document 1, the electrical resistance of the discharge path is not changed during the period from when a surge voltage occurs until the voltage between the main electrodes stabilizes. Therefore, the current flowing between the main electrodes decreases slowly during this period, and the switching loss occurring in the switching element is large. This specification proposes a technique for suppressing surge voltage and reducing switching loss.

The gate drive circuit disclosed herein turns off the switching element by discharging the gate of the switching element and lowering the gate voltage of the switching element. This gate drive circuit includes a current detection circuit, a reference value setting circuit, and a gate resistance changing circuit. The current detection circuit detects a main current flowing between main electrodes of the switching element before turning off. The reference value setting circuit sets a reference value based on the main current detected by the current detection circuit. The gate resistance changing circuit changes the electrical resistance of the discharge path of the gate. The gate resistance changing circuit controls the electrical resistance to a first value during a period in which a reference value, which is either the gate voltage or the main current, is equal to or greater than a reference value when turning off the switching element, and During a period in which the electrical resistance is less than the reference value, the electrical resistance is controlled to a second value lower than the first value. When turning off the switching element, the main voltage between the main electrodes of the switching element increases from a first voltage to a second voltage, and then from the second voltage to a third voltage higher than the first voltage. It decreases to a certain level and then becomes stable. Switching of the electrical resistance from the first value to the second value is performed within a period between a timing when the main voltage becomes the second voltage and a timing when the main voltage stabilizes at the third voltage. Ru. The reference value setting circuit sets the reference value to a higher value as the main current detected by the current detection circuit increases.

In this gate drive circuit, the electrical resistance of the discharge path is switched from the first value to the second value within the period between the timing when the main voltage becomes the second voltage and the timing when the main voltage stabilizes at the third voltage. executed. Therefore, at the timing when the main voltage becomes the second voltage (that is, the timing at which a surge voltage occurs), the electrical resistance of the discharge path is set to the first value (that is, a high resistance value). Therefore, generation of excessive surge voltage is suppressed. Further, after that, the electrical resistance of the discharge path is switched from the first value to the second value (lower resistance value) until the main voltage stabilizes at the third voltage. Therefore, the main current decreases quickly after the surge voltage occurs. Therefore, switching loss is suppressed. Furthermore, the above-mentioned switching of the electrical resistance of the discharge path is performed by comparing a reference value (either the gate voltage or the main current) with a reference value. During turn-off, the reference value decreases. If the reference value is set to an appropriate value, the electrical resistance of the discharge path can be switched within the above period by switching the electrical resistance of the discharge path when the reference value becomes lower than the reference value. . Here, the timing at which the main current starts to decrease when the switching element is turned off varies depending on the magnitude of the main current before the switching element is turned off. The larger the main current before turn-off is, the earlier the main current starts to decrease. Therefore, the larger the main current before turn-off, the earlier the timing at which the surge voltage occurs. In this gate drive circuit, the larger the main current before turn-off is, the higher the reference value is set. Therefore, the larger the main current before turn-off is, the earlier the timing for switching the electrical resistance of the discharge path from the first value to the second value becomes. Therefore, the earlier the timing at which the surge voltage occurs, the earlier the timing at which the electrical resistance of the discharge path is switched. In this way, by setting the reference value according to the magnitude of the main current before turn-off, it is possible to set the timing for switching the electrical resistance of the discharge path according to the timing of occurrence of the surge voltage. Therefore, according to this gate drive circuit, even if the magnitude of the main current before turn-off is different, the electrical resistance of the discharge path can be switched at an appropriate timing.

Circuit diagram of an inverter circuit. FIG. 3 is a circuit diagram of a gate drive circuit of Example 1. 5 is a flowchart showing turn-off processing in the first embodiment. 5 is a graph showing changes in each value in the turn-off process of Example 1. A table showing a method of calculating a reference value Vgb. A graph showing the relationship between current Ids18 and gate voltage Vg18. A graph showing temperature characteristics of gate voltage Vg18 and current Ids18. FIG. 3 is a circuit diagram of a gate drive circuit according to a second embodiment. 7 is a graph showing changes in each value in the turn-off process of Example 2.

The inverter circuit 10 shown in FIG. 1 has three series circuits 17 connected between a high potential wiring 12 and a low potential wiring 14. Each series circuit 17 has two FETs (field effect transistors) 18 connected between a high potential wiring 12 and a low potential wiring 14. Each FET 18 is of n-channel type. In each series circuit 17, the drain of FET 18a is connected to high potential wiring 12, the source of FET 18a is connected to the drain of FET 18b, and the source of FET 18b is connected to low potential wiring 14. The inverter circuit 10 has three intermediate wirings 16. One end of each intermediate wiring 16 is connected to the source of the FET 18a (ie, the drain of the FET 18b) of the corresponding series circuit 17. The other end of each intermediate wire 16 is connected to the motor 11. A gate drive circuit 30 is connected to the gate of each FET 18. Gate drive circuit 30 controls FET 18. A DC voltage is applied between the high potential wiring 12 and the low potential wiring 14 from the outside. The inverter circuit 10 converts DC power supplied from the outside into AC power, and supplies the AC power to the motor 11 .

FIG. 2 shows one FET 18 and a gate drive circuit 30 that controls the FET 18. As shown in FIG. 2, the gate drive circuit 30 includes a current sense resistor 32, a temperature sense diode 34, a control IC 40, a gate charge circuit 44, and a gate discharge circuit 50.

The current sense resistor 32 is connected to a current sense FET 19 provided in the same semiconductor substrate as the FET 18. The drain of current sense FET 19 is connected to the drain of FET 18. The gate of current sense FET 19 is connected to the gate of FET 18. The source of current sense FET 19 is connected to the source of FET 18 via current sense resistor 32. Current sense FET 19 turns on and off simultaneously with FET 18. Current sense FET 19 is smaller than FET 18. Therefore, a current Ids19 flows through the current sense FET 19, which is smaller than the drain-source current Ids18 flowing through the FET 18 and is proportional to the current Ids18. Current Ids19 flows through current sense resistor 32. Therefore, the voltage Vsen across the current sense resistor 32 is proportional to the current Ids18 of the FET 18.

Temperature sense diode 34 is placed near FET 18. A constant current source 36 is connected to the temperature sense diode 34 . Constant current source 36 causes a constant current to flow through temperature sense diode 34 . The temperature of the temperature sense diode 34 is approximately equal to the temperature T18 of the FET 18. The forward voltage drop of the temperature sense diode 34 changes depending on the temperature T18 of the FET 18. Although the temperature sense diode 34 is shown as one diode in FIG. 2, the temperature sense diode 34 may be formed of a plurality of diodes connected in series.

A PWM signal is input to the control IC 40 from the outside. The control IC 40 generates a command value for instructing whether to turn the FET 18 on or off based on the PWM signal, and transmits the command value to the gate charging circuit 44 and the gate discharging circuit 50.

Gate charging circuit 44 includes a control FET 46 and a gate-on resistor 48. Control FET 46 is of n-channel type. The source of the control FET 46 is connected to a wiring 49 to which voltage VH is applied. Voltage VH is a potential higher than the lowering start threshold of FET 18. The drain of control FET 46 is connected to the gate of FET 18 via gate-on resistor 48. The gate of the control FET 46 is connected to the control IC 40. The control FET 46 switches according to a command value input from the control IC 40. When the control FET 46 is turned on, a gate current flows from the wiring 49 toward the gate of the FET 18 via the control FET 46 and the gate-on resistor 48, and the gate of the FET 18 is charged.

The gate discharge circuit 50 includes a first control FET 52, a first gate-off resistor 54, a capacitor 55, a second control FET 56, a second gate-off resistor 58, an AND circuit 60, a comparator 62, and a reference value calculation section 64. .

The first control FET 52 is of n-channel type. The drain of the first control FET 52 is connected to the gate of the FET 18 via a first gate-off resistor 54. A capacitor 55 is connected in parallel to the first gate-off resistor 54. Note that the capacitor 55 may be omitted. The source of the first control FET 52 is connected to ground. Note that in this embodiment, the ground means the potential of the source of the FET 18. The gate of the first control FET 52 is connected to the control IC 40. The first control FET 52 switches according to a command value input from the control IC 40. When the first control FET 52 is turned on, a gate current flows from the gate of the FET 18 to the ground via the first gate-off resistor 54 and the first control FET 52, and the gate of the FET 18 is discharged.

The second control FET 56 is of n-channel type. The drain of the second control FET 56 is connected to the gate of the FET 18 via a second gate-off resistor 58. The source of the second control FET 56 is connected to ground. An output terminal of an AND circuit 60 is connected to the gate of the second control FET 56. The second control FET 56 switches according to the signal input from the AND circuit 60. When the second control FET 56 is turned on, a gate current flows from the gate of the FET 18 to the ground via the second gate-off resistor 58 and the second control FET 56, and the gate of the FET 18 is discharged.

The reference value calculation unit 64 is connected to both ends of the current sense resistor 32. The reference value calculation unit 64 detects the current Ids18 flowing through the FET 18 based on the voltage Vsen across the current sense resistor 32. The reference value calculation unit 64 is connected to both ends of the temperature sense diode 34. The reference value calculation unit 64 detects the temperature T18 of the FET 18 based on the voltage across the temperature sense diode 34 (ie, forward voltage drop). The reference value calculation unit 64 calculates the reference value Vgb based on the current Ids18 and the temperature T18. The reference value calculation unit 64 may calculate the reference value Vgb using a mathematical formula or may calculate the reference value Vgb using a map. The method for calculating the reference value Vgb will be described in detail later.

A non-inverting input terminal of the comparator 62 is connected to an output terminal of the reference value calculation section 64. The reference value Vgb is input to the non-inverting input terminal of the comparator 62. The gate voltage Vg18 of the FET 18 is input to the inverting input terminal of the comparator 62. The comparator 62 controls the output signal to be Low when the gate voltage Vg18 is greater than or equal to the reference value Vgb, and controls the output signal to be High when the gate voltage Vg18 is less than the reference value Vgb.

The output signal of the comparator 62 is input to one input terminal of the AND circuit 60 . A command value is input from the control IC 40 to the other input terminal of the AND circuit 60 . The AND circuit 60 controls its own output signal to High when all the signals input to the input terminals are High, and controls its own output signal to Low in other cases. The output signal of the AND circuit 60 is input to the gate of the second control FET 56.

Next, the operation of the gate drive circuit 30 to turn off the FET 18 will be explained. FIG. 3 shows the steps performed by gate drive circuit 30 when turning off FET 18. Further, FIG. 4 shows changes in each value when the FET 18 is turned off. In the period T0 before turn-off, the control FET 46 is on, and the first control FET 52 and the second control FET 56 are off. Therefore, the gate voltage Vg18 of the FET 18 is the voltage VH, and the FET 18 is turned on. Therefore, in the period T0, the drain-source voltage Vds18 of the FET 18 is approximately 0V, and the drain-source current Ids18 of the FET 18 is large.

The gate drive circuit 30 executes steps S2 and S4 shown in FIG. 3 during the period T0 (more specifically, immediately before timing t1). In step S2, the reference value calculation unit 64 detects the current Ids18 flowing through the FET 18 and the temperature T18 of the FET 18. In step S4, the reference value calculation unit 64 calculates the reference value Vgb based on the detected current Ids18 and temperature T18. The reference value Vgb changes depending on the current Ids18 and the temperature T18, but in any case, the reference value Vgb is lower than the voltage VH and higher than 0V. During the period T0, the gate voltage Vg18 of the FET 18 is the voltage VH (that is, a voltage higher than the reference value Vgb), so the output voltage of the comparator 62 is Low. Therefore, the output voltage of the AND circuit 60 (ie, the gate voltage Vg56 of the second control FET 56) becomes Low.

The gate drive circuit 30 executes step S6 at timing t1. In step S6, the control IC 40 turns off the control FET 46 and turns on the first control FET 52. At timing t1, the output voltage of the AND circuit 60 (that is, the gate voltage Vg56 of the second control FET 56) is maintained at Low, so the second control FET 56 is maintained off. When each of the control FETs 46, 52, and 56 is controlled in this manner at timing t1, the gate of the FET 18 is separated from the wiring 49 (that is, the voltage VH) by the control FET 46, and the first control FET 52 and the first gate-off resistor 54 connected to ground by Then, a gate current flows from the gate of the FET 18 to the ground via the first control FET 52 and the first gate-off resistor 54, and the gate of the FET 18 is discharged. Therefore, the gate voltage Vg18 of the FET 18 decreases after timing t1. Note that when a capacitor 55 is connected in parallel to the first gate-off resistor 54, rapid discharge occurs through the capacitor 55 at timing t1, so that the gate voltage Vg18 rapidly reaches a predetermined value at timing t1. descend.

At timing t2 after timing t1, gate voltage Vg18 decreases to a predetermined voltage Vgth (hereinafter referred to as a reduction start threshold). Then, the current Ids18 flowing through the FET 18 starts to decrease. Further, the drain-source voltage Vds18 of the FET 18 increases. At this time, a surge voltage is applied to the FET 18 due to the influence of the decrease in the current Ids18 and the parasitic inductance of the circuit. The surge voltage is applied immediately after timing t2. Therefore, immediately after timing t2, voltage Vds18 rises to peak voltage Vdsp1. Thereafter, voltage Vds18 decreases until timing t3. As described above, the gate of the FET 18 is discharged via the first gate-off resistor 54 during the period T1 between the timing t1 and the timing t3. The electrical resistance of the first gate-off resistor 54 is relatively high. Therefore, during the period T1, the current Ids18 is prevented from changing at an extremely high rate of change. This prevents the peak voltage Vdsp1 of the voltage Vds18 from becoming an extremely high value.

As shown in FIG. 3, the gate drive circuit 30 repeatedly executes step S8 after timing t1. In step S8, the comparator 62 determines whether the gate voltage Vg18 has decreased to less than the reference value Vgb. In FIG. 4, at timing t3, gate voltage Vg18 decreases to reference value Vgb. Therefore, at timing t3, the gate drive circuit 30 executes step S10. In step S10, the comparator 62 switches the output voltage from Low to High. Then, the output voltage of the AND circuit 60 (ie, the gate voltage Vg56 of the second control FET 56) is switched from Low to High. Therefore, at timing t3, the second control FET 56 is turned on. Therefore, after timing t3, the gate of the FET 18 is discharged not only through the discharge path consisting of the first control FET 52 and the first gate-off resistor 54, but also through the discharge path consisting of the second control FET 56 and the second gate-off resistor 58. . As a result, the electrical resistance of the discharge path that discharges the gate of the FET 18 is reduced. Therefore, after timing t3, the discharge rate of the gate (that is, the rate of decrease in gate voltage Vg18) increases. Thereafter, at timing t4, the current Ids18 decreases to zero, and the turn-off of the FET 18 is completed.

In the graph of the current Ids18 in FIG. 4, the solid line shows the case where the control method of this embodiment is implemented (the case where the second control FET 56 is turned on at timing t3), and the broken line shows the case where the second control FET 56 is turned on at the timing t3. It shows the case where it is not done. As shown in the broken line graph, when the second control FET 56 is not turned on, the rate of decrease in the current Ids18 slows down as time passes. Therefore, in the broken line graph, the time required for the current Ids18 to decrease to zero is long, and the switching loss generated in the FET 18 is large. In contrast, in the solid line graph, the current Ids18 decreases faster after timing t3 when the second control FET 56 is turned on. Therefore, the time required for the current Ids18 to decrease to zero is short, and the switching loss generated in the FET 18 is small. In this manner, the gate drive circuit 30 of this embodiment can reduce the switching loss that occurs when turning off the FET 18.

Further, when the second control FET 56 is turned on at timing t3, a second surge voltage is generated and the voltage Vds18 rises to the second peak voltage Vdsp2. This is because the current Ids18 decreases faster at timing t3. In FIG. 4, ringing (vibration) occurs in the voltage Vds18 after timing t3. The oscillation of voltage Vds18 attenuates over time. When the vibration is attenuated, the voltage Vds18 becomes stable at the voltage VM. The voltage VM has a value lower than the peak voltages Vdsp1 and Vdsp2 and higher than the voltage Vds18 (that is, approximately 0V) in the period T0. In this way, the voltage Vds18 fluctuates and changes to the voltage VM after timing t3. Since the current Ids18 has already decreased to a certain low value at timing t3, even if the second control FET 56 is turned on at timing t3 to reduce the electrical resistance of the discharge path, a very high surge voltage will not occur. That is, the second peak voltage Vdsp2 of the voltage Vds18 does not have a very large value.

As described above, according to the gate drive circuit 30 of the first embodiment, it is possible to suppress the switching loss of the FET 18 while suppressing the generation of high surge voltage. Although the case in which ringing occurs in the voltage Vds18 has been described in FIG. 4, there may be cases where ringing does not occur.

Next, a method for calculating the reference value Vgb in step S4 will be explained. As shown in FIG. 5, the reference value calculation unit 64 calculates the reference value Vgb according to the current Ids18 and the temperature T18 detected in step S2. The reference value calculation unit 64 increases the reference value Vgb as the current Ids18 becomes larger, and increases the reference value Vgb as the temperature T18 becomes higher. By changing the reference value Vgb in this way, switching loss can be suppressed more effectively. This will be explained in detail below.

As shown in FIG. 4, the reference value Vgb needs to be set so that the timing t3 at which the second control FET 56 is turned on is later than the timing at which the surge voltage occurs. For this purpose, the reference value Vgb needs to be lower than the lowering start threshold Vgth. However, if the reference value Vgb is too low with respect to the reduction start threshold Vgth, the timing t3 for turning on the second control FET 56 will be excessively delayed, and the effect of suppressing switching loss will hardly be obtained. The decrease start threshold Vgth varies depending on the current Ids18 flowing through the FET 18 and the temperature T18 of the FET 18. Therefore, if the reference value Vgb is appropriately set with respect to the fluctuating lowering start threshold Vgth, switching loss can be suppressed more effectively.

FIG. 6 shows the relationship between the gate voltage Vg18 and the current Ids18 when turning off the FET 18. FIG. 6 shows cases in which the current Ids18 in the on state is about 460 A, about 250 A, and about 150 A, respectively. In FIG. 6, the gate voltage Vg18 when the current Ids18 starts to decrease is the decrease start threshold Vgth. As is clear from FIG. 6, the higher the current Ids18, the higher the lowering start threshold Vgth. As described above, the reference value calculation unit 64 increases the reference value Vgb as the current Ids18 becomes higher. Therefore, the higher the decrease start threshold Vgth, the higher the reference value Vgb. In this way, since the reference value Vgb is changed in accordance with the variation of the drop start threshold Vgth due to the current Ids18, variations in the difference between the drop start threshold Vgth and the reference value Vgb are suppressed. Therefore, in FIG. 4, the timing t3 for turning on the second control FET 56 may be extremely later than the timing at which the surge voltage (peak voltage Vdsp1) occurs, or may be extremely delayed at the timing at which the surge voltage (peak voltage Vdsp1) occurs. This prevents them from getting too close. Therefore, switching loss of the FET 18 can be effectively suppressed.

FIG. 7 shows the relationship between the current Ids18 of the FET 18 and the gate voltage Vg18. FIG. 7 shows the relationship when the FET 18 is at high temperature, medium temperature, and low temperature. As is clear from FIG. 7, when the gate voltage Vg18 is lowered at a constant rate, when the FET 18 is at a low temperature, the current Ids18 is faster (the gate voltage Vg18 is higher) than when the FET 18 is at a high temperature. decrease in stages). That is, in the case of a low temperature, the gate voltage Vg18 (that is, the decrease start threshold Vgth) when the current Ids18 starts decreasing is higher than that in the case of a high temperature. As described above, the reference value calculation unit 64 increases the reference value Vgb as the temperature T18 increases. Therefore, the higher the decrease start threshold Vgth, the higher the reference value Vgb. In this way, since the reference value Vgb is changed in accordance with the variation of the decrease start threshold Vgth due to the temperature T18, variations in the difference between the decrease start threshold Vgth and the reference value Vgb are suppressed. Therefore, the timing t3 at which the second control FET 56 is turned on may be extremely later than the timing at which the surge voltage (peak voltage Vdsp1) occurs, or extremely close to the timing at which the surge voltage (peak voltage Vdsp1) occurs. Prevented. Therefore, switching loss of the FET 18 can be effectively suppressed.

As described above, according to the gate drive circuit 30 of the first embodiment, the reference value Vgb can be appropriately set according to the current Ids18 and the temperature T18, so that switching loss can be suppressed more effectively.

FIG. 8 shows a gate drive circuit 130 according to the second embodiment. In the second embodiment, the configuration of the gate discharge circuit 50 is different from that in the first embodiment. In the second embodiment, the drain of the second control FET 56 is directly connected to the gate of the FET 18. Furthermore, in the second embodiment, the gate discharge circuit 50 does not include the capacitor 55. Further, in the second embodiment, the gate discharge circuit 50 includes a low-pass filter 151, a sample-hold circuit 152, a comparator 154, a flip-flop circuit 156, an OR circuit 158, and an OFF-holding circuit 160. A sense voltage Vsen across the current sense resistor 32 is input to the sample hold circuit 152 via the low pass filter 151. The sample and hold circuit 152 continuously outputs the input sense voltage Vsen for a certain period of time. Therefore, the output voltage of the sample and hold circuit 152 is proportional to the current Ids18 a predetermined time ago. The output voltage of the sample and hold circuit 152 is divided by resistors R1 and R2. In the second embodiment, the voltage divided by the resistors R1 and R2 is used as the reference value Vsenb. The reference value Vsenb is input to the non-inverting input terminal of the comparator 154. The sense voltage Vsen is input to the inverting input terminal of the comparator 154. The output signal of the comparator 154 is input to the S terminal of the flip-flop circuit 156. A command value is input from the control IC 40 to the R terminal of the flip-flop circuit 156 . A Q terminal of the flip-flop circuit 156 is connected to an input terminal of an OR circuit 158. The output terminal of the OFF holding circuit 160 is connected to the other input terminal of the OR circuit 158. The output terminal of the OR circuit 158 is connected to the gate of the second control FET 56. An input terminal of the off-holding circuit 160 is connected to the gate of the FET 18. The OFF holding circuit 160 outputs a signal indicating whether the potential of the gate of the FET 18 has decreased to approximately 0V.

Next, the operation of the gate drive circuit 130 of Example 2 will be explained using FIG. 9. During period T10 in FIG. 9, the control FET 46 is on and the first control FET 52 is off. Further, in period T10, the output signal of the off-holding circuit 160 is Low, and the output signal of the flip-flop circuit 156 is Low. Therefore, during the period T10, the second control FET 56 is off. Therefore, during the period T10, the gate voltage Vg18 is maintained at the voltage VH, and the FET 18 is turned on. During period T10 (more specifically, just before timing t11), sample and hold circuit 152 reads sense voltage Vsen. Therefore, after that, the output signal of the sample and hold circuit 152 is maintained at the sense voltage Vsen during the period T10. Therefore, the reference value Vsenb is a value obtained by dividing the sense voltage Vsen in the period T10.

At timing t11, the control IC 40 turns off the control FET 46 and turns on the first control FET 52. Therefore, at timing t11, the gate of the FET 18 starts discharging, and the gate voltage Vg18 starts decreasing. After timing t11, the comparator 154 monitors whether the sense voltage Vsen is lower than the reference value Vsenb. That is, the comparator 154 determines whether the current Ids18 is lower than the current value Ids18b corresponding to the reference value Vsenb. At timing t12, current Ids18 starts decreasing, and at timing t13, current Ids18 falls below current value Ids18b. Then, the comparator 154 switches the output signal from Low to High. Then, the flip-flop circuit 156 switches the output signal from Low to High. Then, the OR circuit 158 switches the output signal from Low to High. Therefore, at timing t13, the second control FET 56 is turned on, and the electrical resistance of the discharge path decreases. Therefore, after timing t13, the rate of decrease of current Ids18 becomes faster, and switching loss is suppressed. When the gate voltage Vg18 drops to approximately 0V at timing t14, the output voltage of the OFF holding circuit 160 becomes High. Therefore, the second control FET 56 is maintained on even after timing t14.

In the off-operation of the second embodiment described above, the gate is discharged via the gate-off resistor 54 at timing t12, so the peak voltage Vdsp1 does not have a very large value. Furthermore, since the current Ids18 at timing t13 is relatively small, the peak voltage Vdsp2 does not have a very large value. In this way, in the second embodiment as well, switching loss can be reduced while suppressing the generation of high surge voltage.

Further, in the second embodiment, the second control FET 56 is turned on when the current Ids18 becomes lower than the current value Ids18b corresponding to the reference value Vsenb. If the current value Ids18b is a fixed value, when the current Ids18 is large in the period T10, the time difference between the timing t12 when the current Ids18 starts to decrease and the timing t13 when the current Ids18 decreases to the current value Ids18b becomes large, and a surge occurs. The time difference between the timing at which the voltage (peak voltage Vdsp1) is generated and the timing t13 becomes large. Further, when the current Ids18 in the period T10 is small, the time difference between the timing t12 when the current Ids18 starts to decrease and the timing t13 when the current Ids18 decreases to the current value Ids18b becomes small, and a surge voltage (peak voltage Vdsp1) occurs. The time difference between the timing t13 and the timing t13 becomes smaller. As described above, when the current value Ids18b is a fixed value, the variation in the time difference between the timing at which the surge voltage (peak voltage Vdsp1) occurs and the timing t13 increases. In contrast, in the gate drive circuit 130 of the second embodiment, the reference value Vsenb is a value obtained by dividing the sense voltage Vsen in the period T10. Therefore, the reference value Vsenb becomes higher as the current Ids18 in the period T10 becomes larger. That is, the current value Ids18b corresponding to the reference value Vsenb increases as the current Ids18 in the period T10 increases. Therefore, variations in the time difference between the timing at which the surge voltage (peak voltage Vdsp1) occurs and the timing t13 are unlikely to occur. Timing t13 is prevented from becoming extremely later than the timing at which the surge voltage (peak voltage Vdsp1) occurs or from becoming extremely close to the timing at which the surge voltage (peak voltage Vdsp1) occurs. Therefore, switching loss of the FET 18 can be effectively suppressed.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims as filed. Further, the techniques illustrated in this specification or the drawings simultaneously achieve multiple objectives, and achieving one of the objectives has technical utility in itself.

18:FET
19: Current sense FET
30: Gate drive circuit 32: Current sense resistor 34: Temperature sense diode 36: Constant current source 44: Gate charging circuit 46: Control FET
48: Gate on resistance 49: Wiring 50: Gate discharge circuit 52: First control FET
54: First gate-off resistor 55: Capacitor 56: Second control FET
58: Second gate-off resistor 60: AND circuit 62: Comparator 64: Reference value calculation section

Claims (1)

A gate drive circuit that turns off the switching element by discharging the gate of the switching element to lower the gate voltage of the switching element, the gate driving circuit comprising:
a current detection circuit that detects a main current flowing between main electrodes of the switching element before turn-off;
a reference value setting circuit that sets a reference value based on the main current detected by the current detection circuit;
The gate resistance changing circuit changes the electrical resistance of the discharge path of the gate, and when the switching element is turned off, the gate resistance changing circuit changes the electric resistance of the discharge path of the gate in a period in which a reference value, which is either the gate voltage or the main current, is equal to or higher than the reference value. a gate resistance changing circuit that controls the electrical resistance to a first value, and controls the electrical resistance to a second value lower than the first value during a period when the reference value is less than the reference value;
has
When turning off the switching element, the main voltage between the main electrodes of the switching element increases from a first voltage to a second voltage, and then from the second voltage to a third voltage higher than the first voltage. It decreases to and then stabilizes.
Switching of the electrical resistance from the first value to the second value is performed within a period between a timing when the main voltage becomes the second voltage and a timing when the main voltage stabilizes at the third voltage. ,
The reference value setting circuit sets the reference value to a higher value as the main current detected by the current detection circuit increases;
Gate drive circuit.

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