JP5056405B2 - Switching device - Google Patents

Description

  The present invention relates to a switching device for a semiconductor switching element.

As a conventional technique, a driving device for a power semiconductor element that changes a resistance value of a gate resistance of a voltage-driven power semiconductor element is known (for example, see Patent Document 1). Patent Document 1 discloses a first drive circuit that drives a power semiconductor element via a first resistor, and a first drive circuit that drives the power semiconductor element via a second resistor having a resistance value lower than the first resistance. Two drive circuits, a slope detection circuit for detecting a rate of change of the gate voltage of the power semiconductor element over time, and operations of the first drive circuit and the second drive circuit based on an output signal from the slope detection circuit. A control device that controls the first drive circuit to drive the power semiconductor element at an initial stage of the switching operation of the power semiconductor element, and from the slope detection circuit Based on the output signal, the second drive circuit starts driving the power semiconductor element during a mirror period in which the gate voltage of the power semiconductor element is constant. To control the drive apparatus is disclosed of the power semiconductor device.
JP 2007-166655 A

  By the way, the time change rate of the gate voltage can fluctuate due to factors such as variations in semiconductor elements, aging, temperature characteristics, and the resistance value of the gate resistance. May occur.

  In this regard, the above-described conventional technology includes a timer circuit that outputs a delay signal obtained by delaying the output signal from the slope detection circuit by a predetermined time to the control circuit, thereby reliably switching the drive circuit in the mirror period. However, it is necessary to set an appropriate delay time in advance, so the semiconductor device turns on when the time change rate of the gate voltage cannot be detected correctly only by providing the timer circuit. Sometimes malfunction cannot be prevented.

  Therefore, an object of the present invention is to provide a switching device that can prevent malfunction when a semiconductor switching element is turned on.

In order to achieve the above object, a switching device for a semiconductor switching element according to the present invention comprises:
By detecting that the time change rate of the gate voltage of the semiconductor switching element exceeds a first reference value and then falls below a second reference value different from the first reference value, the sign of the time change rate is Sign change detecting means for detecting a change;
And switching means for changing a driving voltage or a driving current for turning on the switching element in accordance with a detection timing of a change in the sign of the time change rate detected by the sign change detecting means.

  According to the present invention, it is possible to prevent malfunction when the semiconductor switching element is turned on.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a motor / generator drive system 100 which is an embodiment of a switching device according to the present invention. The motor / generator drive system 100 includes an in-vehicle battery 10 of a DC power source, a DC-DC converter 20 that boosts the output voltage of the battery 10, and an output voltage that has been boosted by the DC-DC converter 20 (hereinafter, “boosted voltage”). And a smoothing capacitor 30 that stabilizes the voltage and the inverter 40 that controls the motor 50 by converting the boosted voltage by the DC-DC converter 20 into a three-phase alternating current. Note that the inverter 40 may control electric power generated by the generator 60. Further, the DC-DC converter 20 may step down the input voltage from the inverter 40 side and output the stepped down voltage to the battery 10 side.

  The DC-DC converter 20 boosts and converts the voltage on the battery 10 side by a voltage conversion control circuit such as a switching regulator, and outputs the boosted voltage to the inverter 40 side (or converts the voltage on the inverter 40 side into a step-down converter). The step-down voltage is output to the 10 side). This boosted voltage (voltage on the inverter 40 side) is applied to both ends of each phase series circuit in the inverter 40 to which the upper arm side switching element and the lower arm side switching element are connected. The voltage conversion control circuit includes, for example, an upper arm side switching element Q13 having a diode D13 in parallel between a collector and an emitter, a lower arm side switching element Q14 having a diode D14 in parallel between a collector and an emitter, and one end thereof. Reactor 25 is connected to the connection point of element Q13 and element Q14, and the other end is connected to the output potential of battery 10, drive circuit E13 for driving element Q13, and drive circuit E14 for driving element Q14. Since the step-up conversion operation and the step-down conversion operation are well known, description thereof is omitted.

  The positive terminal 22p of the DC-DC converter 20 is connected to the positive input terminal 41p of the inverter 40 via the positive wiring 70p. Further, the negative terminal 22n of the DC-DC converter 20 is connected to the negative input terminal 41n of the inverter 40 via the negative wiring 70n.

  The inverter 40 includes a control circuit 46 for the motor 50 and a control circuit 47 for the generator 60. The control circuit 46 outputs a drive circuit E1 (E2) that outputs a signal for switching the U-phase switching element Q1 (Q2), and a drive circuit E3 (E4) that outputs a signal for switching the V-phase switching element Q3 (Q4). And a drive circuit E5 (E6) for outputting a signal for switching the W-phase switching element Q5 (Q6). The control circuit 46 controls the on / off of each switching element in accordance with a three-phase (U, V, W) drive signal (for example, PWM signal), thereby converting the DC power after boosting by the DC-DC converter 20 to AC. The motor 50 is driven by converting into electric power. That is, the rotation of the motor 50 is controlled by utilizing the fact that a rotating magnetic field is generated when a three-phase alternating current is passed through the three-phase winding of the motor 50 by the control circuit 46. The control circuit 47 of the generator 60 has the same configuration as that of the control circuit 46 except for the control method of the control circuit 46, and the description thereof will be omitted.

  Note that the switching elements Q1 to Q14 are voltage-driven elements composed of semiconductors such as N-channel IGBTs and N-channel MOSFETs.

  The switching elements Q1, 3, and 5 are high-side switching elements that are short-circuited to the power supply voltage of the positive input terminal 41p of the inverter 40. The switching elements Q2, 4, and 6 are the ground voltage ( This is a low-side switching element that is short-circuited to a reference voltage. A diode is connected in parallel (or built in) to each switching element Q1-6. Each of the diodes D1 to D6 has a forward direction from the ground to the power supply voltage (a direction from the emitter to the collector) (the power supply voltage side is a cathode). That is, the anode is connected to the emitter of the switching element, and the cathode is connected to the collector of the switching element. The same applies to the switching elements Q13 and Q14.

  A connection point Pu between the switching elements Q1 and Q2 is connected to a U-phase coil of the motor 50 via a U-phase output terminal 42u of the inverter 40. A connection point Pv between the switching elements Q3 and Q4 is connected to a V-phase coil of the motor 50 via a V-phase output terminal 42v of the inverter 40. A connection point Pw between the switching elements Q5 and Q6 is connected to a W-phase coil of the motor 50 via a W-phase output terminal 42w of the inverter 40.

  FIG. 2 is a diagram for explaining a detailed configuration example of the U-phase high-side drive circuit of inverter 40. A shown in FIG. 2 is a control IC that controls the switching element Q1. Here, since the U-phase low-side drive circuit of the inverter 40 and the high-phase and low-side drive circuits of the other phases may have the same configuration, the description thereof is omitted. Further, each switching element may be controlled by one control IC, or each switching element may be controlled by a plurality of control ICs. The voltage conversion control circuit of the DC-DC converter 20 may have the same configuration.

  The switching element Q1 is a high-side switching element that is short-circuited to the power supply voltage VD of the DC power supply (corresponding to the power supply voltage of the positive input terminal 41p). A diode D1 is connected (or incorporated) in parallel between the collector and emitter of the switching element Q1. The diode D1 is a free wheel diode (or a parasitic diode) whose forward direction is the direction from the ground to the power supply voltage (the direction from the emitter to the collector). The emitter of switching element Q1 is connected to the collector of switching element Q2, and its connection point Pu is connected to the U-phase coil of motor 50.

  Further, the control unit G1 outputs a drive signal for switching the switching element Q1 according to a Q1 control signal input from an input terminal MIN from a control device such as a microcomputer (not shown), and turns on / off the switching element Q1.

  In the case of FIG. 2, the control unit G1 turns on the switching element Q1 via the gate resistor R1 by turning on a transistor M1 (for example, a P-channel MOSFET) which is a normal switch for turning on to turn on the switching element Q1. Turn on. That is, when the transistor M1 is turned on, the gate of the switching element Q1 is charged with the gate drive voltage VDD (for example, 15 V) via the gate resistor R1, so that the switching element Q1 can be turned on.

  Further, the control unit G1 switches the transistor M6 (for example, a P-channel MOSFET), which is a high-speed switch for turning on to make the turn-on speed of the switching element Q1 higher than usual, thereby reducing the gate resistance of the switching element Q1. Can be varied. That is, when the transistor M6 is turned on, the resistor R3 is connected in parallel to the resistor R1, so that the resistance value of the gate resistance of the switching element Q1 can be reduced.

  Further, the control unit G1 turns off the switching element Q1 via the gate resistor R2 by turning on a transistor M2 (for example, an N-channel MOSFET) which is a normal switch for turning off for turning off the switching element Q1. . That is, when the transistor M2 is turned on, the gate of the switching element Q1 is discharged via the gate resistor R2, and thus the switching element Q1 can be turned off.

  The gate voltage change rate detection circuit H1 detects a gate voltage change rate dVge / dt representing a change rate with respect to time of the gate voltage Vge of the switching element Q1. The gate voltage change rate detection circuit H1 includes a transistor T1 (npn type) whose collector is connected to the power supply and whose base is connected to the gate of the switching element Q1, a current source I2 connected to the emitter of the transistor T1, and a transistor T1 A high-pass filter including a capacitor C1 connected to the emitter and a resistor R5 is provided. The output waveform of the bypass filter (that is, the output waveform of the gate voltage change rate detection circuit H1) corresponds to a waveform representing the gate voltage change rate dVge / dt.

  The comparator CMP1 outputs an on timing signal for determining the on timing of the high speed switch M6. The comparator CMP1 compares the gate voltage change rate dVge / dt of the non-inverting input terminal with the threshold value VthLo of the inverting input terminal. The threshold value VthLo can be set to an appropriate value by voltage division between the resistors R6 and R7 outside the control IC and the resistor R4 inside the control IC.

  The comparator CMP2 outputs an enable signal for allowing the high-speed switch M6 to be turned on. The comparator CMP2 compares the gate voltage change rate dVge / dt of the non-inverting input terminal with the threshold VthHi of the inverting input terminal. The threshold value VthHi is, for example, a value offset by the resistor R4 and the current source I1 so as to be larger than the threshold value VthLo. As described above, by providing hysteresis to the comparison reference voltage (threshold values VthHi and VthLo) of the gate voltage change rate dVge / dt, malfunction due to the influence of noise can be prevented.

  FIG. 3 shows an edge-triggered waveform shaping circuit configured in the control unit G1. The high-speed turn-on signal odrm6 corresponding to the drive signal for the high-speed switch M6 is generated by ANDing the output results of the comparators CMP1 and CMP2. That is, when the falling edge of the on-timing signal idvge_x of the comparator CMP1 is detected in a state where the enable signal idvdtp of the comparator CMP2 is at a Hi level (an enable state indicating an on-permitted state of the high-speed switch M6), When the turn-on signal odrm6 is turned on, the high-speed switch M6 is turned on.

  Here, in the case of FIG. 3, a one-shot pulse generation circuit is provided in order to prevent malfunction due to high-frequency noise. The one-shot pulse generation circuit receives a delay circuit g2 that delays the on-timing signal idvge_x of the comparator CMP1, an inversion circuit g3 that inverts the logic of the on-timing signal idvge_x, an output of the delay circuit g2, and an output of the inversion circuit g3 And a one-shot pulse having a delay time width by the delay circuit g2 is output to the AND circuit g5. In the case of FIG. 3, the delay circuit g2 is provided with a delay time by 10 buffers. Therefore, when the one-shot pulse generation circuit is provided, when the falling edge of the one-shot pulse is detected when the enable signal idvdtp of the comparator CMP2 is in the Hi level (enable state), the Lo-level fast turn-on signal When odrm6 becomes Hi level, the high-speed switch M6 is turned on. Even when high-frequency noise having a period shorter than the one-shot pulse width occurs, it is possible to prevent malfunctions in which the high-speed switch M6 is turned on earlier than the original because the timing at which the high-speed turn-on signal odrm6 becomes Hi level is advanced. . This is because when the high-speed switch M6 is turned on earlier than the design value, a recovery surge generated in a diode parallel to the switching element is increased.

  The set / reset flip-flop g7 is turned on when a Q1 control signal for commanding the turn-off of the switching element Q1 is input from the input terminal MIN (corresponding to imin in FIG. 3) (at the timing when the Q1 control signal is turned off). The state fast turn-on signal odrm6 is turned off. When the high-speed turn-on signal odrm6 is turned off, the high-speed switch M6 is turned off.

  FIG. 4 is an operation waveform diagram of the circuit diagram shown in FIG. When a Q1 control signal for turning on the switching element Q1 is input to the input terminal MIN, the normal switch M1 is turned on. The switching element Q1 is charged with the gate resistor R1. The gate voltage Vge increases according to the CR curve of the gate resistance and the gate capacitance. Therefore, as illustrated, the gate voltage change rate dVge / dt draws a curve that gradually rises to zero after rapidly rising in the initial stage of charging. However, since the waveform representing the gate voltage change rate dVge / dt at this time strongly depends on the temperature and the type of the switching element, the peak value may vary.

  When the gate voltage change rate dVge / dt exceeds the threshold value VthHi of the comparator CMP2, the high-speed switch M6 is enabled when the enable signal idvdtp of the comparator CMP2 becomes Hi level.

  Subsequently, when the gate voltage Vge exceeds the gate-on threshold value of the switching element Q1, the collector current Ice settles to a steady value after a large current value flows for a moment. When the current change rate dIce / dt representing the current change with respect to time of the collector current Ice at this time is large, a recovery surge is generated in the diode D2 parallel to the switching element Q2 connected in series with the switching element Q1 (see FIG. 1).

  FIG. 5 is a diagram for explaining the generation timing of the surge between the collector and the emitter of the switching element Q. As a surge generated between the collector and the emitter of the switching element Q, there are an off surge generated when the switching element Q is turned off and a recovery surge generated in a diode connected in parallel to the switching element Q. When switching element Q1 (Q2) is turned off, an off-surge is generated between the collector and emitter of switching element Q1 (Q2). Also, when one switching element is turned off and the other switching element is turned on, the voltage applied to the diode connected in parallel to the one switching element is switched from the forward voltage to the reverse voltage, so that a recovery surge is applied to the diode. Will occur. That is, when the switching element Q1 (Q2) is turned off and the switching element Q2 (Q1) is turned on, a recovery surge is generated in the diode D1 (D2) connected in parallel to the switching element Q1 (Q2).

  If this recovery surge is too large, the diode and the switching element may be destroyed. Therefore, in the state 1 shown in FIG. 4, the current change rate dIce / dt is set by keeping the resistance value of the gate resistor R1 large. Reduces and suppresses recovery surge.

  The state 2 shown in FIG. 4 will be described. As the collector current Ice becomes a steady value, the collector voltage Vce also decreases. At this time, since the collector-gate capacitance Ccg is entered into the mirror region, the gate voltage Vge becomes a substantially constant value, and the gate voltage change rate dVge / dt approaches zero. In the region where the collector current Ice becomes a steady value and no recovery surge occurs, the falling edge when the gate voltage change rate dVge / dt is less than or equal to the threshold value VthLo is detected by the comparator CMP1 and the one-shot pulse generation circuit. In addition to the normal switch M1, the high-speed switch M6 is also turned on. By turning on the high-speed switch M6, the resistance value of the gate resistance of the switching element Q1 becomes smaller than that in the state 1 (R1 // R3 = (R1 × R3) / (R1 + R3)). Thereby, the charging speed of the gate of the switching element Q1 is increased, and the turn-on speed is increased while the switching element Q1 is turned on, so that the turn-on loss of the switching element Q1 can be reduced. The description of the case of reducing the turn-on loss of the other switching element Q is omitted, but the same can be considered.

  The state 3 shown in FIG. 4 will be described. When the collector voltage Vce reaches the saturation voltage Vce (sat), the gate voltage Vge starts to rise again, and eventually becomes constant at the gate drive voltage VDD. In state 3, since collector current Ice and collector voltage Vce are steady values, there is no relation to turn loss or recovery surge loss (steady state). That is, since the gate resistance value is irrelevant, the high-speed switch M6 may be on or off. FIG. 4 shows an operation waveform in which the high-speed switch M6 is turned on.

  Therefore, according to the above-described embodiment, the on-timing of the high-speed switch M6 is generated according to the detection timing capturing the sign change (change from positive to negative) of the magnitude of the gate voltage change rate dVge / dt, Since the drive voltage or drive current for turning on the switching element is changed, it is possible to prevent malfunction caused by actively changing the gate drive of the switching element by detecting the time change rate of the gate voltage. That is, detecting that the sign of the magnitude of the gate voltage change rate dVge / dt changes from positive to negative means detecting that the rising gate voltage subsequently falls. The high speed switch M6 can be reliably turned on in a region where the ratio dVge / dt is small, and surge can be prevented from increasing.

  In addition, since the gate voltage change rate dVge / dt is compared with two threshold voltages VthLo, it is possible to reliably detect a sign change of the magnitude of the gate voltage change rate dVge / dt. In the configuration in which the gate voltage change rate dVge / dt is compared with one threshold voltage, the gate voltage change rate dVge / dt having a large variation may not reach the threshold voltage. For example, when the gate voltage change rate dVge / dt falls without reaching the threshold voltage, if the high-speed switch is in an enabled state, the on-timing of the high-speed switch is advanced, and a surge occurs greatly (in the case of FIG. 4). If so, the high-speed switch may be turned on in the state 1 region). However, in the above-described embodiment having a configuration in which the gate voltage change rate dVge / dt is compared with two threshold voltages, the high-speed switch M6 is enabled only when the gate voltage change rate dVge / dt exceeds the threshold voltage VthHi. Even if the gate voltage change rate dVge / dt is lower than expected and does not exceed the threshold voltage VthHi for some reason, the high-speed switch M6 does not turn on, but the on-loss of the high-speed switch M6 cannot be reduced. The inconvenience that the surge voltage becomes large can be prevented, and stable control can be realized.

  Further, a comparator CMP1 that compares the gate voltage change rate dVge / dt and the threshold voltage VthLo, and a comparator CMP2 that compares the gate voltage change rate dVge / dt and the threshold voltage VthHi are configured. With this configuration, the threshold voltage can be directly adjusted via the terminal AGCTH of the control IC, and the on-state of the high-speed switch M6 can be adjusted by a test before shipment. A reliable switching element can be turned on.

  The threshold value VthHi may be set to a value lower than the threshold value VthLo. However, in order to reliably detect the sign change of the magnitude of the gate voltage change rate dVge / dt, the threshold value VthHi is set as in the above-described embodiment. It is preferable to set VthHi to a value higher than the threshold value VthLo.

  Further, the parasitic capacitance between the gate and the emitter of the switching element is a huge capacitance value on the order of about 0.001 μm to 0.01 μF, and the gate voltage Vge is a voltage generated in this parasitic capacitance. There is an advantage that it is not easily affected by switching noise. That is, erroneous detection of the gate voltage change rate detection circuit H1 can be prevented. Even if switching noise enters the gate voltage Vge, erroneous detection of the gate voltage change rate detection circuit H1 can be prevented by setting the enable threshold value VthHi high.

  Further, since the high speed switch M6 detects the falling edge of the output of the comparator CMP1 and holds it by the set / reset flip-flop g7, the high speed switch M6 does not matter whether the gate voltage change rate dVge / dt crosses the threshold value VthLo many times. Since chattering does not occur, stable control is possible.

  That is, in state 2, when the gate voltage change rate dVge / dt falls below VthLo, the falling of the output of the comparator CMP1 is detected, and the high-speed switch M6 is held on. Since the gate voltage Vge is charged at high speed when the high-speed switch M6 is turned on, the magnitude of the gate voltage change rate dVge / dt increases and may exceed the threshold value VthLo depending on conditions. However, since the ON state of the high-speed switch M6 is already held, stable control can be realized without causing chattering.

  FIG. 6 shows a simulation drive waveform when the transistor M6 is not turned on at high speed. FIG. 7 shows a simulation drive waveform when the transistor M6 is turned on at high speed.

  A simulation result of switching energy applied to a switching element (in this case, an IGBT) per turn-on is shown surrounded by a dotted line. In the case of FIG. 6, it is about 77.5 [mJ], whereas in the case of FIG. 7, it is about 52.9 [mJ], and the switching energy is reduced by 32%. The peak value of the collector current Ice of the switching element, which is almost proportional to the recovery surge voltage, is about 41.1 [A] in the case of FIG. 6 and about 41.2 [A] in the case of FIG. There is no. Therefore, according to the present embodiment, the recovery surge is prevented by preventing the malfunction due to the active change of the gate drive of the switching element by detecting the time change rate of the gate voltage while suppressing the loss of the switching energy. It can be prevented from increasing.

  It is also possible to reduce the surge voltage of the recovery surge while suppressing the turn-on loss by adjusting the resistance value (R1, R3) of the gate resistance or the threshold value (VthLo, VthHi). That is, the trade-off characteristics of the turn-on loss and the suppression of the recovery surge voltage can be improved.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, in the above-described embodiment, the on-timing of the high-speed switch M6 is generated using the two comparators CMP1 and 2, but the sign of the magnitude of the gate voltage change rate dVge / dt is obtained by using two stages of differential circuits in series. The change point may be detected (that is, the vicinity of the apex of the gate voltage change rate dVge / dt waveform is detected), and the high-speed switch M6 may be turned on according to the detection timing. At this time, in order to prevent erroneous detection, the high speed switch M6 may be turned on after a delay time by a delay means such as a timer elapses after detection of a sign change point having a magnitude of the gate voltage change rate dVge / dt.

  Further, the means for obtaining the voltage waveform representing the gate voltage change rate dVge / dt is not limited to the above-described high-pass filter including the capacitor C1 and the resistor R5, but the gate voltage change rate detection as shown in FIGS. It may be a circuit.

  In the above-described embodiments, the driving voltage or driving current for turning on the switching element is changed by changing the gate resistance of the switching element. However, the driving voltage itself (for example, the gate driving voltage VDD) or the current source is changed. For example, the drive current itself may be varied.

  In the above-described embodiment, the switching device according to the present invention has been described by taking an in-vehicle control system as an example. However, the present invention is not limited to a vehicle and can be applied to other uses such as a robot. is there.

1 is a schematic configuration diagram of a motor / generator drive system 100 that is an embodiment of a switching device according to the present invention. 3 is a diagram for explaining a detailed configuration example of a U-phase high-side drive circuit of an inverter 40. FIG. It is an edge trigger type waveform shaping circuit configured in the control unit G1. FIG. 3 is an operation waveform diagram of the circuit diagram shown in FIG. 2. FIG. 5 is a diagram for explaining the occurrence timing of a surge between the collector and emitter of a switching element Q. This is a simulation drive waveform when the transistor M6 is not turned on at high speed. It is a simulation drive waveform when the transistor M6 is turned on at high speed. It is an example of a detection circuit of a gate voltage change rate. It is an example of a detection circuit of a gate voltage change rate.

Explanation of symbols

A Control IC
C * Capacitor CMP * Comparator D * Diode G1 Controller M * Transistor Q * Switching element R * Resistance VD Power supply voltage

Claims (5)

A switching device for a semiconductor switching element,
By detecting that the time change rate of the gate voltage of the semiconductor switching element exceeds a first reference value and then falls below a second reference value different from the first reference value, the sign of the time change rate is Sign change detecting means for detecting a change;
And switching means for changing a driving voltage or a driving current for turning on the switching element in accordance with a detection timing of a change in the sign of the time change rate detected by the sign change detecting means. apparatus. 2. The switching device according to claim 1 , wherein the switching unit changes the drive voltage or the drive current in accordance with a timing at which the time change rate falls below the second reference value. 3. The switching device according to claim 2 , wherein the switching unit changes the drive voltage or the drive current after a delay time has elapsed from a time point when the time change rate falls below the second reference value. 4. The switching device according to claim 1, wherein the first reference value is set to a value higher than the second reference value. 5. The switching device according to any one of claims 1 to 4 , wherein the switching unit changes a resistance value of a gate resistance of the switching element.

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