JP2022027921A - Tワイヤと画素電極との間の減少した容量結合を伴う狭額縁電気光学ディスプレイバックプレーンのためのビアの設置 - Google Patents
Tワイヤと画素電極との間の減少した容量結合を伴う狭額縁電気光学ディスプレイバックプレーンのためのビアの設置 Download PDFInfo
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- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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Abstract
Description
本願は、2018年2月15日に出願された米国仮特許出願第62/631,261号の優先権を主張する。本明細書に引用または議論される特許および特許出願全ては、参照することによって、それらの全体として本明細書に組み込まれる。
本発明は、例えば、以下の項目を提供する。
(項目1)
電気光学ディスプレイであって、前記電気光学ディスプレイは、
ドライバチップと、
基板を備えているバックプレーンと
を備え、
前記基板は、画素電極のアレイを備えている表側を含み、前記画素電極のアレイは、画素行と画素列とを含み、
前記画素行の各々は、前記画素行に対して平行に延びている行線を含み、各行線は、Tワイヤに結合され、前記Tワイヤは、前記ドライバチップにも結合され、
各Tワイヤは、前記基板の裏側に沿って、前記行線に対して実質的に垂直な方向に延び、各Tワイヤは、ビアを通して前記基板の表側に移行し、
各Tワイヤのための各ビアは、最も近い近隣ビアを有し、前記ビアと前記最も近い近隣ビアとは、同じ画素列と整列させられていない、電気光学ディスプレイ。
(項目2)
各画素電極は、それに関連付けられた薄膜トランジスタを有する、項目1に記載の電気光学ディスプレイ。
(項目3)
前記行線は、ソース線である、項目2に記載の電気光学ディスプレイ。
(項目4)
各画素列は、それに関連付けられたそれぞれの列線を有する、項目2または3に記載の電気光学ディスプレイ。
(項目5)
前記列線は、走査線である、項目4に記載の電気光学ディスプレイ。
(項目6)
前記ドライバチップは、前記基板に結合されている、項目1-5のいずれか1項に記載の電気光学ディスプレイ。
(項目7)
前記基板は、プリント回路基板、可撓性回路、または微細加工回路を備えている、項目1-6のいずれか1項に記載の電気光学ディスプレイ。
(項目8)
前記ビアは、前記基板上にジグザグパターンで配列されている、項目1-7のいずれか1項に記載の電気光学ディスプレイ。
(項目9)
前記ビアは、前記バックプレーン上に疑似ランダムパターンで配列されている、項目1-8のいずれか1項に記載の電気光学ディスプレイ。
(項目10)
各ビアは、前記バックプレーンにおける開口部の中に配置された伝導性材料を備えている、項目1-9のいずれか1項に記載の電気光学ディスプレイ。
(項目11)
前記電気光学ディスプレイは、電気泳動媒体をさらに含む、項目1-10のいずれか1項に記載の電気光学ディスプレイ。
(項目12)
電気光学ディスプレイを形成する方法であって、前記方法は、
ドライバチップおよびバックプレーンを提供することであって、前記バックプレーンは、複数の画素行と複数の画素列とのアレイにおいて配列された複数の画素電極を有する基板を備え、前記複数の画素行の各々は、それに関連付けられた行線を有する、ことと、
前記複数の画素列のうちの第1の画素列に関連付けられた第1の複数のTワイヤを形成することであって、前記第1の複数のTワイヤの各々は、前記ドライバチップに接続されている、ことと、
2つのビアが任意の画素列の隣接する画素行に関連付けられないように、前記バックプレーン内に第1の複数のビアを形成することと、
前記バックプレーン内に配置された前記第1の複数のビアのうちの1つを使用して、前記第1の複数のTワイヤの各々を第1の複数の行線のうちのそれぞれの1つに接続することと
を含む、方法。
(項目13)
前記複数の画素列のうちの第2の画素列に関連付けられた第2の複数のTワイヤを形成することであって、前記第2の複数のTワイヤの各々は、前記ドライバチップに接続されている、ことと、
2つのビアが任意の画素列の隣接する画素行に関連付けられないように、前記バックプレーン内に第2の複数のビアを形成することと、
前記バックプレーン内に配置された前記第2の複数のビアのうちの1つを使用して、前記第2の複数のTワイヤの各々を第2の複数の行線のうちのそれぞれの1つに接続することと
をさらに含む、項目12に記載の方法。
(項目14)
前記複数の画素電極の各々は、それに関連付けられた薄膜トランジスタを有する、項目12または13に記載の方法。
(項目15)
前記第1の複数の行線および前記第2の複数の行線は、ソース線である、項目14に記載の方法。
(項目16)
前記複数の列線の各々は、走査線である、項目12に記載の方法。
(項目17)
前記ドライバチップは、前記バックプレーンに結合される、項目12-16のいずれか1項に記載の方法。
(項目18)
前記バックプレーンは、プリント回路基板、フレックス回路、または印刷層の基板である、項目12-17のいずれか1項に記載の方法。
(項目19)
前記第1の複数のビアおよび前記第2の複数のビアは、前記バックプレーン上にジグザグパターンで配列される、項目12-18のいずれか1項に記載の方法。
(項目20)
前記第1の複数のビアおよび前記第2の複数のビアは、前記バックプレーン上に疑似ランダムパターンで配列される、項目12-18のいずれか1項に記載の方法。
(項目21)
第1の複数のビアを形成することは、
前記バックプレーンにおいて第1の複数の開口部を形成することと、
前記第1の複数の開口部の各々を伝導性材料で充填することと
をさらに含む、項目12-20のいずれか1項に記載の方法。
al.による、Adv. Mater.,2002,14(11),845も参照されたい。このタイプのナノクロミックフィルムは、例えば、米国特許第6,301,038号、第6,870,657号、および第6,950,220号にも説明される。このタイプの媒体も、典型的に、双安定性である。
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- 2019-02-12 EP EP19754049.5A patent/EP3752883A4/en active Pending
- 2019-02-12 US US16/273,334 patent/US11081066B2/en active Active
- 2019-02-12 JP JP2020543285A patent/JP2021514073A/ja active Pending
- 2019-02-14 TW TW108104907A patent/TWI698690B/zh active
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2021
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EP3752883A4 (en) | 2021-11-10 |
JP2021514073A (ja) | 2021-06-03 |
EP3752883A1 (en) | 2020-12-23 |
TWI698690B (zh) | 2020-07-11 |
WO2019160841A1 (en) | 2019-08-22 |
CN111712759A (zh) | 2020-09-25 |
US11081066B2 (en) | 2021-08-03 |
US20190251911A1 (en) | 2019-08-15 |
TW201940952A (zh) | 2019-10-16 |
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