JP2022013773A - 表示装置 - Google Patents
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- JP2022013773A JP2022013773A JP2021103882A JP2021103882A JP2022013773A JP 2022013773 A JP2022013773 A JP 2022013773A JP 2021103882 A JP2021103882 A JP 2021103882A JP 2021103882 A JP2021103882 A JP 2021103882A JP 2022013773 A JP2022013773 A JP 2022013773A
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- thin film
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/32—Stacked devices having two or more layers, each emitting at different wavelengths
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
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- Chemical & Material Sciences (AREA)
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Abstract
Description
101 基板
102 表示パネル
103 ゲート駆動部
104 データ駆動部
110 基板
111 マルチバッファー層
112 下部バッファー層
113 第1ゲート絶縁膜
114 第1層間絶縁膜
115 第2ゲート絶縁膜
116 上部バッファー層
117 第3ゲート絶縁膜
118 第2層間絶縁膜
119 第1平坦化層
120 第2平坦化層
122 バンク
200 第1薄膜トランジスタ
300 第3薄膜トランジスタ
400 第2薄膜トランジスタ
500 ストレージキャパシタ
600 発光素子
700 封止部
Claims (21)
- 表示領域及び非表示領域を含む基板と、
前記非表示領域に存在する第1薄膜トランジスタと、
前記表示領域に存在する第2薄膜トランジスタ及び第3薄膜トランジスタとを含み、
前記第1薄膜トランジスタは、
第1ポリシリコンを含む第1半導体パターンと、
前記第1半導体パターンと重畳する第1ゲート電極と、
前記第1半導体パターンに連結される第1ソース電極及び第1ドレイン電極とを含み、
前記第2薄膜トランジスタは、
第1酸化物半導体を含む第2半導体パターン及び第3半導体パターンと、
前記第2半導体パターンと重畳する第2ゲート電極と、
前記第3半導体パターンと重畳する第3ゲート電極と、
前記第2半導体パターンと前記第3半導体パターンがコンタクトホールを介して連結される第2ソース電極及び第2ドレイン電極とを含み、
前記第3薄膜トランジスタは、
第1酸化物半導体を含む第4半導体パターンと、
前記第4半導体パターンと重畳する第4ゲート電極と、
前記第4半導体パターンに連結される第3ソース電極及び第3ドレイン電極とを含む、表示装置。 - 前記第2半導体パターンと前記第3半導体パターンは第2ソース電極及び第2ドレイン電極を介して並列で連結された、請求項1に記載の表示装置。
- 前記第2半導体パターンと前記第3半導体パターンは重畳して構成される、請求項1に記載の表示装置。
- 前記第2半導体パターンは第2ソース電極及び第2ドレイン電極が接触する第2ソース及び第2ドレイン領域を含み
前記第3半導体パターンは第2ソース電極及び第2ドレイン電極が接触する第3ソース及び第3ドレイン領域を含む、請求項3に記載の表示装置。 - 前記第2ソース領域、第2ドレイン領域、前記第3ソース領域及び第3ドレイン領域のそれぞれはドーパントによってドーピングされ、導体化領域を含む、請求項4に記載の表示装置。
- チャネル方向への前記第2半導体パターンの導体化領域の長さをL1とし、チャネル方向への前記第3半導体パターンの導体化領域の長さをL2としたとき、L2はL1より大きく設定された、請求項5に記載の表示装置。
- 前記ドーパントは、ホウ素(B)、リン(P)、フッ素(F)及び水素(H)の少なくとも1種を含む、請求項5に記載の表示装置。
- Idsがソース-ドレイン電流であり、Vgsがゲート-ソース電圧であるとき、Ids-Vgsカーブの飽和領域で、前記第2薄膜トランジスタの駆動電流値は前記第3薄膜トランジスタの駆動電流値より高い値を有する、請求項1に記載の表示装置。
- 電圧変化量に対する電流変化量(S-Factor)が電圧変動に対する電流変動の比を示せば、前記第2薄膜トランジスタの電圧変化量に対する電流変化量の値は前記第3薄膜トランジスタの電圧変化量に対する電流変化量の値より高い、請求項1に記載の表示装置。
- 表示領域及び非表示領域を含む基板と、
前記非表示領域にある駆動回路部と、
前記表示領域にある画素部とを含み、
前記画素部は互いに異なる構造に構成されたスイッチングトランジスタ及び駆動トランジスタを含み、
前記駆動トランジスタは、
ソース/ドレイン領域及びチャネル領域を含む第1アクティブと、
前記第1アクティブの上部にある第2アクティブと、
前記前記第2アクティブの上部で、前記第1アクティブのソース/ドレイン領域及び前記第2アクティブのソース/ドレイン領域に連結されたソース/ドレイン電極と、
前記第1アクティブの下部にある下部ゲート電極と、
前記第2アクティブの上部にある上部ゲート電極とを含み、
前記第1アクティブのソース/ドレイン領域は第1コンタクトホールを介して前記ソース/ドレイン電極に連結され、
前記第2アクティブのソース/ドレイン領域は第2コンタクトホールを介して前記ソース/ドレイン電極に連結され、
前記第1コンタクトホールはチャネル方向に前記上部ゲート電極から前記第2コンタクトホールの位置より遠く位置する、表示装置。 - 前記駆動トランジスタは、前記第1アクティブと前記第2アクティブがソース/ドレイン電極を介して並列で連結される、請求項10に記載の表示装置。
- 前記第1アクティブと前記第2アクティブは重畳して構成される、請求項10に記載の表示装置。
- チャネル方向に前記第1コンタクトホールが前記下部ゲート電極から離隔した距離をL4とし、チャネル方向に前記第2コンタクトホールが前記下部ゲート電極から離隔した距離をL3としたとき、L4の長さがL3の長さより長い、請求項10に記載の表示装置。
- 前記第1アクティブのソース/ドレイン領域と前記第2アクティブのソース/ドレイン領域はそれぞれドーパントでドーピングされて導体化した、請求項10に記載の表示装置。
- チャネル方向への前記第1アクティブの導体化した領域の長さをL2とし、チャネル方向への前記第2アクティブの導体化した領域の長さをL1としたとき、L2はL1より大きく設定された、請求項13に記載の表示装置。
- 前記ドーパントは、ホウ素(B)、リン(P)、フッ素(F)及び水素(H)の少なくとも1種を含む、請求項14に記載の表示装置。
- 前記第1アクティブ及び前記第2アクティブは酸化物半導体を含む、請求項10に記載の表示装置。
- Idsがソース-ドレイン電流であり、Vgsがゲート-ソース電圧であるとき、Ids-Vgsカーブの飽和領域で、前記駆動トランジスタの駆動電流値は前記スイッチングトランジスタの駆動電流値より高い値を有する、請求項10に記載の表示装置。
- 電圧変化量に対する電流変化量(S-Factor)が電圧変動に対する電流変動の比を示せば、前記駆動トランジスタの電圧変化量に対する電流変化量の値は前記スイッチングトランジスタの電圧変化量に対する電流変化量の値より高い、請求項10に記載の表示装置。
- 表示領域及び非表示領域を含む基板と、
前記非表示領域に位置する駆動回路部と、
前記表示領域に位置する画素部とを含み、
前記画素部はスイッチングトランジスタ及び駆動トランジスタを含み、
前記駆動トランジスタは、
第1酸化物半導体を含む第2半導体パターン及び第3半導体パターンと、
前記第2半導体パターンと重畳する第2ゲート電極と、
前記第3半導体パターンと重畳する第3ゲート電極と、
コンタクトホールを介して前記第2半導体パターン及び前記第3半導体パターンと連結される第2ソース電極及び第2ドレイン電極とを含み、
前記スイッチングトランジスタは、
第2酸化物半導体を含む第4半導体パターンと、
前記第4半導体パターンと重畳する第4ゲート電極と、
前記第4半導体パターンと連結される第3ソース電極及び第3ドレイン電極とを含む、表示装置。 - 前記第1酸化物半導体は前記第2酸化物半導体と同一である、請求項20に記載の表示装置。
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