JP2021150460A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
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- 238000007772 electroless plating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- Wire Bonding (AREA)
Abstract
Description
図1に示すように、パワー半導体モジュール50は、パワー半導体チップ1と、絶縁基板2と、接合材3a、3b、3cと、電極パターン4と、金属基板5と、リードフレーム配線6と、端子ケース7と、封止樹脂8と、金属端子9と、金属ワイヤ10と、を備える。
次に、実施の形態にかかる半導体装置の製造方法について、説明する。図3〜図5は、実施の形態にかかるパワー半導体モジュールの電極部の製造途中の状態を示す断面図である。まず、従来技術による半導体装置の製造方法と同様に、半導体基板上に半導体素子20を形成する。例えば、半導体装置がIGBTである場合、半導体基板上にエピタキシャル成長によりドリフト層、ベース層を形成し、イオン注入で不純物イオンを注入することによりおもて面にエミッタ領域を形成し、裏面にコレクタ領域を形成する。次に、おもて面に熱酸化等でゲート絶縁膜を選択的に形成する。
2 積層基板
3a、3b、3c 接合材
4 電極パターン
5 金属基板
6 リードフレーム配線
7 端子ケース
8 封止樹脂
9 金属端子
10 金属ワイヤ
12 積層基板
20、120 半導体基板上の半導体素子
21、121 AlSi電極
22、122 第1保護膜
23、123 第2保護膜
24、124 上部電極膜
25、125 はんだ
26 凹部
27 治具
50 パワー半導体モジュール
Claims (10)
- 半導体基板上に半導体素子を形成する第1工程と、
前記半導体素子のおもて面に、前記半導体素子に電気的に接続された電極層を形成する第2工程と、
前記電極層上に、選択的に第1保護膜を形成する第3工程と、
前記第1保護膜上の、前記第1保護膜と上部電極膜とが接する部分を覆う第2保護膜が形成される部分に凹部を形成する第4工程と、
前記電極層上の前記第1保護膜以外の部分に、前記第1保護膜と接するように上部電極膜を形成する第5工程と、
前記上部電極膜と前記第1保護膜とが接する部分に前記第2保護膜を形成する第6工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第4工程では、凸部を有する治具を前記第1保護膜に押し当てることにより前記凹部を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第4工程では、前記第1保護膜の粘度が300Pa・s以上1000Pa・s以下であるときに、前記凹部を形成することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第4工程では、前記凹部を複数形成し、前記凹部間の距離を10μm以上30μm以下に前記凹部を形成することを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。
- 前記第4工程では、前記凹部の直径を10μm以上30μm以下に前記凹部を形成することを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。
- 前記第4工程では、前記凹部の深さを前記第1保護膜の厚さの30%以上80%以下に前記凹部を形成することを特徴とする請求項1〜5のいずれか一つに記載の半導体装置の製造方法。
- 前記第4工程では、前記第1保護膜のおもて面を底辺とした台形形状に前記凹部を形成することを特徴とする請求項1〜6のいずれか一つに記載の半導体装置の製造方法。
- 前記第4工程では、前記凹部を前記第1保護膜と前記上部電極膜とが接する部分から10μm以上30μm以下離して、前記凹部を形成することを特徴とする請求項1〜7のいずれか一つに記載の半導体装置の製造方法。
- 前記第1保護膜および前記第2保護膜は、ポリイミド膜であることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置の製造方法。
- 前記上部電極膜は、ニッケルリン(NiP)であることを特徴とする請求項1〜9のいずれか一つに記載の半導体装置の製造方法。
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