JP2021125599A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving connection reliability of wiring formed on a semiconductor lamination structure including a layer having at least two different kinds of compositions.SOLUTION: A semiconductor light-emitting device 1 includes a base layer 16, a mesa part 13 including a layer having at least two different kinds of compositions laminated on the base layer 16, and metal wiring 27 led out to a lead-out part 14 from an apex of the mesa part 13 through a side part of the mesa part 13. The meta part 13 includes a first side surface 17B, a second side surface 18B crossing the first side surface 17B, and a wiring arrangement part 19 in which the metal wiring 27 is arranged. The metal wiring 27 strides over an intersection 29 between the first side surface 17B and the second side surface 18B of the wiring arrangement part 19, and covers the first side surface 17B and the second side surface 18B.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having a semiconductor laminated structure including layers having at least two different compositions.

Patent Document 1 discloses a self-scanning light emitting device array. The self-scanning light emitting element array is arranged in a width direction intersecting the longitudinal direction of the light emitting element array of the light emitting unit and the light emitting portions linearly arranged along the scanning direction which is the longitudinal direction of the light emitting element array. Including the shift part.
The light emitting unit includes a light emitting element for writing, which is composed of a plurality of light emitting thyristors arranged linearly along the scanning direction of the light emitting element array. These writing light emitting elements are composed of a cathode common type light emitting thyristor. The cathode electrode is grounded via a common electrode formed on the back surface of the p-type wafer substrate. Further, a write signal is applied to the anode electrode of the light emitting element for writing via a write line and a resistor. Further, the gate electrode of the light emitting element for writing is connected to the gate electrode of the corresponding switching element of the shift portion.

On the other hand, as described above, the shift unit includes a plurality of switching elements provided corresponding to the light emitting element for writing. These switching elements are composed of a cathode common type light emitting thyristor. The cathode electrode is grounded via a common electrode formed on the back surface of the p-type wafer substrate. Further, among the switching elements, a first transfer clock pulse is applied to the anode electrodes of the even-numbered switching elements via the current limiting resistor and the first transfer line. A second transfer clock pulse is applied to the anode electrode of the odd-numbered switching element via the current limiting resistor and the second transfer line. Further, a power supply voltage is applied to the gate electrode of the switching element via a resistor and a power supply line. Further, a diode is interposed between the gate electrodes of adjacent switching elements so that the direction facing the switching element having a small number is the forward direction.

Japanese Unexamined Patent Publication No. 2011-71319

The semiconductor wafer of the self-scanning light emitting device array of Patent Document 1 includes, for example, a p-type layer as a first layer and an n-type layer as a second layer on a p-type wafer substrate made of a GaAs substrate or the like. A plurality of semiconductor layers including a p-type layer as a third layer and an n-type layer as a fourth layer are sequentially laminated. Each of the light emitting portions is formed by selectively removing the laminated structure of the semiconductor layer to form a mesa shape.

In this type of mesa shape, the surface shape of the side surface exposed by wet etching may differ from side to side. For example, as an example, one side surface has a curved shape from the bottom to the top of the side surface, while another side surface tapers from the bottom to the top of the other side surface. It has an inclined shape.
In such a case, if wiring (for example, the writing line of Patent Document 1, the first transfer line, the second transfer line, the power supply line, etc.) is formed on the curved side surface, the step coverage of the wiring may be poor and the wiring may be broken. There is.

An object of the present invention is to provide a semiconductor device capable of improving the connection reliability of wiring formed on a semiconductor laminated structure including layers having at least two or more different compositions.

A semiconductor device according to one aspect of the present invention includes a semiconductor laminated structure including a base layer, layers selectively laminated in a first region on the base layer having at least two different compositions, and the semiconductor. The semiconductor laminated structure includes metal wiring drawn from the top of the laminated structure through a side portion of the semiconductor laminated structure to a second region of the base layer different from the first region, and the semiconductor laminated structure is the semiconductor laminated structure. The metal wiring includes a wiring arrangement portion selectively formed on a part of the side portion, having a first side surface and a second side surface intersecting the first side surface, and the metal wiring is arranged. It straddles the intersection between the first side surface and the second side surface of the wiring arrangement portion, and covers the first side surface and the second side surface.

According to one aspect of the present invention, the metal wiring straddles the intersection between the first side surface and the second side surface of the wiring arrangement portion of the semiconductor laminated structure, and covers the first side surface and the second side surface. ing. Therefore, even if one of the wiring arrangement portion and the first side surface and the second side surface has a shape that easily induces a disconnection of the metal wiring (a shape that easily induces a decrease in step coverage, etc.), at least the first side surface and the second side surface. It is possible to prevent disconnection on the other side of the side surface and secure a connected state. As a result, the connection reliability of the metal wiring can be improved.

FIG. 1 is a schematic perspective view of a semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor light emitting device according to the embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line III-III of FIG. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. FIG. 5A is a diagram showing a part of a manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention. FIG. 5B is a diagram showing a part of a manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention. FIG. 6A is a diagram showing the next step of FIG. 5A. FIG. 6B is a diagram showing the next step of FIG. 5B. FIG. 7A is a diagram showing the next step of FIG. 6A. FIG. 7B is a diagram showing the next step of FIG. 6B. FIG. 8A is a diagram showing the next step of FIG. 7A. FIG. 8B is a diagram showing the next step of FIG. 7B. FIG. 9A is a diagram showing the next step of FIG. 8A. FIG. 9B is a diagram showing the next step of FIG. 8B. FIG. 10 is a schematic perspective view of a semiconductor light emitting device according to another embodiment of the present invention. FIG. 11 is a schematic plan view of the semiconductor light emitting device according to another embodiment of the present invention. FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. FIG. 14A is a diagram showing a part of a manufacturing process of the semiconductor light emitting device according to another embodiment of the present invention. FIG. 14B is a diagram showing a part of a manufacturing process of the semiconductor light emitting device according to another embodiment of the present invention. FIG. 15A is a diagram showing the next step of FIG. 14A. FIG. 15B is a diagram showing the next step of FIG. 14B. FIG. 16A is a diagram showing the next step of FIG. 15A. FIG. 16B is a diagram showing the next step of FIG. 15B. FIG. 17A is a diagram showing the next step of FIG. 16A. FIG. 17B is a diagram showing the next step of FIG. 16B. FIG. 18A is a diagram showing the next step of FIG. 17A. FIG. 18B is a diagram showing the next step of FIG. 17B. FIG. 19A is a diagram showing the next step of FIG. 18A. FIG. 19B is a diagram showing the next step of FIG. 18B. FIG. 20 is a schematic perspective view of a semiconductor light emitting device according to another embodiment of the present invention. FIG. 21 is a schematic perspective view of a semiconductor light emitting device according to another embodiment of the present invention.

<Embodiment of the present invention>
First, embodiments of the present invention will be listed and described.
A semiconductor device according to an embodiment of the present invention includes a semiconductor laminated structure including a base layer, layers selectively laminated in a first region on the base layer having at least two different compositions, and the semiconductor. The semiconductor laminated structure includes metal wiring drawn from the top of the laminated structure through a side portion of the semiconductor laminated structure to a second region of the base layer different from the first region, and the semiconductor laminated structure is the semiconductor laminated structure. The metal wiring includes a wiring arrangement portion selectively formed on a part of the side portion, having a first side surface and a second side surface intersecting the first side surface, and the metal wiring is arranged. It straddles the intersection between the first side surface and the second side surface of the wiring arrangement portion, and covers the first side surface and the second side surface.

According to this configuration, the metal wiring straddles the intersection between the first side surface and the second side surface of the wiring arrangement portion of the semiconductor laminated structure, and covers the first side surface and the second side surface. Therefore, even if one of the wiring arrangement portion and the first side surface and the second side surface has a shape that easily induces a disconnection of the metal wiring (a shape that easily induces a decrease in step coverage, etc.), at least the first side surface and the second side surface. It is possible to prevent disconnection on the other side of the side surface and secure a connected state. As a result, the connection reliability of the metal wiring can be improved.

In the semiconductor device according to the embodiment of the present invention, the first side surface includes a concave surface selectively recessed from the lower part to the upper part of the first side surface, and the second side surface is the second side surface. It may be inclined in a tapered shape from the lower part of the side surface to the upper part.
In the semiconductor device according to the embodiment of the present invention, the concave surface of the first side surface may include a warped portion that warps from the lower part to the upper part of the first side surface.

In the semiconductor device according to the embodiment of the present invention, the wiring arrangement portion includes a convex portion formed by selectively projecting the side portion of the semiconductor laminated structure in a direction along the surface of the base layer. You may be.
In the semiconductor device according to the embodiment of the present invention, the wiring arrangement portion includes a recess formed by selectively recessing the side portion of the semiconductor laminated structure in a direction along the surface of the base layer. May be good.

In the semiconductor device according to the embodiment of the present invention, a plurality of the semiconductor laminated structures may be formed on the common base layer.
In the semiconductor device according to the embodiment of the present invention, the plurality of semiconductor laminated structures may be arranged in a matrix along each of a first direction and a second direction orthogonal to the first direction.

In the semiconductor device according to the embodiment of the present invention, the plurality of semiconductor laminated structures may be arranged in a line along the first direction.
In the semiconductor device according to the embodiment of the present invention, the metal wiring may be formed across the plurality of semiconductor laminated structures.
The semiconductor device according to the embodiment of the present invention includes electrodes formed on the tops of the semiconductor laminated structures, and the metal wiring may connect the electrodes of the plurality of semiconductor laminated structures to each other.

In the semiconductor device according to the embodiment of the present invention, the electrodes may be formed in an island shape on the top of the semiconductor laminated structure.
In the semiconductor device according to the embodiment of the present invention, the electrodes may be formed in an annular shape along the peripheral edge of the top of the semiconductor laminated structure.
The semiconductor device according to the embodiment of the present invention may include a pad portion formed at an end portion of the metal wiring and common to the plurality of semiconductor laminated structures.

In the semiconductor device according to the embodiment of the present invention, the semiconductor laminated structure may be formed in a mesa shape in which the periphery is surrounded by the second region of the base layer.
The semiconductor device according to the embodiment of the present invention may include a semiconductor light emitting device having a function of emitting light from the semiconductor laminated structure.
In the semiconductor device according to the embodiment of the present invention, the semiconductor laminated structure may include a light emitting layer and a p-type layer and an n-type layer sandwiching the light emitting layer.

In the semiconductor device according to the embodiment of the present invention, the semiconductor laminated structure may include a group III-V semiconductor laminated structure.
In the semiconductor device according to the embodiment of the present invention, the metal wiring may include a metal wiring containing at least one of Au and Al.
<Detailed Description of Embodiments of the Present Invention>
Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view of a semiconductor light emitting device 1 according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor light emitting device 1 according to the embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line III-III of FIG. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. Note that FIGS. 1 and 2 show only a part of the configuration of the semiconductor light emitting device 1 for the sake of clarity.
The semiconductor light emitting device 1 includes a substrate 2, a semiconductor laminated structure 3 formed on the substrate 2, and an n-side electrode as an example of a back electrode that contacts the back surface of the substrate 2 (the surface opposite to the semiconductor laminated structure 3). 4 and a p-side electrode 5 as an example of a surface electrode in contact with the surface of the semiconductor laminated structure 3 are included.

In this embodiment, the substrate 2 is composed of a GaAs (gallium arsenide) substrate. Of course, the substrate 2 may be composed of other semiconductor substrates such as silicon and GaP (gallium phosphide). In this embodiment, the substrate 2 is formed in a substantially square shape in a plan view as shown in FIGS. 1 and 2, but the plan shape of the substrate 2 is not particularly limited, and is, for example, a rectangular shape in a plan view. May be good. Further, the thickness of the substrate 2 may be, for example, 50 μm to 500 μm. Further, the substrate 2 contains silicon (Si) as an n-type impurity at an appropriate concentration.

In this embodiment, the semiconductor laminated structure 3 is composed of a group III-V semiconductor laminated structure, and includes a light emitting layer 6, an n-type semiconductor layer 7, and a p-type semiconductor layer 8. The n-type semiconductor layer 7 is arranged on the substrate 2 side with respect to the light emitting layer 6, and the p-type semiconductor layer 8 is arranged on the p-side electrode 5 side with respect to the light emitting layer 6. In this way, the light emitting layer 6 is sandwiched between the p-type semiconductor layer 8 and the n-type semiconductor layer 7, and a double heterojunction is formed. Electrons are injected into the light emitting layer 6 from the n-type semiconductor layer 7, and holes are injected from the p-type semiconductor layer 8. Light is generated by recombination of these in the light emitting layer 6. Further, the total thickness including the thickness of the substrate 2 and the thickness of the semiconductor laminated structure 3 may be, for example, 60 μm to 260 μm.

The composition of each layer constituting the light emitting layer 6, the n-type semiconductor layer 7 and the p-type semiconductor layer 8 is appropriately selected according to the emission wavelength range of the light emitting layer 6, and for example, when the emission wavelength is in the infrared wavelength region of 800 nm or more. AlGaAs-based semiconductors are mainly selected, and when the emission wavelength is in the visible light wavelength range of about 380 nm to 780 nm, AlInGaP-based semiconductors are mainly selected. Of these, as an example, the layer configurations of the light emitting layer 6, the n-type semiconductor layer 7 and the p-type semiconductor layer 8 when the emission wavelength is in the infrared wavelength region of 800 nm or more will be described with reference to FIGS. 3 and 4. do.

The n-type semiconductor layer 7 may include an n-type clad layer 9. Although not shown, the n-type semiconductor layer 7 may include an n-type window layer or an n-type distributed Bragg reflector (DBR) layer between the n-type clad layer 9 and the substrate 2, if necessary. good.
The n-type clad layer 9 may be composed of an Al _x Ga _1-x As (0 <x <1) -based semiconductor. The Al composition in the formula is appropriately set according to the range of the emission wavelength of the light emitting layer 6. Further, the n-type clad layer 9 may contain silicon (Si) as an n-type impurity at an appropriate concentration.

Further, the n-type clad layer 9 may have a thickness of 1000 Å to 40,000 Å. Further, the n-type clad layer 9 may be formed of a single layer, or may be formed of, for example, a plurality of layers having different Al compositions.
On the other hand, the p-type semiconductor layer 8 may be configured by laminating a p-type clad layer 10, a p-type window layer 11 and a p-type contact layer 12 in this order on the light emitting layer 6.

The p-type clad layer 10 and the p-type window layer 11 are composed of Al _x Ga _1-x As (0 <x <1) -based semiconductors, and the p-type contact layer 12 is Al _x Ga _1-x As (0 ≦). It may be composed of an x <1) -based semiconductor. The Al composition in the formula is appropriately set according to the range of the emission wavelength of the light emitting layer 6. The p-type clad layer 10, the p-type window layer 11, and the p-type contact layer 12 can all be represented by the composition formula Al _x Ga _1-x As, but strictly speaking, they have different compositions from each other. Further, the p-type clad layer 10, the p-type window layer 11 and the p-type contact layer 12 may contain carbon (C) and zinc (Zn) as p-type impurities at appropriate concentrations. Further, as another composition of the p-type contact layer 12, GaP may be used.

The thickness of each of the p-type clad layer 10, the p-type window layer 11, and the p-type contact layer 12 is, for example, that the p-type clad layer 10 has a thickness of 1000 Å to 20000 Å, and the p-type window layer 11 has a thickness of 1000 Å to 20000 Å. It may have a thickness of 0 Å to 10000 Å and the p-type contact layer 12 may have a thickness of 100 Å to 20000 Å. That is, the p-type window layer 11 may be omitted (thickness 0 Å).

The p-type clad layer 10, the p-type window layer 11, and the p-type contact layer 12 may be formed of a single layer, or may be formed of, for example, a plurality of layers having different Al compositions. good.
The light emitting layer 6 has an MQW (multiple-quantum well) structure (multiple-quantum well structure), and light is generated by recombination of electrons and holes, and the generated light is amplified. It is a layer.

The light emitting layer 6 has, for example, a multiple-quantum well (MQW) structure in which a quantum well layer made of an AlGaAs layer and a barrier layer made of an AlGaAs layer are alternately and repeatedly laminated for a plurality of cycles. You may. For example, the quantum well layer (AlGaAs) and the barrier layer (AlGaAs) are alternately and repeatedly laminated for 2 to 50 cycles, whereby the light emitting layer 6 having a multiple quantum well structure may be formed. In this embodiment, both the quantum well layer and the barrier layer are made of an AlGaAs layer, but the Al composition of the quantum well layer is lower than the Al composition of the barrier layer. Further, the compositions of the quantum well layer and the barrier layer may be appropriately changed according to the emission wavelength of the light emitting layer 6. For example, when the emission wavelength is an infrared wavelength, the quantum well layer may be an InGaAs layer.

The semiconductor laminated structure 3 forms the mesa portion 13 by removing a part of the semiconductor laminated structure 3. With reference to FIGS. 3 and 4, the p-type semiconductor layer 8, the light emitting layer 6, and the n-type semiconductor layer 7 are selectively etched and removed from the surface of the semiconductor laminated structure 3 to form the mesa portion 13. More specifically, the semiconductor laminated structure 3 is etched from the surface of the p-type semiconductor layer 8 to the middle portion of the n-type semiconductor layer 7 (in this embodiment, the n-type clad layer 9). As a result, around the mesa portion 13, the second region of the present invention composed of the n-type semiconductor layer 7 (in this embodiment, the n-type clad layer 9) and the substrate 2 drawn out laterally from the mesa portion 13 As an example, a drawer portion 14 is formed. Therefore, the mesa portion 13 is surrounded by the drawer portion 14.

In the mesa portion 13, the p-type contact layer 12 is formed smaller than the p-type window layer 11, so that the top of the mesa portion 13 has a plane size of the p-type contact layer 12 and the p-type window layer 11. The resulting stepped portion 20 is formed. As a result, the p-type contact layer 12 is surrounded by the stepped portion 20 having an annular shape in a plan view. As an example, the layer surrounded by the step portion 20 may include a p-type window layer 11 in addition to the p-type contact layer 12.

Here, the top of the mesa portion 13 is not limited to the region forming the uppermost surface of the mesa portion 13, but is the top as long as it has a certain region in which the metal wiring 27 described later can be formed (connected). You may call it. For example, the mesa portion 13 is formed in a two-stage structure in which a step is formed in the central portion in the thickness direction, and a metal wiring 27 is formed (connected to the mesa portion 13) in the step portion in the central portion in the thickness direction. If so, the stepped portion may be referred to as the "top of the mesa portion 13".

Further, in this embodiment, a plurality of mesa portions 13 are regularly arranged on a common substrate 2. The plurality of mesa portions 13 may be arranged in a matrix along each of the first direction X and the second direction Y orthogonal to the first direction X, for example. In other words, the drawer portion 14 is formed in a grid pattern on the common substrate 2, and the mesa portion 13 is selectively formed in each window portion 15 of the grid as an example of the first region of the present invention. ing.

When the substrate 2 and the semiconductor laminated structure 3 are divided into a mesa portion 13 and a portion other than the mesa portion 13 (a portion remaining after etching), the substrate 2 other than the mesa portion 13 and a part of the n-type semiconductor layer 7 are put together. It may be referred to as a base layer 16.
The mesa portion 13 has side surfaces 17A and 18A that intersect the laminated interface of the n-type semiconductor layer 7, the light emitting layer 6, and the p-type semiconductor layer 8. The side surfaces 17A and 18A are surfaces that appear when the semiconductor laminated structure 3 is etched to form the mesa portion 13.

In this embodiment, each mesa portion 13 is formed in a rectangular shape in a plan view, and intersects (orthogonally) a pair of first side surfaces 17A facing each other (for example, parallel to each other) and a pair of first side surfaces 17A. It includes a pair of second side surfaces 18A that face each other (eg, parallel to each other). For example, the first side surface 17A may be a side surface parallel to the first direction X, and the second side surface 18A may be a side surface parallel to the second direction Y.

A wiring arrangement portion 19 on which the metal wiring 27 described later is arranged is formed on a part of the side surfaces 17A and 18A of each mesa portion 13. In this embodiment, the wiring arrangement portion 19 is a convex portion formed by selectively projecting a part of the side surfaces 17A and 18A in the direction along the surface of the substrate 2. More specifically, a part of the second side surface 18A of the mesa portion 13 projects as the wiring arrangement portion 19.

The wiring arrangement portion 19 is formed over the entire thickness direction from the top portion of the mesa portion 13 (more specifically, the portion below the step portion 20) to the surface of the drawer portion 14. That is, the wiring arrangement portion 19 is not formed with a layer surrounded by the step portion 20 (in this embodiment, the p-type contact layer 12).
The wiring arrangement portion 19 is formed in a rectangular shape in a plan view, and includes a first side surface 17B and a second side surface 18B that intersects (orthogonally) the first side surface 17B. The first side surface 17B may be a surface parallel to the first side surface 17A, and the second side surface 18B may be a surface parallel to the second side surface 18A. More specifically, the wiring arrangement portion 19 extends outward at right angles to the first side surface 17A of the mesa portion 13, and faces the pair of second side surfaces 18B and the ends of the pair of second side surfaces 18B. And has a first side surface 17B parallel to the first side surface 17A of the mesa portion 13.

That is, in this embodiment, the mesa portion 13 is for arranging the outer side surfaces (first side surface 17A and second side surface 18A) forming the outer shape (contour) of the mesa portion 13 and the metal wiring 27 on the outer outer side surface. It has an auxiliary side surface (first side surface 17B and second side surface 18B) formed. The auxiliary side surfaces (first side surface 17B and second side surface 18B) are continuous so as to intersect the outer side surface of the mesa portion 13, and are smaller than the outer side surface.

Further, in this embodiment, when the first side surfaces 17A and 17B and the second side surfaces 18A and 18B of the mesa portion 13 are compared with reference to FIGS. 3 and 4, the cross-sectional shapes thereof are different from each other.
With reference to FIG. 3, the first side surfaces 17A and 17B of the mesa portion 13 have a concave surface that is selectively recessed from the lower portion (intersection portion 21 with the drawer portion 14) of the first side surface 17A and 17B toward the upper portion. It has become. More specifically, this concave surface includes a curved portion 22 that is curved toward the upper portion from the lower portion (intersection portion 21 with the drawer portion 14) of the first side surfaces 17A and 17B. As a result, a recess 24 recessed inward from the outer edge 23 of the top of the mesa portion 13 is formed in the lower portion of the first side surfaces 17A and 17B.

On the other hand, with reference to FIG. 4, the second side surfaces 18A and 18B of the mesa portion 13 are inclined in a tapered shape from the lower portion (intersection portion 25 with the drawer portion 14) of the second side surfaces 18A and 18B toward the upper portion. There is. That is, the second side surfaces 18A and 18B are inclined so that an obtuse angle is formed between the surface of the drawer portion 14 and the second side surfaces 18A and 18B. As a result, the lower portions of the second side surfaces 18A and 18B are located outside the outer edge 23 of the top of the mesa portion 13.

An insulating layer 26 is formed on the semiconductor laminated structure 3. The insulating layer 26 covers the entire surface of the semiconductor laminated structure 3. Further, the insulating layer 26 may be made of an insulating material such as silicon _{oxide (SiO 2) or silicon nitride (SiN).}
In this embodiment, the n-side electrode 4 as the back surface electrode is composed of Au or an alloy containing Au. The n-side electrode 4 may have, for example, a laminated structure represented by an AuGeNi layer / Au layer (on the substrate 2 side). The n-side electrode 4 covers the entire back surface of the substrate 2 and serves as a common electrode for a plurality of mesas portions 13.

On the other hand, the p-side electrode 5 as the surface electrode is made of Au or an alloy containing Au in this embodiment. The p-side electrode 5 may have, for example, a laminated structure represented by a Ti layer / Au layer or a Cr layer / Au layer (semiconductor laminated structure 3 side). With reference to FIGS. 1 and 2, the p-side electrode 5 is formed on the top of each mesa portion 13. In this embodiment, the p-side electrode 5 is formed in an island shape (circular shape) on the top of each mesa portion 13 and is connected to the p-type contact layer 12.

A metal wiring 27 is further formed on the semiconductor laminated structure 3. The metal wiring 27 is formed on the insulating layer 26. In this embodiment, the metal wiring 27 is composed of Au or an alloy containing Au. The metal wiring 27 may have, for example, a laminated structure represented by a Ti layer / Au layer or a Cr layer / Au layer (on the semiconductor laminated structure 3 side). That is, the metal wiring 27 may be made of the same material as the p-side electrode 5.

The metal wiring 27 connects the p-side electrodes 5 of the plurality of mesa portions 13 to each other. In this embodiment, the p-side electrodes 5 are arranged at the tops of each of the plurality of mesa portions 13 arranged in a planar visual matrix. The metal wiring 27 connecting the p-side electrodes 5 to each other is formed in a planar grid shape. At the end of the metal wiring 27, a pad portion 28 common to the plurality of mesa portions 13 is formed in the drawer portion 14. The pad portion 28 is electrically connected to the plurality of p-side electrodes 5 via the metal wiring 27.

The metal wiring 27 is pulled out from the top of each mesa portion 13 to the drawer portion 14 via the wiring arrangement portion 19 and the intersections 21 and 25, and reaches the adjacent mesa portion 13. The metal wiring 27 straddles the intersection 29 between the first side surface 17B and the second side surface 18B in the wiring arrangement portion 19, and covers the first side surface 17B and the second side surface 18B. In this embodiment, one of the pair of intersections 29, the intersection 29, is covered with the metal wiring 27, and the other intersection 29 is not covered with the metal wiring 27. Therefore, the first side surface 17B and the second side surface 18B of the wiring arrangement portion 19 each have a portion that is exposed without being covered by the metal wiring 27.

5A and 5B to 9A and 9B are diagrams showing a part of a manufacturing process of the semiconductor light emitting device 1 according to the embodiment of the present invention. The figure of "number + A" as shown in FIG. 5A corresponds to the cross section of FIG. 3 described above, and the figure of "number + B" as shown in FIG. 5B corresponds to the cross section of FIG. 4 described above. ..
In order to manufacture the semiconductor light emitting device 1, for example, as shown in FIGS. 5A and 5B, a semiconductor laminated structure 3 is formed by epitaxial growth on a substrate 2 (wafer) made of GaAs or the like. As the growth method of the semiconductor laminated structure 3, known growth methods such as a molecular beam epitaxial growth method and an organic metal vapor phase growth method can be applied. At this time, if necessary, a dopant (for example, the above-mentioned n-type impurity or p-type impurity) is injected into each layer.

Next, as shown in FIGS. 6A and 6B, the semiconductor laminated structure 3 is selectively removed to form the mesa portion 13 and the drawer portion 14. The mesa portion 13 and the pull-out portion 14 may be formed by, for example, wet etching. More specifically, first, the p-type contact layer 12 is etched to form the stepped portion 20, and then the remaining portion of the semiconductor laminated structure 3 is etched to form the mesa portion 13. At this time, since the semiconductor laminated structure 3 is composed of a plurality of layers having different compositions as described above, the cross-sectional shapes of the first side surfaces 17A and 17B of the mesa portion 13 and the second side surfaces 18A and 18B are formed. Appears in a state in which the cross-sectional shapes of are different from each other. That is, as described above, the first side surfaces 17A and 17B include the warped portion 22 that is selectively warped, while the second side surfaces 18A and 18B are inclined in a tapered shape from the lower portion to the upper portion.

Next, as shown in FIGS. 7A and 7B, the insulating layer 26 is formed so as to cover the semiconductor laminated structure 3. The insulating layer 26 may be formed by, for example, a CVD method. After that, the insulating layer 26 is selectively removed to expose the p-type contact layer 12 from the insulating layer 26.
Next, as shown in FIGS. 8A and 8B, the p-side electrode 5 and the metal wiring 27 are formed. The p-side electrode 5 and the metal wiring 27 may be formed by, for example, a lift-off method. More specifically, first, a resist (not shown) having an opening having the same pattern as the pattern of the p-side electrode 5 and the metal wiring 27 is formed on the semiconductor laminated structure 3. Next, an electrode material film (not shown) is laminated on the semiconductor laminated structure 3 by, for example, a thin-film deposition method. Next, the electrode material film on the resist is removed together with the resist. As a result, the p-side electrode 5 and the metal wiring 27 made of the electrode material film remaining on the semiconductor laminated structure 3 are formed.

In addition to the lift-off method, the p-side electrode 5 and the metal wiring 27 may be formed by, for example, separately patterning. With this method, the p-side electrode 5 and the metal wiring 27 can be formed of different thicknesses and different types of metals. For example, the p-side electrode 5 required to reduce the contact resistance and the metal wiring 27 required to prevent disconnection may be formed of different thicknesses and different types of metals. It is effective in such a case.

Next, as shown in FIGS. 9A and 9B, the n-side electrode 4 is formed on the back surface of the substrate 2 by, for example, a thin-film deposition method. After that, although not shown, the above-mentioned semiconductor light emitting device 1 is obtained by dividing the substrate 2 (wafer) into chip sizes.
As described above, according to the semiconductor light emitting device 1, the metal wiring 27 straddles the intersection 29 between the first side surface 17B and the second side surface 18B in the wiring arrangement portion 19, and the first side surface 17B and the second side surface 18B. Covering. Therefore, like the mesa portion 13, the curved portion 22 is formed on the first side surfaces 17A and 17B, and the shape (step coverage) that easily induces the disconnection of the metal wiring 27 as compared with the tapered second side surfaces 18A and 18B. It is possible to prevent disconnection at least on the second side surface 18B even if the shape is such that it is easy to induce a decrease in the shape. As a result, the connection state of the metal wiring 27 can be ensured, so that the connection reliability of the metal wiring 27 can be improved.

Moreover, as in this embodiment, by adopting the structure of the wiring arrangement portion 19 in the semiconductor light emitting device 1 provided with the metal wiring 27 for connecting the plurality of element portions (mesa portions 13), the reliability of the plurality of element portions is achieved. Gender can be improved collectively.
FIG. 10 is a schematic perspective view of the semiconductor light emitting device 31 according to another embodiment of the present invention. FIG. 11 is a schematic plan view of the semiconductor light emitting device 31 according to another embodiment of the present invention. FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. Note that FIGS. 10 and 11 show only a part of the configuration of the semiconductor light emitting device 31 for the sake of clarity. Further, in FIGS. 10 to 13, the same reference numerals are given to the configurations corresponding to the respective parts shown in FIGS. 1 to 4 described above, and the description thereof will be omitted.

In the semiconductor light emitting device 31, a transparent electrode layer 32 that covers the top of the mesa portion 13 is formed. The transparent electrode layer 32 is formed so as to fill the stepped portion 20, and is in contact with the p-type window layer 11 and the p-type contact layer 12. Further, the transparent electrode layer 32 has an end surface 33 that coincides with the outer edge 23 of the top of the mesa portion 13.
Further, the transparent electrode layer 32 may be composed of TCO (Transparent Conducting Oxide) such as indium tin oxide (ITO: Indium Tin Oxide), In ₂ O ₃ , SnO _{2, ZnO, and In ZO.} Further, the transparent electrode layer 32 may have a thickness of, for example, 50 nm to 400 nm.

A p-side electrode 34 is formed on the transparent electrode layer 32. In this embodiment, the p-side electrode 34 is made of Au or an alloy containing Au. The p-side electrode 34 may have, for example, a laminated structure represented by a Ti layer / Au layer or a Cr layer / Au layer (semiconductor laminated structure 3 side). The p-side electrode 34 is formed in an annular shape on the transparent electrode layer 32 along the end surface 33 of the transparent electrode layer 32 (the outer edge 23 of the top of the mesa portion 13).

Further, the surface of the transparent electrode layer 32 surrounded by the annular p-side electrode 34 is covered with the insulating layer 26. The transparent electrode layer 32 is also formed on the wiring arrangement portion 19.
The metal wiring 27 extends from the outer peripheral portion of the annular p-side electrode 34 along the side surfaces 17A, 17B, 18A, 18B of the mesa portion 13 and is drawn out to the drawer portion 14.
Further, a Distributed Bragg Reflector (DBR) layer 35 may be formed between the substrate 2 and the n-type semiconductor layer 7 (in this embodiment, the n-type clad layer 9). The DBR layer 35 may have, for example, a configuration in which a plurality of AlGaAs / AlGaAs are laminated. In this case, AlGaAs and AlGaAs laminated as a pair have different Al compositions.

14A and 14B to 19A and 19B are diagrams showing a part of a manufacturing process of the semiconductor light emitting device 31 according to another embodiment of the present invention. The figure of "number + A" as shown in FIG. 14A corresponds to the cross section of FIG. 12 described above, and the figure of "number + B" as shown in FIG. 14B corresponds to the cross section of FIG. 13 described above. ..
In order to manufacture the semiconductor light emitting device 31, for example, as shown in FIGS. 14A and 14B, a semiconductor laminated structure 3 is formed by epitaxial growth on a substrate 2 (wafer) made of GaAs or the like. As the growth method of the semiconductor laminated structure 3, known growth methods such as a molecular beam epitaxial growth method and an organic metal vapor phase growth method can be applied. At this time, if necessary, a dopant (for example, the above-mentioned n-type impurity or p-type impurity) is injected into each layer.

Next, as shown in FIGS. 15A and 15B, the semiconductor laminated structure 3 is selectively removed to form the mesa portion 13 and the lead-out portion 14. The mesa portion 13 and the pull-out portion 14 may be formed by, for example, wet etching. More specifically, first, the p-type contact layer 12 is etched to form the stepped portion 20, and then the remaining portion of the semiconductor laminated structure 3 is etched to form the mesa portion 13. At this time, since the semiconductor laminated structure 3 is composed of a plurality of layers having different compositions as described above, the cross-sectional shapes of the first side surfaces 17A and 17B of the mesa portion 13 and the second side surfaces 18A and 18B are formed. Appears in a state in which the cross-sectional shapes of are different from each other. That is, as described above, the first side surfaces 17A and 17B include the warped portion 22 that is selectively warped, while the second side surfaces 18A and 18B are inclined in a tapered shape from the lower portion to the upper portion.

Next, as shown in FIGS. 16A and 16B, the transparent electrode layer 32 is formed on the mesa portion 13. The transparent electrode layer 32 can be formed by, for example, a vapor deposition method, a sputtering method, or the like.
Next, as shown in FIGS. 17A and 17B, the insulating layer 26 is formed so as to cover the semiconductor laminated structure 3. The insulating layer 26 may be formed by, for example, a CVD method. After that, the transparent electrode layer 32 is exposed from the insulating layer 26 by selectively removing the insulating layer 26.

Next, as shown in FIGS. 18A and 18B, the p-side electrode 34 and the metal wiring 27 are formed. The p-side electrode 34 and the metal wiring 27 may be formed by, for example, a lift-off method. More specifically, first, a resist (not shown) having an opening having the same pattern as the pattern of the p-side electrode 34 and the metal wiring 27 is formed on the semiconductor laminated structure 3. Next, an electrode material film (not shown) is laminated on the semiconductor laminated structure 3 by, for example, a thin-film deposition method. Next, the electrode material film on the resist is removed together with the resist. As a result, the p-side electrode 34 and the metal wiring 27 made of the electrode material film remaining on the semiconductor laminated structure 3 are formed.

Next, as shown in FIGS. 19A and 19B, the n-side electrode 4 is formed on the back surface of the substrate 2 by, for example, a thin-film deposition method. After that, although not shown, the above-mentioned semiconductor light emitting device 31 is obtained by dividing the substrate 2 (wafer) into chip sizes.
As described above, also in this semiconductor light emitting device 31, the metal wiring 27 straddles the intersection 29 between the first side surface 17B and the second side surface 18B in the wiring arrangement portion 19, and the first side surface 17B and the second side surface 18B Covering. Therefore, like the mesa portion 13, the curved portion 22 is formed on the first side surfaces 17A and 17B, and the shape (step coverage) that easily induces the disconnection of the metal wiring 27 as compared with the tapered second side surfaces 18A and 18B. It is possible to prevent disconnection at least on the second side surface 18B even if the shape is such that it is easy to induce a decrease in the shape. As a result, the connection state of the metal wiring 27 can be ensured, so that the connection reliability of the metal wiring 27 can be improved.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
For example, in the above-described embodiment, the wiring arrangement portion 19 is a convex portion formed by selectively projecting a part of the side surfaces 17A and 18A in the direction along the surface of the substrate 2, but FIG. As shown, a part of the side surfaces 17A and 18A may be a recess formed by selectively recessing in a direction along the surface of the substrate 2. In this case, the wiring arrangement portion 19 extends inward at right angles to the first side surface 17A of the mesa portion 13, and connects the pair of second side surfaces 18B facing each other and the ends of the pair of second side surfaces 18B. It also has a first side surface 17B parallel to the first side surface 17A of the mesa portion 13.

Further, in the above-described embodiment, the structure of the LED multi-array is shown as an example of the semiconductor light emitting device in which the wiring arrangement unit 19 is adopted, but the wiring arrangement unit 19 can also be adopted in other semiconductor light emitting devices. can. Examples of such a semiconductor light emitting device include a light emitting thyristor, a surface emitting laser (VCSEL), and the like. Further, the wiring arrangement unit 19 can be adopted not only in the semiconductor light emitting device but also in the case of forming wiring in a mesa structure having at least two or more different compositions in switching elements such as MOSFETs and IGBTs.

Further, the structure of the wiring arrangement unit 19 is not limited to the wiring for connecting a plurality of mesa portions 13 of a single element having a multi-array as described above, but is applied to a circuit structure for connecting a plurality of elements different from each other. May be good. For example, even if the structure of the wiring arrangement unit 19 is applied to a structure in which a light emitting thyristor, a diode, a transfer thyristor, a resistor, etc. are formed in a mesa shape on a common substrate and these elements are connected by wiring. good.

As an example of the light emitting thyristor array, the configuration of FIG. 21 can be shown.
In the light emitting thyristor array 40, as shown in FIG. 21, a plurality of light emitting thyristors 41 are formed on a common substrate 2. The plurality of light emitting psyllistas 41 may be arranged in a line along the second direction Y, for example.
The light emitting thyristor 41 can be used, for example, as a light source head of an electrophotographic image forming apparatus or a light source head of an image scanner. In this case, the light emitting thyristor array 40 in which a plurality of light emitting thyristors 41 are assembled is mounted on, for example, a mounting substrate of a light source head.

The plurality of light emitting thyristors 41 are separated from each other in a mesa shape by being etched to the middle portion of the semiconductor laminated structure 3. That is, a recess 42 partitioned by the drawer portion 14 is formed between the adjacent light emitting thyristors 41. Further, each light emitting thyristor 41 is formed with the above-mentioned wiring arrangement portion 19.
The gate electrodes 43 of the plurality of light emitting thyristors 41 are collectively connected by the gate wiring 44. A gate pad 45 is formed at one end of the gate wiring 44. The gate wiring 44 connects the gate electrodes 43 of the plurality of light emitting thyristors 41 to each other via the wiring arrangement portion 19.

Further, the plurality of light emitting thyristors 41 are unevenly arranged at one end of the region on the substrate 2. As a result, an electrode forming region 47 is formed on the opposite side of the gate electrode 43 with respect to the light extraction surface 46 of the plurality of light emitting thyristors 41. A surface pad 48 is formed in the electrode forming region 47. A metal wiring 49 drawn outward from each light emitting thyristor 41 via a wiring arrangement portion 19 is connected to the surface pad 48.

Further, in the above-described embodiment, a configuration in which the conductive type of each semiconductor portion of the semiconductor light emitting device 1 is inverted may be adopted. For example, in the semiconductor light emitting device 1, the p-type portion may be n-type and the n-type portion may be p-type. Therefore, in the configuration of the semiconductor light emitting device 1, the prefix of "n type" or "n side" is read as "first", and the prefix of "p type" or "p side" is read as "second". May be good.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor light emitting device 2 Substrate 3 Semiconductor laminated structure 4 n side electrode 5 p side electrode 6 Light emitting layer 7 n type semiconductor layer 8 p type semiconductor layer 13 Mesa part 14 Drawer part 15 Window part 16 Base layer 17A 1st side surface 17B 1st Side surface 18A Second side surface 18B Second side surface 19 Wiring arrangement part 21 Crossing part 22 Warping part 23 Outer edge 25 Crossing part 27 Metal wiring 28 Pad part 29 Crossing part 31 Semiconductor light emitting device 34 p side electrode 40 Light emitting thyristor array 41 Light emitting thyristor 43 Gate Electrode 44 Gate wiring 45 Gate pad 48 Surface pad 49 Metal wiring

Claims (18)

With the base layer
A semiconductor laminated structure including at least two or more layers having different compositions selectively laminated in the first region on the base layer.
A metal wiring drawn from the top of the semiconductor laminated structure through a side portion of the semiconductor laminated structure to a second region of the base layer different from the first region is included.
The semiconductor laminated structure is a wiring that is selectively formed on a part of the side portion of the semiconductor laminated structure, has a first side surface and a second side surface that intersects the first side surface, and the metal wiring is arranged. Including the placement part
The metal wiring is a semiconductor device that straddles the intersection between the first side surface and the second side surface of the wiring arrangement portion and covers the first side surface and the second side surface. The first side surface includes a concave surface that is selectively recessed from the lower part to the upper part of the first side surface, and the second side surface is tapered from the lower part to the upper part of the second side surface. The semiconductor device according to claim 1. The semiconductor device according to claim 2, wherein the concave surface of the first side surface includes a warped portion that warps from the lower part to the upper part of the first side surface. The wiring arrangement portion according to any one of claims 1 to 3, wherein the wiring arrangement portion includes a convex portion formed by selectively projecting the side portion of the semiconductor laminated structure in a direction along the surface of the base layer. The semiconductor device described. The wiring arrangement portion according to any one of claims 1 to 3, wherein the wiring arrangement portion includes a recess formed by selectively denting the side portion of the semiconductor laminated structure in a direction along the surface of the base layer. Semiconductor device. The semiconductor device according to any one of claims 1 to 5, wherein a plurality of the semiconductor laminated structures are formed on a common base layer. The semiconductor device according to claim 6, wherein the plurality of semiconductor laminated structures are arranged in a matrix along each of a first direction and a second direction orthogonal to the first direction. The semiconductor device according to claim 6, wherein the plurality of semiconductor laminated structures are arranged in a line along a first direction. The semiconductor device according to any one of claims 6 to 8, wherein the metal wiring is formed so as to straddle the plurality of semiconductor laminated structures. Including an electrode formed on the top of each of the semiconductor laminated structures,
The semiconductor device according to claim 9, wherein the metal wiring connects the electrodes of the plurality of semiconductor laminated structures to each other. The semiconductor device according to claim 10, wherein the electrodes are formed in an island shape on the top of the semiconductor laminated structure. The semiconductor device according to claim 10, wherein the electrodes are formed in an annular shape along the peripheral edge of the top of the semiconductor laminated structure. The semiconductor device according to any one of claims 9 to 12, which is formed at an end portion of the metal wiring and includes a pad portion common to the plurality of semiconductor laminated structures. The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor laminated structure is formed in a mesa shape surrounded by the second region of the base layer over the entire circumference. The semiconductor device according to any one of claims 1 to 14, further comprising a semiconductor light emitting device having a function of emitting light from the semiconductor laminated structure. The semiconductor device according to claim 15, wherein the semiconductor laminated structure includes a light emitting layer and a p-type layer and an n-type layer sandwiching the light emitting layer. The semiconductor device according to any one of claims 1 to 16, wherein the semiconductor laminated structure includes a group III-V semiconductor laminated structure. The semiconductor device according to any one of claims 1 to 17, wherein the metal wiring includes a metal wiring containing at least one of Au and Al.

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