JP2020527852A - アキシャル構成の三次元半導体構造を備えた光電子デバイス - Google Patents
アキシャル構成の三次元半導体構造を備えた光電子デバイス Download PDFInfo
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- JP2020527852A JP2020527852A JP2019572565A JP2019572565A JP2020527852A JP 2020527852 A JP2020527852 A JP 2020527852A JP 2019572565 A JP2019572565 A JP 2019572565A JP 2019572565 A JP2019572565 A JP 2019572565A JP 2020527852 A JP2020527852 A JP 2020527852A
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Abstract
Description
前記第1の導電層に垂直に延びて前記第1の導電層と接する少なくとも第3の三次元半導体素子と、
前記第1の導電層と反対の前記第3の三次元半導体素子の端部に置かれて、前記第1の波長及び前記第2の波長とは異なる第3の波長の電磁放射線を放射する又は受けることができる第3の活性領域と、
前記導電性パッドの内の1つに電気的に結合され、前記第3の活性領域に結合されている第5の導電層と
を更に有し、
前記第1の三次元半導体素子、前記第2の三次元半導体素子及び前記第3の三次元半導体素子は前記第1の導電層に垂直に測定して同一の高さを有する。
a) 前記第1の光電子回路を形成する工程、及び
b) 前記第2の導電層、前記第3の導電層及び前記第4の導電層を前記導電性パッドに電気的に結合することにより、前記第1の光電子回路を前記第2の電子回路に接合する工程
を連続的に有することを特徴とする方法を更に提供する。
c) 前記第1の三次元半導体素子及び前記第2の三次元半導体素子を支持体に同時的に形成する工程、
d) 前記第1の活性領域を前記支持体と反対の前記第1の三次元半導体素子の端部に、前記第2の活性領域を前記支持体と反対の前記第2の三次元半導体素子の端部に同時的に形成する工程、
e) 前記第2の導電層、前記第3の導電層及び前記第4の導電層を形成する工程、
f) 前記支持体を除去する工程、及び
g) 前記第1の導電層を形成する工程
を連続的に有する。
h) 前記第1の三次元半導体素子間、及び前記第2の三次元半導体素子間に電気絶縁層を形成する工程、
i) 前記第1の三次元半導体素子及び前記第2の三次元半導体素子が同一の高さを有するように、前記電気絶縁層、前記第1の三次元半導体素子及び前記第2の三次元半導体素子を部分的にエッチングする工程
を有する。
発光ダイオードによって放射される電磁放射線を少なくとも部分的に通し、表面17を画定している電気絶縁層16と、
発光ダイオードによって放射される電磁放射線を少なくとも部分的に通す導電層18と、
高さH及び直径D1を有する第1のワイヤ20(3本の第1のワイヤが示されている)、高さH及び直径D2を有する第2のワイヤ22(3本の第2のワイヤが示されている)、並びに高さH及び直径D3を有する第3のワイヤ24(3本の第3のワイヤが示されている)(第1、第2及び第3のワイヤは表面17に垂直な平行な軸芯を有し、導電層18から延びて導電層18と接しており、直径D1は直径D2より小さく、直径D2は直径D3より小さい)と、
導電層18と反対の各第1のワイヤ20の端部に設けられた第1の頭部26、導電層18と反対の各第2のワイヤ22の端部に設けられた第2の頭部28、及び導電層18と反対の各第3のワイヤ24の端部に設けられた第3の頭部30と、
高さH及びワイヤの軸芯に沿って測定された頭部26の大きさの合計と実質的に等しい厚さを有して、ワイヤ20, 22, 24間に設けられて第1の電気絶縁性材料から形成された第1の電気絶縁層32と、
第1の電気絶縁層32と同一の厚さを有して第1の電気絶縁層32の周りに延びており、第1の電気絶縁性材料とは異なるか又は第1の電気絶縁性材料と同一であってもよい第2の電気絶縁性材料から形成された電気絶縁層34と、
電気絶縁層34の厚さ全体に亘って電気絶縁層34を通って延びている開口部36と、
開口部36内を延びて、導電層18に接している導電層38と、
電気絶縁層32、電気絶縁層34、導電層38、及び電気絶縁層32から突出している頭部26, 28, 30の部分上に設けられて導電性材料から形成されており、特に電気絶縁層32から突出している頭部26, 28, 30の部分と接している別個の導電性部分40と、
別個の導電層42, 44, 46, 48(導電層42は第1の頭部26と接しており、導電層44は第2の頭部28と接しており、導電層46は第3の頭部30と接しており、導電層48は導電層38と接している)と、
導電層42, 44, 46, 48を覆って導電層42, 44, 46, 48間に延びており、好ましくは実質的に平坦な表面51を画定している電気絶縁層50と、
多層構造を有することができ、絶縁層50を通って延びて表面51と面一である導電性パッド52, 54, 56, 58(導電性パッド52は導電層42と接しており、導電性パッド54は導電層44と接しており、導電性パッド56は導電層46と接しており、導電性パッド58は導電層48と接している)と
を有している。
ワイヤ20と同一の材料から形成されて、第1の導電型、例えばN型でドープされた半導体部分64、
活性領域66、及び
第2の導電型、例えばP型でドープされた半導体部分68
を連続的に有している。
図8Aの下から上に、基板71、シード層とも称される少なくとも1つの核生成層(図8Aには例として2つのシード層72, 73が示されている)、電気絶縁層74、及び電気絶縁層74の材料とは異なる材料で形成されている電気絶縁層74上の電気絶縁層76の積層体に相当する支持体70を形成する工程、
第1の開口部78の直径が第1のワイヤ20の直径に実質的に相当するように電気絶縁層74に第1の開口部78を形成して、第1のワイヤ20の所望の位置でシード層73の一部を露出させ、第2の開口部80の直径が第2のワイヤ22の直径に実質的に相当するように電気絶縁層74, 76に第2の開口部80を形成して、第2のワイヤ22の所望の位置でシード層73の一部を露出させ、第3の開口部82の直径が第3のワイヤ24の直径に実質的に相当するように電気絶縁層74, 76に第3の開口部82を形成して、第3のワイヤ24の所望の位置でシード層73の一部を露出させる工程、及び
開口部78, 80, 82内でシード層72からワイヤ20, 22, 24を同時的に成長させる工程
の後に得られた構造を示す。
絶縁層32を形成する工程、
絶縁層34を形成する工程、及び
絶縁層34を厚さの一部に亘ってエッチング又は薄くして、実質的に平坦な表面86を画定する工程
の後に得られた構造を示す。
エッチング停止層が頭部26, 28, 30上に設けられている場合、エッチング停止層を除去する工程、及び
頭部26, 28, 30の露出部分、絶縁層32及び絶縁層34上に金属部分40を形成する工程
の後に得られた構造を示す。
例えばカソードスパッタリング法によって、図8Hに示されている構造上に、例えば0.5 μmの厚さを有する金属層を堆積させる工程、及び
この金属層をエッチングして導電層42, 44, 46, 48を画定する工程
の後に得られた構造を示す。
図8Iに示されている構造に亘って絶縁層50を堆積させる工程、及び
導電性パッド52, 54, 56, 58を、例えば銅で形成する工程
の後に得られた構造を示す。
Claims (12)
- 第1の光電子回路(12)が第2の電子回路(14)に接合されている光電子デバイス(10)を製造する方法であって、
前記第2の電子回路(14)は導電性パッド(62)を有し、
前記第1の光電子回路は複数の画素を有し、前記画素毎に、
第1の導電層(18)と、
前記第1の導電層に垂直に延びて前記第1の導電層と接し、前記第1の導電層に垂直に測定して同一の高さ(H) を有する少なくとも第1の三次元半導体素子(20)及び第2の三次元半導体素子(22)と、
前記第1の導電層と反対の前記第1の三次元半導体素子の端部に置かれて、第1の波長の第1の電磁放射線を放射する又は受けることができる第1の活性領域(66)と、
前記第1の導電層と反対の前記第2の三次元半導体素子の端部に置かれて、前記第1の波長とは異なる第2の波長の第2の電磁放射線を放射する又は受けることができる第2の活性領域(66)と、
前記導電性パッド(62)に電気的に結合されている第2の導電層(42)、第3の導電層(44)及び第4の導電層(48)と
を有し、前記第2の導電層(42)は前記第1の活性領域に結合され、前記第3の導電層(44)は前記第2の活性領域に結合され、前記第4の導電層(48)は前記第1の導電層に結合されており、
前記方法は、
a) 前記第1の光電子回路(12)を形成する工程、及び
b) 前記第2の導電層(42)、前記第3の導電層(44)及び前記第4の導電層(48)を前記導電性パッド(62)に電気的に結合することにより、前記第1の光電子回路(12)を前記第2の電子回路(14)に接合する工程
を連続的に有し、
工程a)は、
c) 前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)を支持体(70)に同時的に形成する工程、
d) 前記第1の三次元半導体素子(20)間、及び前記第2の三次元半導体素子(22)間に電気絶縁層(32)を形成する工程、
e) 前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)が同一の高さ(H) を有するように、前記電気絶縁層(32)、前記第1の三次元半導体素子及び前記第2の三次元半導体素子を部分的にエッチングする工程、
f) 前記第1の活性領域(66)を前記支持体と反対の前記第1の三次元半導体素子の端部に、前記第2の活性領域(66)を前記支持体と反対の前記第2の三次元半導体素子の端部に同時的に形成する工程、
g) 前記第2の導電層(42)、前記第3の導電層(44)及び前記第4の導電層(48)を形成する工程、
h) 前記支持体を除去する工程、及び
i) 前記第1の導電層(18)を形成する工程
を連続的に有することを特徴とする方法。 - 工程h)及び工程i)の間に、前記電気絶縁層(32)、前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)を前記第1の活性領域(66)及び前記第2の活性領域(66)と反対の側でエッチングする工程を更に有することを特徴とする請求項1に記載の方法。
- 前記第1の導電層と接する前記第1の三次元半導体素子の直径(D1)は、前記第1の導電層と接する前記第2の三次元半導体素子の直径(D2)より小さいことを特徴とする請求項1又は2に記載の方法。
- 前記第1の三次元半導体素子を第1の平均ピッチに応じて規則的に分散させ、前記第2の三次元半導体素子を前記第1の平均ピッチとは異なる第2の平均ピッチに応じて規則的に分散させることを特徴とする請求項1〜3のいずれか1つに記載の方法。
- 前記第1の光電子回路(12)は、前記画素毎に、
前記第1の導電層(18)に垂直に延びて前記第1の導電層(18)と接する少なくとも第3の三次元半導体素子(24)と、
前記第1の導電層と反対の前記第3の三次元半導体素子の端部に置かれて、前記第1の波長及び前記第2の波長とは異なる第3の波長の電磁放射線を放射する又は受けることができる第3の活性領域(66)と、
前記導電性パッド(62)の内の1つに電気的に結合され、前記第3の活性領域に結合されている第5の導電層(46)と
を更に有し、
前記第1の三次元半導体素子(20)、前記第2の三次元半導体素子(22)及び前記第3の三次元半導体素子(24)は前記第1の導電層に垂直に測定して同一の高さ(H) を有することを特徴とする請求項1〜4のいずれか1つに記載の方法。 - 前記第1の導電層と接する前記第2の三次元半導体素子の直径(D2)は、前記第1の導電層と接する前記第3の三次元半導体素子の直径(D3)より小さいことを特徴とする請求項5に記載の方法。
- 前記第3の三次元半導体素子を、前記第1の平均ピッチ及び前記第2の平均ピッチとは異なる第3の平均ピッチに応じて規則的に分散させることを特徴とする請求項5又は6に記載の方法。
- 前記第1の活性領域(66)及び前記第2の活性領域(66)は単一量子井戸又は多重量子井戸を有することを特徴とする請求項1〜7のいずれか1つに記載の方法。
- 前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)を、III-V 族化合物、II-VI 族化合物、IV族の半導体及び化合物を含む群から選択された半導体材料で主に形成することを特徴とする請求項1〜8のいずれか1つに記載の方法。
- 前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)は、ワイヤ状、錐体状又は錐台状であることを特徴とする請求項1〜9のいずれか1つに記載の方法。
- 前記第1の導電層(18)と平行に測定した各画素の最大寸法は5μmより小さいことを特徴とする請求項1〜10のいずれか1つに記載の方法。
- 前記第1の三次元半導体素子(20)及び前記第2の三次元半導体素子(22)は、ワイヤ状、錐体状又は錐台状であり、
前記第1の導電層と接する前記第1の三次元半導体素子の直径(D1)は、前記第1の導電層と接する前記第2の三次元半導体素子の直径(D2)より小さく、
前記第1の活性領域(66)及び前記第2の活性領域(66)は単一量子井戸又は多重量子井戸を有し、
前記第1の活性領域によって放射される放射線の波長は、前記第2の活性領域によって放射される放射線の波長より大きいことを特徴とする請求項1〜11のいずれか1つに記載の方法。
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FR3098013B1 (fr) * | 2019-06-25 | 2021-07-02 | Commissariat Energie Atomique | Procédé de fabrication d'un dispositif optoélectronique à diodes électroluminescentes de type axial |
FR3098019B1 (fr) * | 2019-06-25 | 2022-05-20 | Aledia | Dispositif optoélectronique comprenant des éléments semi-conducteurs tridimensionnels et procédé pour sa fabrication |
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CN111430518A (zh) * | 2019-12-13 | 2020-07-17 | 深圳第三代半导体研究院 | 一种Micro-LED芯片及其制造方法 |
FR3111016B1 (fr) * | 2020-06-01 | 2023-01-13 | Aledia | Dispositif optoélectronique et procédé de fabrication |
FR3114682B1 (fr) * | 2020-09-29 | 2023-05-19 | Aledia | Dispositif optoelectronique a diodes electroluminescentes a affichage couleur |
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WO2019002786A1 (fr) | 2019-01-03 |
TW201911558A (zh) | 2019-03-16 |
EP3646383A1 (fr) | 2020-05-06 |
US20210313497A1 (en) | 2021-10-07 |
FR3068517B1 (fr) | 2019-08-09 |
CN111033747B (zh) | 2023-10-13 |
TWI775886B (zh) | 2022-09-01 |
EP3646383B1 (fr) | 2022-08-17 |
KR102526313B1 (ko) | 2023-04-26 |
KR20200019215A (ko) | 2020-02-21 |
US11195878B2 (en) | 2021-12-07 |
CN111033747A (zh) | 2020-04-17 |
FR3068517A1 (fr) | 2019-01-04 |
JP7146827B2 (ja) | 2022-10-04 |
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