JP2020521325A5 - - Google Patents

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Publication number
JP2020521325A5
JP2020521325A5 JP2019563887A JP2019563887A JP2020521325A5 JP 2020521325 A5 JP2020521325 A5 JP 2020521325A5 JP 2019563887 A JP2019563887 A JP 2019563887A JP 2019563887 A JP2019563887 A JP 2019563887A JP 2020521325 A5 JP2020521325 A5 JP 2020521325A5
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JP
Japan
Prior art keywords
trench
height difference
physical parameters
core
gap
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JP2019563887A
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English (en)
Japanese (ja)
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JP7026140B2 (ja
JP2020521325A (ja
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Priority claimed from US15/982,918 external-priority patent/US10748272B2/en
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Publication of JP2020521325A5 publication Critical patent/JP2020521325A5/ja
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JP2019563887A 2017-05-18 2018-05-18 半導体ウエハ上のパターン内の高低差の測定 Active JP7026140B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762508312P 2017-05-18 2017-05-18
US62/508,312 2017-05-18
US15/982,918 US10748272B2 (en) 2017-05-18 2018-05-17 Measuring height difference in patterns on semiconductor wafers
US15/982,918 2018-05-17
PCT/US2018/033480 WO2018213758A2 (en) 2017-05-18 2018-05-18 Measuring height difference in patterns on semiconductor wafers

Publications (3)

Publication Number Publication Date
JP2020521325A JP2020521325A (ja) 2020-07-16
JP2020521325A5 true JP2020521325A5 (enExample) 2021-07-26
JP7026140B2 JP7026140B2 (ja) 2022-02-25

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JP2019563887A Active JP7026140B2 (ja) 2017-05-18 2018-05-18 半導体ウエハ上のパターン内の高低差の測定

Country Status (6)

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US (2) US10748272B2 (enExample)
JP (1) JP7026140B2 (enExample)
KR (1) KR102341667B1 (enExample)
CN (2) CN110622289B (enExample)
TW (1) TWI757489B (enExample)
WO (1) WO2018213758A2 (enExample)

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CN112639396B (zh) * 2019-08-07 2022-11-11 株式会社日立高新技术 尺寸测量装置、尺寸测量方法以及半导体制造系统
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CN113594057B (zh) * 2021-08-05 2024-02-02 上海天岳半导体材料有限公司 一种晶片的原子台阶的宽度计算装置、方法、设备及介质
US12175656B2 (en) * 2022-02-23 2024-12-24 Applied Materials Israel Ltd. Gray level ratio inspection
US11662324B1 (en) * 2022-03-18 2023-05-30 Applied Materials Israel Ltd. Three-dimensional surface metrology of wafers
WO2024178198A1 (en) * 2023-02-24 2024-08-29 Fractilia, Llc Method of dispositioning and control of a semiconductor manufacturing process

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