JP2020505770A - 相互接続構造及びその形成方法 - Google Patents
相互接続構造及びその形成方法 Download PDFInfo
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- JP2020505770A JP2020505770A JP2019539194A JP2019539194A JP2020505770A JP 2020505770 A JP2020505770 A JP 2020505770A JP 2019539194 A JP2019539194 A JP 2019539194A JP 2019539194 A JP2019539194 A JP 2019539194A JP 2020505770 A JP2020505770 A JP 2020505770A
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- metal
- opening
- dielectric material
- interconnect
- semiconductor device
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
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Abstract
Description
本出願は、2017年1月20日に出願された米国仮出願第62/448,788号の利益を主張し、その全内容は参照により本明細書に組み込まれる。
Claims (20)
- 半導体デバイスであって、
誘電体材料を有する基板と、
前記誘電体材料内に形成された相互接続開口と、
前記誘電体材料内に形成された前記相互接続開口の表面をコンフォーマルに覆う第1金属と、
前記相互接続開口内に相互接続構造を形成するために、前記第1金属上に形成されており、前記第1金属によってカプセル化されている第2金属と、
を備える、半導体デバイス。 - 前記相互接続開口は、トレンチ開口、ビア開口、又はデュアルダマシン開口を含む、
請求項1記載の半導体デバイス。 - 前記第1金属は、Ru、Cu、W、Al、又はCoを含み、前記誘電体材料に直接接触しており、前記第2金属へのバリア/ライナとして作用する、
請求項1記載の半導体デバイス。 - 前記第2金属は、Cu、Mn、Al、W及びCoを含み、前記第1金属よりも低い抵抗率を有する、
請求項1記載の半導体デバイス。 - 前記誘電体材料内に形成された複数の導電層をさらに備え、
前記導電層は前記相互接続構造の底部にあり、前記複数の導電層のうちの少なくとも1つは前記相互接続構造と直接接触している、
請求項1記載の半導体デバイス。 - 前記導電層はRu、Cu、W、Al又はCoを含む、
請求項5記載の半導体デバイス。 - 前記誘電体材料は、層間絶縁層(ILD)、金属間絶縁層(IMD)及び低K材料層のうちの少なくとも1つを含む、
請求項1記載の半導体デバイス。 - 前記相互接続構造の頂部表面は前記誘電体材料の頂部表面よりも低い、
請求項1記載の半導体デバイス。 - 前記第1金属は、前記誘電体材料に直接接触し、前記第2金属の頂部表面は、前記第1金属の頂部表面と同じ高さである、
請求項1記載の半導体デバイス。 - 半導体デバイスを製造する方法であって、
基板上に誘電体材料を設けるステップと、
前記誘電体材料内に相互接続開口を形成するステップと、
前記相互接続開口の表面をコンフォーマルに覆うために第1金属を堆積するステップと、
前記相互接続開口を充填するために前記第1金属上に第2金属を堆積させるステップと、
前記相互接続開口内の前記第2金属を凹部形成するステップと、
前記相互接続開口を完全に充填するために、前記第1金属及び前記第2金属上に第3金属を堆積するステップと、
前記半導体デバイスを平坦化するステップであって、前記誘電体材料の頂部表面は前記第3金属の頂部表面と同じ高さとする、ステップと、
を有する方法。 - 前記第3金属を凹部形成するステップであって、前記相互接続開口内の前記第3金属の頂部表面は、前記誘電体材料の頂部表面よりも低い、ステップをさらに含む、
請求項10記載の方法。 - 前記誘電体材料を形成するステップは、前記誘電体材料内に複数の導電層を形成するステップを含む、
請求項10記載の方法。 - 前記誘電体材料内に前記導電層を形成するステップは、前記相互接続開口の底部に前記導電層を形成するステップを含み、
前記複数の導電層のうちの少なくとも1つは、前記相互接続開口内に充填された金属と直接接触する、
請求項12記載の方法。 - 前記相互接続開口を形成するステップは、トレンチ開口、ビア開口又はデュアルダマシン開口を形成するステップを含む、
請求項10記載の方法。 - 前記誘電体材料内に相互接続開口を形成するステップは、
前記誘電体材料上にハードマスク積層体を形成するステップと、
前記ハードマスク積層体をエッチングしてハードマスクパターンを形成する第1エッチングプロセスを実行するステップと、
パターニングされた前記ハードマスク積層体上にスピンオンカーボン(SOC)層をコーティングし、前記SOC層をパターニングするステップと、
パターニングされた前記SOC層をマスクとして使用することにより前記誘電体材料内へエッチングダウンする第2エッチングプロセスを実行するステップと、
前記SOC層を除去するステップと、
トレンチ開口、ビア開口又はデュアルダマシン開口を有する相互接続開口の形成を完了するために、パターニングされた前記ハードマスク積層体をマスクとして使用することにより、前記誘電体材料内へエッチングダウンする第3エッチングプロセスを実行するステップと、
を含む、請求項10記載の方法。 - 前記第1金属の上に前記第2金属を堆積するステップは、前記誘電体材料の頂部表面上に、前記相互接続開口内のトレンチの底部上に、及び、前記相互接続開口内の前記トレンチの側壁に沿って、前記第2金属を堆積するステップを含む、
請求項10記載の方法。 - 前記第2金属を凹部形成するステップは、
前記誘電体材料の頂部表面上の部分及び前記相互接続開口内のトレンチの側壁に沿った部分を完全に除去するステップと、
前記相互接続開口内のトレンチの底部上の部分を部分的に除去するステップと、を含む、
請求項10記載の方法。 - 前記第2金属を堆積するステップは、前記第1金属と同じ金属を堆積されるステップを含む、
請求項10記載の方法。 - 前記第1金属及び前記第3金属で前記第2金属をカプセル化するステップをさらに含み、
前記第2金属は、前記相互接続開口内で、前記第1金属上に形成されており、前記第3金属によって覆われている、
請求項10記載の方法。 - 前記第1金属を堆積するステップは、
原子層堆積(ALD)プロセス又はコンフォーマルCVDプロセスを介して前記第1金属を堆積するステップを含み、
前記第1金属は、前記相互接続開口の表面をコンフォーマルに覆い、前記誘電体材料と直接接触し、前記第2金属に対するバリア/ライナとして作用する、
請求項10記載の方法。
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US10833078B2 (en) | 2017-12-04 | 2020-11-10 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
TWI681537B (zh) * | 2019-05-30 | 2020-01-01 | 旺宏電子股份有限公司 | 半導體結構與連線結構的製作方法 |
CN113223998B (zh) * | 2020-02-04 | 2022-10-04 | 联芯集成电路制造(厦门)有限公司 | 具有金属间介电图案的半导体元件的制作方法 |
US20220093505A1 (en) * | 2020-09-24 | 2022-03-24 | Intel Corporation | Via connections for staggered interconnect lines |
US11776895B2 (en) * | 2021-05-06 | 2023-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for manufacturing the same |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191254A (ja) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US20060094236A1 (en) * | 2004-11-03 | 2006-05-04 | Elkins Patricia C | Electroless plating of metal caps for chalcogenide-based memory devices |
US20060097397A1 (en) * | 2004-11-10 | 2006-05-11 | Russell Stephen W | Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device |
US20070059925A1 (en) * | 2005-09-13 | 2007-03-15 | Kyung-In Choi | Method of forming metal wiring layer of semiconductor device |
US20130270703A1 (en) * | 2011-12-21 | 2013-10-17 | Daniel J. Zierath | Electroless filled conductive structures |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7285867B2 (en) * | 2002-11-08 | 2007-10-23 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
US6992344B2 (en) * | 2002-12-13 | 2006-01-31 | International Business Machines Corporation | Damascene integration scheme for developing metal-insulator-metal capacitors |
US6899796B2 (en) * | 2003-01-10 | 2005-05-31 | Applied Materials, Inc. | Partially filling copper seed layer |
US7265038B2 (en) * | 2003-11-25 | 2007-09-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a multi-layer seed layer for improved Cu ECP |
US7176141B2 (en) * | 2004-09-07 | 2007-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plasma treatment to improve barrier layer performance over porous low-K insulating dielectrics |
KR100870271B1 (ko) | 2007-06-28 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 및 그의 형성 방법 |
US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
US8791549B2 (en) * | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
KR101802435B1 (ko) * | 2011-03-28 | 2017-11-29 | 삼성전자주식회사 | 반도체 장치의 금속 배선 형성 방법 |
US8796853B2 (en) * | 2012-02-24 | 2014-08-05 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
US9349636B2 (en) | 2013-09-26 | 2016-05-24 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
KR102092863B1 (ko) * | 2013-12-30 | 2020-03-24 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US9728445B2 (en) * | 2014-01-22 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming conducting via and damascene structure |
CN107836034B (zh) | 2015-06-05 | 2022-07-19 | 东京毅力科创株式会社 | 用于互连的钌金属特征部填充 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191254A (ja) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US20060094236A1 (en) * | 2004-11-03 | 2006-05-04 | Elkins Patricia C | Electroless plating of metal caps for chalcogenide-based memory devices |
US20060097397A1 (en) * | 2004-11-10 | 2006-05-11 | Russell Stephen W | Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device |
US20070059925A1 (en) * | 2005-09-13 | 2007-03-15 | Kyung-In Choi | Method of forming metal wiring layer of semiconductor device |
US20130270703A1 (en) * | 2011-12-21 | 2013-10-17 | Daniel J. Zierath | Electroless filled conductive structures |
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