JP2020188078A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of controlling spreading of a bonding material between an island and a semiconductor chip.SOLUTION: A semiconductor device 1 includes: an island 2 having a first surface 19 and a second surface 20; a bonding material 4 formed on the island 2; a semiconductor chip 5 formed on the bonding material 4 and including a first electrode 46 in contact with the bonding material 4; and a sealing resin 6 for covering the island 2, the bonding material 4, and the semiconductor chip 5 so that the second surface 20 of the island 2 is exposed therefrom. Arithmetic average roughness Ra of the first surface 19 of the island 2 is less than 0.1 μm.SELECTED DRAWING: Figure 4A

Description

The present invention relates to a semiconductor device.

Patent Document 1 discloses a QFN ((Quad For Non-Lead Package) type semiconductor device. In the manufacturing process of the semiconductor device, the die pad, a linear diver surrounding the die pad, and the diver are integrated. A lead frame containing a plurality of leads extending perpendicular to the diver is prepared. A semiconductor chip is bonded onto the die pad, and after bonding, a plurality of electrode pads and a plurality of leads of the semiconductor chip are formed. It is connected by the wire of.

JP-A-2015-060876

For example, as an example of a structure in which a semiconductor chip is arranged on a die pad as in Patent Document 1, there is a structure in which a die pad and a semiconductor chip are joined via a conductive bonding material. In this structure, the current flowing in the thickness direction of the semiconductor chip can be passed vertically through the bonding material to the die pad, and further from the back surface of the die pad to the wiring on the mounting substrate.
Since the bonding material forms a part of the current path, it is preferable that the bonding material is not damaged such as cracks. On the other hand, when the material of the bonding material and the material of the die pad are different from each other, when they are exposed to temperature changes during the manufacturing process, cracks are likely to occur in the bonding material due to the difference in the coefficient of linear expansion of each other. ..

As a countermeasure, it is considered to reduce the stress generated in the joint material due to the difference in the coefficient of linear expansion by forming a thick joint material. However, if the amount of the bonding material is increased, the bonding material tends to spread on the surface of the die pad, and in some cases, the bonding material may leak from the front surface to the back surface of the die pad.
An object of the present invention is to provide a semiconductor device capable of controlling the spread of a bonding material between an island and a semiconductor chip.

Another object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of cracks in the bonding material due to stress and allowing a good current to flow in the longitudinal direction from the semiconductor chip toward the island. is there.

The semiconductor device according to one aspect of the present invention is a conductive junction formed on a conductive island having a first surface and a second surface on the opposite side thereof and made of a material different from the island. The island, the bonding material, and the semiconductor chip are covered so that the material, the semiconductor chip formed on the bonding material and having the first electrode in contact with the bonding material, and the second surface of the island are exposed. The arithmetic mean roughness Ra of the first surface of the island, including the sealing resin, is less than 0.1 μm.

The semiconductor device according to another aspect of the present invention is formed on a conductive island having a first surface and a second surface on the opposite side thereof, and having a thickness of 20 μm to 80 μm, and said. A conductive bonding material made of a material different from the island, a semiconductor chip formed on the bonding material, having a first electrode in contact with the bonding material, and formed in a rectangular shape in a plan view, and the island. The island, the bonding material, and a sealing resin covering the semiconductor chip are included so that the second surface is exposed, and a part of the bonding material is only one side of the semiconductor chip or 2 in a plan view. It is leaking only from the side.

According to the semiconductor device according to one aspect of the present invention, the arithmetic mean roughness Ra of the first surface of the island is less than 0.1 μm. As a result, when the joint material is formed on the first surface of the island, it is possible to prevent the joint material from expanding widely.
For example, consider the case where a large number of convex portions are formed on the first surface of the island and the arithmetic mean roughness Ra of the first surface is not less than 0.1 μm. In this case, the bonding material on the first surface of the island may expand widely due to the capillary phenomenon of fine recesses (grooves and the like) between a large number of convex portions. On the other hand, if the arithmetic mean roughness Ra of the first surface of the island is less than 0.1 μm, the capillary phenomenon can be suppressed, and as a result, it is possible to suppress the wide expansion of the bonding material. it can.

As a result, the bonding material can be made relatively thick. By making the joint material thicker, the stress generated in the joint material due to the difference in the coefficient of linear expansion between the joint material and the island can be relaxed. As a result, the occurrence of cracks in the bonding material due to the stress can be suppressed, and the increase in resistance of the bonding material can be suppressed. As a result, a current can be satisfactorily flowed from the semiconductor chip toward the island in the vertical direction.

According to the semiconductor device according to another aspect of the present invention, in a plan view, a part of the bonding material leaks from only one side or only two sides of the semiconductor chip. That is, the capillary phenomenon on the first surface of the island is suppressed, and as a result, the wide expansion of the bonding material is suppressed.
Further, since the bonding material has a thickness of 20 μm to 80 μm, the stress generated in the bonding material due to the difference in the coefficient of linear expansion between the bonding material and the island can be relaxed. As a result, the occurrence of cracks in the bonding material due to the stress can be suppressed, and the increase in resistance of the bonding material can be suppressed. As a result, a current can be satisfactorily flowed from the semiconductor chip toward the island in the vertical direction.

FIG. 1 is a schematic perspective view of the upper surface side of the semiconductor device according to the embodiment of the present invention. FIG. 2 is a schematic perspective view of the lower surface side of the semiconductor device. FIG. 3 is a schematic plan view (partially seen through) of the semiconductor device. FIG. 4A is a diagram showing a cross section of IVA-IVA of FIG. FIG. 4B is a diagram showing a cross section of IVB-IVB of FIG. FIG. 5 is an SEM image showing the surface state of the first surface of the island and the lead of the semiconductor device. FIG. 6 is an SEM image showing the surface state of the first surface of the island of the semiconductor device according to the reference example. FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor device. FIG. 7B is a diagram showing the next step of FIG. 7A. FIG. 7C is a diagram showing the next step of FIG. 7B. FIG. 7D is a diagram showing the next step of FIG. 7C. FIG. 7E is a diagram showing the next step of FIG. 7D. FIG. 7F is a diagram showing the next step of FIG. 7E. FIG. 7G is a diagram showing the next step of FIG. 7F. FIG. 8 is a diagram showing a process related to molding of a joint material by a spanker. FIG. 9 is a diagram showing the results of matrix evaluation of Examples. FIG. 10 is a diagram showing the results of matrix evaluation of the reference example.

<Embodiment of the present invention>
First, embodiments of the present invention will be listed and described.
The semiconductor device according to an embodiment of the present invention is a conductive junction formed on a conductive island having a first surface and a second surface on the opposite side thereof and made of a material different from the island. The island, the bonding material, and the semiconductor chip are covered so that the material, the semiconductor chip formed on the bonding material and having the first electrode in contact with the bonding material, and the second surface of the island are exposed. The arithmetic mean roughness Ra of the first surface of the island, including the sealing resin, is less than 0.1 μm.

According to this configuration, the arithmetic mean roughness Ra of the first surface of the island is less than 0.1 μm. As a result, when the joint material is formed on the first surface of the island, it is possible to prevent the joint material from expanding widely.
For example, consider the case where a large number of convex portions are formed on the first surface of the island and the arithmetic mean roughness Ra of the first surface is not less than 0.1 μm. In this case, the bonding material on the first surface of the island may expand widely due to the capillary phenomenon of fine recesses (grooves and the like) between a large number of convex portions. On the other hand, if the arithmetic mean roughness Ra of the first surface of the island is less than 0.1 μm, the capillary phenomenon can be suppressed, and as a result, it is possible to suppress the wide expansion of the bonding material. it can.

As a result, the bonding material can be made relatively thick. By making the joint material thicker, the stress generated in the joint material due to the difference in the coefficient of linear expansion between the joint material and the island can be relaxed. As a result, the occurrence of cracks in the bonding material due to the stress can be suppressed, and the increase in resistance of the bonding material can be suppressed. As a result, a current can be satisfactorily flowed from the semiconductor chip toward the island in the vertical direction.

In the semiconductor device according to the embodiment of the present invention, the thickness of the bonding material may be 20 μm to 80 μm.
When the thickness of the joint material is 20 μm to 80 μm, the stress generated in the joint material due to the difference in the coefficient of linear expansion between the joint material and the island can be satisfactorily relaxed.
In the semiconductor device according to the embodiment of the present invention, the semiconductor chip is formed in a rectangular shape in a plan view, and in a plan view, a part of the bonding material is only one side or only two sides of the semiconductor chip. It may leak from.

The semiconductor device according to the embodiment of the present invention has a conductive island having a first surface and a second surface on the opposite side thereof, and the semiconductor device formed on the island and having a thickness of 20 μm to 80 μm, and said. A conductive bonding material made of a material different from the island, a semiconductor chip formed on the bonding material, having a first electrode in contact with the bonding material, and formed in a rectangular shape in a plan view, and the island. The island, the bonding material, and a sealing resin covering the semiconductor chip are included so that the second surface is exposed, and a part of the bonding material is only one side of the semiconductor chip or 2 in a plan view. It is leaking only from the side.

According to this configuration, in a plan view, a part of the bonding material leaks from only one side or only two sides of the semiconductor chip. That is, the capillary phenomenon on the first surface of the island is suppressed, and as a result, the wide expansion of the bonding material is suppressed.
Further, since the bonding material has a thickness of 20 μm to 80 μm, the stress generated in the bonding material due to the difference in the coefficient of linear expansion between the bonding material and the island can be relaxed. As a result, the occurrence of cracks in the bonding material due to the stress can be suppressed, and the increase in resistance of the bonding material can be suppressed. As a result, a current can be satisfactorily flowed from the semiconductor chip toward the island in the vertical direction.

In the semiconductor device according to the embodiment of the present invention, the portion of the bonding material leaking from the semiconductor chip may not reach the edge of the island, or may reach the edge of the island. Good. In the latter case, when the island has a third surface connecting the first surface and the second surface of the island, the portion of the bonding material leaking from the semiconductor chip is the said. The first surface of the island may reach the third surface.

In the semiconductor device according to the embodiment of the present invention, the island is composed of a first base material made of a metal containing Cu as a main component and a metal containing Ni as a main component formed on the first base material. The first surface plating layer may include the first surface plating layer, and the first surface plating layer may form the first surface of the island.
In the semiconductor device according to the embodiment of the present invention, the island is composed of a first base material made of a metal containing Cu as a main component and a metal containing Ni as a main component formed on the first base material. The first surface layer plating layer includes the first surface layer plating layer, the first surface layer plating layer forms the first surface of the island, and the bonding material may be made of a metal containing solder as a main component.

In the semiconductor device according to the embodiment of the present invention, the first base material has a first surface, a second surface on the opposite side thereof, and a third surface connecting the first surface and the second surface. The first surface plating layer may cover all of the first surface, the second surface, and the third surface of the first base material.
In the semiconductor device according to the embodiment of the present invention, the semiconductor chip includes a second electrode formed on the opposite side of the first electrode in the thickness direction of the semiconductor chip, and the semiconductor device is from the island. The arithmetic average roughness Ra of the first surface of the lead includes a lead that is separated and has a first surface and a second surface on the opposite side thereof, and a wire that connects the lead and the second electrode. May be less than 0.1 μm.

According to this configuration, the arithmetic mean roughness Ra of the first surface of the reed is less than 0.1 μm. As a result, the substantially joining area of the wire to the lead can be increased, so that the joining property of the wire can be improved.
In the semiconductor device according to the embodiment of the present invention, the lead is composed of a second base material made of a metal containing Cu as a main component and a metal containing Ni as a main component formed on the second base material. The second surface plating layer may include the second surface plating layer, and the second surface plating layer may form the first surface of the lead.

In the semiconductor device according to the embodiment of the present invention, the second base material has a first surface, a second surface on the opposite side thereof, and a third surface connecting the first surface and the second surface. The second surface plating layer may cover all of the first surface, the second surface, and the third surface of the second base material.
In the semiconductor device according to the embodiment of the present invention, the lead includes a first lead and a second lead different from the first lead, and the first lead is a plurality of first leads exposed from the sealing resin. The first outer lead and the first inner lead that connects the extension portions of the plurality of first outer leads in the sealing resin are included, and the second lead is a plurality of second outers exposed from the sealing resin. A lead and a second inner lead connected to each of the second outer leads on a one-to-one basis may be included.

In the semiconductor device according to the embodiment of the present invention, the sealing resin is formed in a rectangular shape in a plan view, and the first lead is arranged on the first side side of the sealing resin. The second lead may be arranged on the second side side of the sealing resin facing the first side.
In the semiconductor device according to the embodiment of the present invention, the leads may not be arranged on the third side side of the sealing resin and the fourth side side facing the third side.

In the semiconductor device according to the embodiment of the present invention, the second electrode of the semiconductor chip includes a relatively large first pad and a second pad having an area smaller than that of the first pad, and the wire. Is a plurality of first wires connecting one first pad and one first inner lead, and one second wire connecting one second pad and one second inner lead. It may include a wire.

In the semiconductor device according to the embodiment of the present invention, the sealing resin may be made of a material containing an epoxy resin as a main component.
<Detailed Description of Embodiments of the Present Invention>
Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic perspective view of the upper surface side of the semiconductor device 1 according to the embodiment of the present invention. FIG. 2 is a schematic perspective view of the lower surface side of the semiconductor device 1. FIG. 3 is a schematic plan view of the semiconductor device 1 and is a perspective view of the inside of the sealing resin 6. FIG. 4A is a diagram showing a cross section of IVA-IVA of FIG. FIG. 4B is a diagram showing a cross section of IVB-IVB of FIG. FIG. 5 is an SEM image showing the surface states of the first surface 19 of the island 2 of the semiconductor device 1 and the first surface 42 of the lead 3. FIG. 6 is an SEM image showing the surface state of the first surface 64 of the island 63 of the semiconductor device according to the reference example.

The semiconductor device 1 incorporates, for example, various switching elements (for example, MOSFET, IGBT, bipolar transistor, diode, etc.) and various protection circuits (for example, a protection circuit having an overcurrent / overheat detection function) on one chip. It may be a switch. More specifically, the semiconductor device 1 may be an in-vehicle grade universal switch in which a MOSFET and its protection circuit are built in one chip. Further, the semiconductor device 1 may be referred to as an IPD (Intelligent Power Device).

In this embodiment, the semiconductor device 1 is a SOP (Small Outline Package) type semiconductor package. The semiconductor device 1 includes an island 2, a reed 3, a bonding material 4, a semiconductor chip 5, and a sealing resin 6.
The sealing resin 6 seals the island 2, the lead 3, the bonding material 4, and the semiconductor chip 5 by covering them. The sealing resin 6 is formed in a rectangular parallelepiped shape, and is formed in a rectangular shape (rectangular shape) in a plan view shown in FIG. The sealing resin 6 has a first side 6A and a second side 6B facing each other, and a third side 6C and a fourth side 6D facing each other in a plan view.

With reference to FIG. 3, the island 2 is formed in a substantially rectangular shape (substantially rectangular shape) in a plan view. The island 2 has a first side 2A and a second side 2B facing each other, and a third side 2C and a fourth side 2D facing each other. In this embodiment, the first side 2A and the second side 2B are the long sides of the island 2, and the third side 2C and the fourth side 2D are the short sides of the island 2. The island 2 may be referred to as a die pad in another way. Further, the first side 2A, the second side 2B, the third side 2C, and the fourth side 2D of the island 2 are referred to as a first edge, a second edge, a third edge, and a fourth edge, respectively. May be good.

At least one peripheral edge 7 of the island 2 may selectively project. Therefore, the island 2 may have a substantially rectangular shape (substantially rectangular shape) in which at least one peripheral edge portion 7 selectively protrudes. In other words, by selectively projecting at least one peripheral edge portion 7, a notch portion 8 is formed in a part (four corner portions in this embodiment) of the sides 2A to 2D of the island 2. ing. That is, the island 2 may have a substantially rectangular shape (substantially rectangular shape) in which a notch portion 8 is formed at at least one corner portion.

Here, the peripheral edge portion 7 of the island 2 is a portion of each side 2A to 2D of the island 2 and a portion in the vicinity thereof. In this embodiment, the portion not covered by the semiconductor chip 5 in the plan view may be defined as the peripheral edge portion 7 of the island 2. In this embodiment, a part of the peripheral edge portion 7 along the pair of short sides (third side 2C and fourth side 2D) of the island 2 protrudes to form a pair of protruding portions 9 of the island 2. The pair of protrusions 9 are line-symmetric with respect to the axis A passing through the center of the other sides of the island 2 (in this embodiment, the long sides, the first side 2A and the second side 2B).

Further, each protruding portion 9 is formed at a portion separated from both ends of the third side 2C and the fourth side 2D of the island 2. As a result, a pair of notches 8 are formed at both ends of the third side 2C and the fourth side 2D of the island 2. Each protrusion 9 is sandwiched between a pair of notches 8 in a plan view. Further, each of the protrusions 9 and the pair of notches 8 are line-symmetric with respect to the axis B passing through the center of the third side 2C and the fourth side 2D of the island 2.

Each protrusion 9 has a substantially rectangular shape in a plan view. On the other hand, each notch 8 has a first step 10 having a first distance L1 toward the inside of the island 2 with respect to the sides 2C and 2D, and a second distance L2 shorter than the first distance L1. It may consist of a combination with the second step 11 having. That is, each notch 8 extends along the first side 2A and the second side 2B of the island 2, and forms a straight side 12 forming one side of each protruding portion 9, and the third side 2C of the island 2 and the island 2. It may extend along the fourth side 2D and may be partitioned by a non-linear (for example, crank-shaped, S-shaped, etc.) side 13.

With reference to FIGS. 4A and 4B, the island 2 includes a first base material 14 and a first surface plating layer 15 formed on the first base material 14.
The first base material 14 is made of a metal containing Cu as a main component. For example, the coefficient of linear expansion of a metal containing Cu as a main component may be 16 ( ^10-6 / K) to 19 ( ^10-6 / K). Here, the "metal containing Cu as a main component" is a metal in which the mass ratio (mass%) of Cu constituting the first base material 14 is the highest with respect to other components constituting the first base material 14. It means that.

When the first base material 14 is made of a Cu—Sn alloy, the mass ratio R _Cu of _Cu is higher than the mass ratio R _{Sn of Sn} (R _Cu > R _Sn ). The "metal containing Cu as a main component" may contain trace impurities, but high-purity copper having a purity of 99.99999% (6N) or more and high-purity copper having a purity of 99.99% (4N) or more. Etc. are also included. Examples of other Cu alloys include known Cu alloy materials such as Cu-Zr alloy, Cu-Fe alloy, and Cu-Cr-Sn-Zr alloy.

The first base material 14 has a first surface 16, a second surface 17 on the opposite side thereof, and a third surface 18 connecting the first surface 16 and the second surface 17. In other words, the first surface 16 of the first base material 14 may be the upper surface, the second surface 17 may be the back surface, and the third surface 18 may be the side surface. Further, the first base material 14 may be, for example, a metal plate having a thickness of 0.15 mm to 0.3 mm.

The first surface plating layer 15 is made of a metal containing Ni as a main component. Here, the "metal containing Ni as a main component" means that the mass ratio (mass%) of Ni constituting the first surface layer plating layer 15 is the highest with respect to other components constituting the first surface layer plating layer 15. It refers to expensive metal. The "metal containing Ni as a main component" may contain a trace amount of impurities (for example, Fe, etc.), but if it contains 99% or more of Ni, it may be referred to as a metal containing Ni as a main component.

In this embodiment, the first surface plating layer 15 covers all of the first surface 16, the second surface 17, and the third surface 18 of the first base material 14. That is, the entire surface of the first base material 14 is covered with the first surface plating layer 15. As a result, the entire surface of the island 2 is formed by the first surface plating layer 15.
In this embodiment, the island 2 has a first surface 19, a second surface 20 on the opposite side thereof, and a third surface 21 connecting the first surface 19 and the second surface 20. In other words, the first surface 19 of the island 2 may be the upper surface, the second surface 20 may be the back surface, and the third surface 21 may be the side surface. All of the first surface 19, the second surface 20, and the third surface 21 of the island 2 are formed by the first surface plating layer 15. Further, the first surface layer plating layer 15 may be, for example, a metal thin film having a thickness of 2 μm to 3 μm.

The arithmetic mean roughness Ra of the first surface 19 of the island 2 having such a layer structure is less than 0.1 μm. More specifically, with reference to FIG. 5, a plurality of convex portions 22 are selectively formed on the first surface 19 of the island 2, and a concave portion 23 is formed between the plurality of convex portions 22. .. The arithmetic average roughness Ra of the first surface 19 of the island 2 on which the concave-convex structure of the convex portion 22 and the concave portion 23 is formed is less than 0.1 μm (the arithmetic average roughness Ra of the surface of the SEM image of FIG. 5 is , 0.085 μm). Further, for example, the convex portion 22 and the concave portion 23 may include the linear convex portion 24 and the linear concave portion 25, or may include the point-shaped convex portion 26 and the point-shaped concave portion 27. ..

With reference to FIG. 3, the lead 3 includes a first lead 28 and a second lead 29 that is different from the first lead 28.
In this embodiment, the first lead 28 is arranged on the first side 6A side of the sealing resin 6. In this embodiment, a pair of first leads 28 that are line-symmetrical with respect to the axis A described above are formed.

Each first lead 28 includes a plurality of first outer leads 30 exposed from the sealing resin 6 and a first inner lead 31 connecting an extension portion of the plurality of first outer leads 30 in the sealing resin 6. .. In this embodiment, the extension portions 32 of the four first outer leads 30 are connected by one first inner lead 31.
The first inner lead 31 extends along the first side 6A of the sealing resin 6 and is formed in a substantially rectangular shape in a plan view. Further, the first inner lead 31 is arranged at a height position separated upward from the island 2. The plurality of first outer leads 30 are arranged at intervals along the long side of the first inner lead 31. Each first outer lead 30 extends in a direction perpendicular to the longitudinal direction of the first inner lead 31. Further, referring to FIGS. 1, 2 and 4A, each of the first outer leads 30 is formed in a crank shape and has a bottom surface (second surface 43) at the same height as the second surface 17 of the island 2. have.

In this embodiment, the second lead 29 is arranged on the second side 6B side of the sealing resin 6. The second lead 29 includes a plurality of second outer leads 33 exposed from the sealing resin 6, and a second inner lead 34 connected one-to-one with each of the second outer leads 33. In this embodiment, a total of eight second leads 29, in which one second outer lead 33 and one second inner lead 34 are integrated, are formed.

With reference to FIG. 3, each second inner lead 34 extends in a direction perpendicular to the second side 6B of the sealing resin 6. The second inner lead 34 has a first portion 35 having a relatively wide width and a width narrower than that of the first portion 35 along the direction perpendicular to the second side 6B of the sealing resin 6. It may have a second portion 36 and.
The first portion 35 and the second portion 36 may be formed one by one, or two or more thereof may be formed. In this embodiment, the first portion 35, the second portion 36, the first portion 35, and the second portion 36 are alternately formed from the end portion of the second inner lead 34 on the side closer to the island 2. The second portion 36 sandwiched between the adjacent first portions 35 is a narrow portion between a pair of wide first portions 35, and may be referred to as a neck portion of the second inner lead 34.

Further, referring to FIG. 4A, the second inner lead 34 is arranged at a height position separated upward from the island 2.
Each of the second outer leads 33 extends integrally with the second inner lead 34 in a direction perpendicular to the second side 6B of the sealing resin 6. Further, referring to FIGS. 1, 2 and 4A, each of the second outer leads 33 is formed in a crank shape and has a bottom surface (second surface 43) at the same height as the second surface 17 of the island 2. have.

Further, in the semiconductor device 1, the leads 3 are not arranged on the third side 6C side and the fourth side 6D side of the sealing resin 6. That is, the side surface of the sealing resin 6 on the third side 6C side (the third surface 62 described later) and the side surface on the fourth side 6D side (the third surface 62 described later) are side surfaces on which the lead 3 does not protrude. There is.
With reference to FIGS. 4A and 4B, the lead 3 includes a second base material 37 and a second surface plating layer 38 formed on the second base material 37.

The second base material 37 is made of a metal containing Cu as a main component. That is, the second base material 37 may be made of the same material as the first base material 14. For example, the coefficient of linear expansion of a metal containing Cu as a main component may be 16 ( ^10-6 / K) to 19 ( ^10-6 / K). Here, the "metal containing Cu as a main component" is a metal in which the mass ratio (mass%) of Cu constituting the second base material 37 is the highest with respect to other components constituting the second base material 37. It means that.

When the second base material 37 is made of a Cu—Sn alloy, the mass ratio R _Cu of _Cu is higher than the mass ratio R _{Sn of Sn} (R _Cu > R _Sn ). The "metal containing Cu as a main component" may contain trace impurities, but high-purity copper having a purity of 99.99999% (6N) or more and high-purity copper having a purity of 99.99% (4N) or more. Etc. are also included. Examples of other Cu alloys include known Cu alloy materials such as Cu-Zr alloys, Cu-Fe alloys, and Cu-Cr-Sn-Zr alloys.

The second base material 37 has a first surface 39, a second surface 40 on the opposite side thereof, and a third surface 41 connecting the first surface 39 and the second surface 40. In other words, the first surface 39 of the second base material 37 may be the upper surface, the second surface 40 may be the back surface, and the third surface 41 may be the side surface. Further, the second base material 37 may be, for example, a metal plate having a thickness of 0.15 mm to 0.3 mm.

The second surface plating layer 38 is made of a metal containing Ni as a main component. Here, the "metal containing Ni as a main component" means that the mass ratio (mass%) of Ni constituting the second surface layer plating layer 38 is the highest with respect to other components constituting the second surface layer plating layer 38. It refers to expensive metal. The "metal containing Ni as a main component" may contain a trace amount of impurities (for example, Fe, etc.), but if it contains 99% or more of Ni, it may be referred to as a metal containing Ni as a main component.

In this embodiment, the second surface plating layer 38 covers all of the first surface 39, the second surface 40, and the third surface 41 of the second base material 37. That is, the entire surface of the second base material 37 is covered with the second surface plating layer 38. As a result, the entire surface of the reed 3 is formed by the second surface plating layer 38.
In this embodiment, the lead 3 has a first surface 42, a second surface 43 on the opposite side thereof, and a third surface 44 connecting the first surface 42 and the second surface 43. In other words, the first surface 42 of the lead 3 may be the upper surface, the second surface 43 may be the back surface, and the third surface 44 may be the side surface. All of the first surface 42, the second surface 43, and the third surface 44 of the lead 3 are formed by the second surface plating layer 38. Further, the second surface plating layer 38 may be, for example, a metal thin film having a thickness of 2 μm to 3 μm.

The arithmetic mean roughness Ra of the first surface 42 of the reed 3 having such a layer structure is less than 0.1 μm. More specifically, similarly to the first surface 19 of the island 2 shown in FIG. 5, a plurality of convex portions 22 are selectively formed on the first surface 42 of the lead 3, and the plurality of convex portions 22 are formed. A recess 23 is formed between them. The arithmetic average roughness Ra of the first surface 42 of the lead 3 on which the concave-convex structure of the convex portion 22 and the concave portion 23 is formed is less than 0.1 μm (the arithmetic average roughness Ra of the surface of the SEM image of FIG. 5 is , 0.085 μm). Further, for example, the convex portion 22 and the concave portion 23 may include the linear convex portion 24 and the linear concave portion 25, or may include the point-shaped convex portion 26 and the point-shaped concave portion 27. ..

The bonding material 4 is formed on the island 2 and is in direct contact with the first surface 19 of the island 2. In this embodiment, the bonding material 4 is made of a metal containing solder as a main component. For example, the coefficient of linear expansion of a metal containing solder as a main component may be 19 ( ^10-6 / K) to 32 ( ^10-6 / K).
Here, the "metal containing solder as a main component" refers to a metal that constitutes the bonding material 4 and has the highest mass ratio (mass%) of solder with respect to other components constituting the bonding material 4. Say. The specific composition of the solder may be, for example, lead-containing solder or lead-free solder. Examples of the lead-containing solder include PbSn, PbSnAg, PbSnBi, PbSnBiIn and the like. Examples of the lead-free solder include AuSn, AgSn, AgSnCu, SnZnBi, SnSbNi, SnZn, SnBi and the like. Further, the bonding material 4 has a thickness T1 of 20 μm to 80 μm.

With reference to FIG. 3, the semiconductor chip 5 is formed in a rectangular shape (rectangular shape) in a plan view. The semiconductor chip 5 has a first side 5A and a second side 5B facing each other, and a third side 5C and a fourth side 5D facing each other. In this embodiment, the first side 5A and the second side 5B are the long sides of the semiconductor chip 5, and the third side 5C and the fourth side 5D are the short sides of the semiconductor chip 5.

The semiconductor chip 5 includes a semiconductor substrate 45, a first electrode 46, a second electrode 47, and a surface protective film 48.
The semiconductor substrate 45 may be, for example, a known semiconductor substrate 45 such as a Si substrate or a SiC substrate. The semiconductor substrate 45 has a first surface 49, a second surface 50 on the opposite side thereof, and a third surface 51 connecting the first surface 49 and the second surface 50. In other words, the first surface 49 of the semiconductor substrate 45 may be the upper surface, the second surface 50 may be the back surface, and the third surface 51 may be the side surface. A semiconductor element such as a MOSFET 52 (switching element) and a protection circuit (not shown) of the MOSFET 52 is formed on the first surface 49 of the semiconductor substrate 45. The MOSFET 52 is a vertical element in which a current flows between the first electrode 46 and the second electrode 47 in the thickness direction of the semiconductor substrate 45.

The first electrode 46 is formed on the second surface 50 of the semiconductor substrate 45, and covers, for example, the entire second surface 50. The first electrode 46 is electrically connected to the MOSFET 52 of the semiconductor substrate 45. The first electrode 46 may be made of, for example, a metal film such as aluminum (including an aluminum alloy). The first electrode 46 may be referred to as a drain electrode of the MOSFET 52 or a back electrode of the semiconductor device 1.

The second electrode 47 is formed on the first surface 49 of the semiconductor substrate 45, for example, via an insulating film such as an interlayer insulating film (not shown). The second electrode 47 may be made of, for example, a metal film such as aluminum (including an aluminum alloy) and may be formed in a predetermined pattern. One of the second electrodes 47 may be referred to as a source electrode of the MOSFET 52 or a surface electrode of the semiconductor device 1. Further, the other second electrode 47 may be referred to as a gate electrode of the MOSFET 52.

The surface protective film 48 covers the second electrode 47. The surface protective film 48 may be, for example, a known insulating film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN). The surface protective film 48 is formed with a first opening 53 and a second opening 54. A part of the second electrode 47 is exposed as the first pad 55 from the first opening 53, and a part of the second electrode 47 is exposed as the second pad 56 from the second opening 54. The first pad 55 and the second pad 56 are separated from each other and are insulated from each other. With reference to FIG. 3, in this embodiment, the first pad 55 has a relatively large area and the second pad 56 has a smaller area than the first pad 55.

The first pad 55 is arranged on the first side 6A side of the sealing resin 6. A plurality of the first pads 55 are arranged at intervals along the first side 6A of the sealing resin 6. In this embodiment, two first pads 55 are arranged. Then, one first pad 55 and one first inner lead 31 are connected by a plurality of first wires 57. The distance between the joints of the plurality of first wires 57 in the first pad 55 is smaller than the distance between the joints of the plurality of first wires 57 in the first inner lead 31.

The second pad 56 is arranged on the second side 6B side of the sealing resin 6. A plurality of second pads 56 are arranged at intervals along the second side 6B of the sealing resin 6. In this embodiment, eight first pads 55 are arranged. Then, one second pad 56 and one second inner lead 34 are connected by one second wire 58.
The first wire 57 and the second wire 58 may be known bonding wires such as Au wire and Cu wire.

The semiconductor chip 5 is arranged on the bonding material 4, and the first electrode 46 is in direct contact with the bonding material 4. Further, referring to FIG. 3, a part of the bonding material 4 that supports the semiconductor chip 5 from the second surface 50 side (back surface side) is seen from only one side or only two sides of the semiconductor chip 5 in a plan view. It's leaking.
In FIG. 3, the leaking portion 59 of the bonding material 4 leaking from the second side 5B and the fourth side 5D of the semiconductor chip 5 is shown. More specifically, the distance L3 between the third side 5C and the fourth side 5D of the semiconductor chip 5 and the third side 2C and the fourth side 2D of the island 2 is the first side 5A and the second side of the semiconductor chip 5. The distance between the side 5B and the first side 2A and the second side 2B of the island 2 is longer than the distance L4. As a result, the leaking portion 59 of the bonding material 4 leaking from the fourth side 5D of the semiconductor chip 5 did not reach the fourth side 2D of the island 2, while leaking from the second side 5B of the semiconductor chip 5. The leaked portion 59 of the joining material 4 reaches the second side 2B of the island 2. Further, as shown by the broken line in FIG. 4A, if the leaking portion 59 of the bonding material 4 leaking from the second side 5B of the semiconductor chip 5 does not reach the second surface 20 of the island 2, the second surface of the island 2 The three sides 21 may be partially covered.

As described above, the reason why the leaked portion 59 of the bonding material 4 is difficult to reach the second surface 20 of the island 2 is that the arithmetic average roughness Ra of the first surface 19 of the island 2 is less than 0.1 μm. This is because the arithmetic mean roughness Ra of the third surface 21 of the island 2 is less than 0.1 μm. As will be described later, the first surface 19 and the third surface 21 of the island 2 are each composed of a first surface plating layer 15 formed by a common plating process. Therefore, even if the leaked portion 59 of the bonding material 4 reaches the second side 2B of the island 2, the capillary phenomenon is suppressed on the third surface 21 of the island 2, and as a result, the bonding material 4 is widened to the second surface 20. Expansion is suppressed.

Further, on the second side 2B of the island 2, the first surface 19 and the third surface 21 of the island 2 intersect. Therefore, when the leaked portion 59 of the bonding material 4 reaches this intersection, the surface tension of the leaked portion 59 suppresses the expansion of the leaked portion 59 to the third surface 21, and the leaked portion 59 Is easier to stay at the intersection. As a result, it becomes difficult for the leaked portion 59 of the bonding material 4 to reach the second surface 20 of the island 2.

The leaked portion 59 of the bonding material 4 may be formed on any of the first side 5A and the third side 5C in addition to the second side 5B and the fourth side 5D of the semiconductor chip 5. It may be formed on any one or two sides of the one side 5A to the fourth side 5D.
The sealing resin 6 is made of a material containing an epoxy resin as a main component. As the epoxy resin, for example, a known sealing resin material can be applied. The sealing resin 6 is formed in a rectangular parallelepiped shape as described above, and has a first surface 60, a second surface 61 on the opposite side thereof, and a third surface 62 connecting the first surface 60 and the second surface 61. have. In other words, the first surface 60 of the sealing resin 6 may be the upper surface, the second surface 61 may be the back surface, and the third surface 62 may be the side surface.

The sealing resin 6 seals the island 2, the lead 3, the bonding material 4, and the semiconductor chip 5 by covering them, and exposes the second surface 20 (back surface) of the island 2 as a back surface terminal. There is. With reference to FIGS. 2, 4A and 4B, in this embodiment, the entire second surface 20 of the island 2 is exposed from the second surface 61 of the sealing resin 6. The second surface 20 of the exposed island 2 is connected to, for example, the wiring constituting the circuit of the mounting board when the semiconductor device 1 is mounted on the mounting board. As a result, the current flowing in the thickness direction of the semiconductor chip 5 is allowed to flow in the vertical direction to the island 2 via the bonding material 4, and further flows from the second surface 20 (back surface) of the island 2 to the wiring on the mounting substrate. Can be done.

Further, the first outer lead 30 and the second outer lead 33 extend in a crank shape from the pair of third surfaces 62 of the sealing resin 6 facing each other.
Next, the operation and effect of the semiconductor device 1 will be described. First, the semiconductor device according to the reference example will be examined.
In the semiconductor device according to the reference example, the surface state of the first surface 64 of the island 63 is as shown in FIG. The arithmetic mean roughness Ra of the first surface 64 of the island 63 having such a layer structure is not less than 0.1 μm. More specifically, a large number of spherical protrusions 65 or particles 66 are scattered over the first surface 64 of the island 63 of the semiconductor device according to the reference example. Therefore, the spherical convex portion 65 and the fine groove 67 (gap) between the particles 66 are stretched over the entire first surface 64 of the island 63, for example, in the shape of a spider web.

That is, on the first surface 64 of the island 63 of the reference example, the dimensions (for example, diameter) of the convex portion 65 and the particles 66 are larger than the dimensions of the convex portion 22 of the semiconductor device 1 described above, while the convex portion 65 and The width of the groove between the particles 66 is much smaller than the width of the recess 23 of the semiconductor device 1. The arithmetic average roughness Ra of the first surface 64 of the island 63 on which the concave-convex structure of the spherical convex portion 65, the particles 66, and the groove 67 of the reference example is formed is not less than 0.1 μm. The arithmetic mean roughness Ra of the surface of the SEM image of FIG. 6 is 0.143 μm. In the structure of such a reference example, the bonding material 4 on the first surface 64 of the island 63 may be widely expanded due to the capillary phenomenon of the spider web-shaped groove 67.

On the other hand, when the arithmetic average roughness Ra of the first surface 19 of the island 2 is less than 0.1 μm as in the semiconductor device 1, the capillary phenomenon can be suppressed, and as a result, the bonding material 4 Can be suppressed from expanding widely. For example, even if the thickness of the bonding material 4 is 20 μm to 80 μm, the leaking portion 59 of the bonding material 4 from the semiconductor chip 5 can be fastened to only one side or only two sides of the semiconductor chip 5. That is, the capillary phenomenon on the first surface 19 of the island 2 is suppressed, and as a result, the bonding material 4 is suppressed from expanding widely.

As a result, the bonding material 4 can be made relatively thick (for example, 20 μm to 80 μm). By making the joint material 4 thicker, the stress generated in the joint material 4 due to the difference in the coefficient of linear expansion between the joint material 4 and the island 2 can be relaxed. As a result, it is possible to suppress the occurrence of cracks in the bonding material 4 due to the stress, and it is possible to suppress an increase in the resistance of the bonding material 4. As a result, a current can be satisfactorily flowed from the semiconductor chip 5 toward the island 2 in the vertical direction.

Further, the entire surface of the reed 3 has an arithmetic mean roughness Ra of less than 0.1 μm due to the second surface plating layer 38. As a result, it is possible to suppress unnecessary catching of the sealing resin 6 on the reed 3. As a result, in the manufacturing process of the semiconductor device 1, for example, it is possible to suppress the generation of burrs of the sealing resin 6 due to the excess sealing resin 6 coming into close contact with the first outer lead 30 and the second outer lead 33. it can. Further, even if burrs are generated, the burrs can be easily removed because the adhesion of the sealing resin 6 to the leads 3 is small.

7A to 7G are diagrams showing a part of the manufacturing process of the semiconductor device 1 in process order. FIG. 8 is a diagram showing a process related to molding of the bonding material 4 by the spanker 71. 7A to 7G show a cross section corresponding to FIG. 4A.
Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 7A to 7G.
First, with reference to FIG. 7A, a lead frame 68 made of a base material containing Cu as a main component is prepared. The lead frame 68 integrally includes an island 2 and a lead 3. In FIG. 7A, the reed 3 (for example, the suspended reed 3) that integrally connects the island 2 and the reed 3 is omitted.

Next, with reference to FIG. 7B, the first surface plating layer 15 and the second surface plating layer 38 are formed on the surfaces of the island 2 and the lead 3. The first surface layer plating layer 15 and the second surface layer plating layer 38 are formed by, for example, an electrolytic plating method, but may be formed by an electroless plating method. Further, as the plating solution, a plating solution made of a metal containing Ni as a main component is used. At this time, by adjusting the composition of the Ni plating solution and the plating conditions (for example, current density, time, etc.), the arithmetic mean roughness Ra of the surfaces of the first surface layer plating layer 15 and the second surface layer plating layer 38 is less than 1 μm. Can be.

Next, referring to FIG. 7C, the thread solder 69 having a predetermined length is melted in the central portion of the island 2. As a result, the molten solder 70 is formed on the island 2. The length L of the thread solder 69 used may be measured, for example, with reference to the first surface 19 of the island 2.
Next, referring to FIG. 7D, the molten solder 70 is formed by using the spanker 71 to form the bonding material 4. In this embodiment, as shown in FIG. 8, the molten solder 70 is formed into a rectangular shape in a plan view using a spanker 71.

Next, referring to FIG. 7E, the semiconductor chip 5 is mounted on the bonding material 4 using, for example, a chip mounter (not shown).
Next, referring to FIG. 7F, the first pad 55 and the first inner lead 31 of the semiconductor chip 5 are connected by the first wire 57, and the second pad 56 and the second inner lead 34 of the semiconductor chip 5 are connected to each other. It is connected by the second wire 58.

Next, with reference to 7G, the island 2, the lead 3, the bonding material 4, and the semiconductor chip 5 are sealed with the sealing resin 6. After that, the above-mentioned semiconductor device 1 is obtained by performing the individualization step.
Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.

For example, the package format of the semiconductor device 1 is not limited to SOP, and may be another surface mount type package format. For example, known semiconductor packages such as SOJ (Small Outline J-leaded Package), SOJ (Small Outline J-leaded Package), QFP (Quad Flat Package), and various similar semiconductor packages may be applied.
Further, if a part of the bonding material 4 leaks from only one side or only two sides of the semiconductor chip 5, the arithmetic average roughness Ra of the first surface 19 of the island 2 is 1 μm or more. May be good. On the contrary, if the arithmetic average roughness Ra of the first surface 19 of the island 2 is less than 1 μm, a part of the bonding material 4 may leak from three or more sides of the semiconductor chip 5.

Further, the element built in the semiconductor chip 5 may be, for example, an IGBT, a bipolar transistor, a diode or the like instead of the MOSFET 52.
In addition, various design changes can be made within the scope of the matters described in the claims.

Next, the present invention will be described with reference to Examples and Reference Examples, but the present invention is not limited to the following Examples.
<Example>
First, a surface plating layer containing Ni as a main component was formed on the entire surface of a lead frame made of a base material containing Cu as a main component by an electrolytic plating method. At this time, the composition of the Ni plating solution and the plating conditions were adjusted so that the arithmetic mean roughness Ra of the surface of the surface plating layer (the first surface 19 of the island 2 described above) was less than 1 μm. The arithmetic mean roughness Ra of the surface of the obtained surface plating layer was 0.085 μm. That is, a surface plating layer having the surface state shown in FIG. 5 was formed.

Next, a predetermined length of thread solder was melted in the central portion of the island 2, and the molten solder was formed into a quadrangular shape using a spanker. Next, the semiconductor chip 5 was mounted on the molten solder with a predetermined pressing force. The predetermined pressing force was defined by the height position of the semiconductor chip 5 with respect to the first surface 19 of the island 2 when the pressing of the semiconductor chip 5 into the molten solder was stopped.

Next, the spread state of the solder after mounting the semiconductor chip 5 was matrix-evaluated. In the matrix evaluation, the pressing force of the semiconductor chip 5 was set in five stages on the vertical axis. On the other hand, on the horizontal axis, the length of the thread solder, that is, the amount of molten solder was set in five stages. The results are shown in FIG. FIG. 9 shows a semiconductor device (sealing resin is omitted) in which the island 2 is viewed from the second surface 20 side.

From FIG. 9, under any of the conditions, the leaked portion 59 of the solder (bonding material) remains on the first surface 19 of the island 2 without wrapping around from the first surface 19 to the second surface 20 (one of the solders). The part has reached the edge of the island 2, but not the second surface 20), but the solder did not leak from the first surface 19 of the island 2. That is, the spread of the solder between the island 2 and the semiconductor chip 5 could be well controlled.
<Reference example>
The semiconductor chip 5 was subjected to the same steps as in Examples except that the arithmetic mean roughness Ra of the surface of the surface plating layer was 0.143 μm (the surface plating layer having the surface state shown in FIG. 6). Mounted on top of molten solder. Then, as in the examples, the spread state of the solder after mounting the semiconductor chip 5 was matrix-evaluated. The results are shown in FIG.

From FIG. 10, under any of the conditions, the leaked portion 72 of the solder (bonding material) spreads over almost the entire first surface 64 of the island 63, and a part wraps around from the first surface 64 to the second surface 73. It was spreading. That is, the spread of the solder between the island 63 and the semiconductor chip 5 could not be controlled well. That is, in the reference example, it is presumed that the molten solder spread due to the capillary phenomenon on the first surface 64 of the island 63.

1 Semiconductor device 2 Island 2A (Island) 1st side 2B (Island) 2nd side 2C (Island) 3rd side 2D (Island) 4th side 3 Lead 4 Bonding material 5 Semiconductor chip 5A (Semiconductor chip) 1st side 5B (Semiconductor chip) 2nd side 5C (Semiconductor chip) 3rd side 5D (Semiconductor chip) 4th side 6 Encapsulating resin 6A (Encapsulating resin) 1st side 6B (Encapsulating resin) 2nd side 6C (Encapsulating resin) ) 3rd side 6D (sealing resin) 4th side 14 1st base material 15 1st surface layer plating layer 16 (1st base material) 1st surface 17 (1st base material) 2nd surface 18 (1st base material) ) 3rd surface 19 (Island) 1st surface 20 (Island) 2nd surface 21 (Island) 3rd surface 28 1st lead 29 2nd lead 30 1st outer lead 31 1st inner lead 32 (1st outer lead) Extension 33 2nd outer lead 34 2nd inner lead 37 2nd base material 38 2nd surface layer plating layer 39 (2nd base material) 1st surface 40 (2nd base material) 2nd surface 41 (2nd base material) 3rd surface 42 (lead) 1st surface 43 (lead) 2nd surface 44 (lead) 3rd surface 46 1st electrode 47 2nd electrode 52 MOSFET
55 1st pad 56 2nd pad 57 1st wire 58 2nd wire 59 (joining material) Leakage part

Claims (18)

A conductive island with a first surface and a second surface on the opposite side,
A conductive bonding material formed on the island and made of a material different from the island,
A semiconductor chip formed on the bonding material and having a first electrode in contact with the bonding material,
The island, the bonding material, and the sealing resin covering the semiconductor chip are included so that the second surface of the island is exposed.
A semiconductor device in which the arithmetic mean roughness Ra of the first surface of the island is less than 0.1 μm. The semiconductor device according to claim 1, wherein the thickness of the bonding material is 20 μm to 80 μm. The semiconductor chip is formed in a rectangular shape in a plan view.
The semiconductor device according to claim 1 or 2, wherein a part of the bonding material leaks from only one side or only two sides of the semiconductor chip in a plan view. A conductive island with a first surface and a second surface on the opposite side,
A conductive bonding material formed on the island, having a thickness of 20 μm to 80 μm, and made of a material different from that of the island.
A semiconductor chip formed on the bonding material, having a first electrode in contact with the bonding material, and formed in a rectangular shape in a plan view.
The island, the bonding material, and the sealing resin covering the semiconductor chip are included so that the second surface of the island is exposed.
A semiconductor device in which a part of the bonding material leaks from only one side or only two sides of the semiconductor chip in a plan view. The semiconductor device according to claim 3 or 4, wherein the portion of the bonding material leaking from the semiconductor chip does not reach the edge of the island. The semiconductor device according to claim 3 or 4, wherein the portion of the bonding material leaking from the semiconductor chip reaches the edge of the island and does not reach the second surface of the island. The island has a third surface that connects the first surface and the second surface of the island.
The semiconductor device according to claim 6, wherein the portion of the bonding material leaking from the semiconductor chip reaches the first surface to the third surface of the island. The island includes a first base material made of a metal containing Cu as a main component and a first surface plating layer made of a metal containing Ni as a main component formed on the first base material.
The semiconductor device according to any one of claims 1 to 7, wherein the first surface plating layer forms the first surface of the island. The island includes a first base material made of a metal containing Cu as a main component and a first surface plating layer made of a metal containing Ni as a main component formed on the first base material.
The first surface plating layer forms the first surface of the island.
The semiconductor device according to any one of claims 1 to 7, wherein the bonding material is made of a metal containing solder as a main component. The first base material has a first surface, a second surface on the opposite side thereof, and a third surface connecting the first surface and the second surface.
The semiconductor device according to claim 8 or 9, wherein the first surface plating layer covers all of the first surface, the second surface, and the third surface of the first base material. The semiconductor chip includes a second electrode formed on the opposite side of the first electrode in the thickness direction of the semiconductor chip.
The semiconductor device is
A reed that is separated from the island and has a first surface and a second surface on the opposite side.
Includes a wire connecting the lead and the second electrode.
The semiconductor device according to any one of claims 1 to 10, wherein the arithmetic average roughness Ra of the first surface of the lead is less than 0.1 μm. The lead includes a second base material made of a metal containing Cu as a main component and a second surface plating layer made of a metal containing Ni as a main component formed on the second base material.
The semiconductor device according to claim 11, wherein the second surface plating layer forms the first surface of the reed. The second base material has a first surface, a second surface on the opposite side thereof, and a third surface connecting the first surface and the second surface.
The semiconductor device according to claim 12, wherein the second surface plating layer covers all of the first surface, the second surface, and the third surface of the second base material. The lead includes a first lead and a second lead different from the first lead.
The first reed includes a plurality of first outer reeds exposed from the sealing resin and a first inner reed connecting an extension portion of the plurality of first outer leads in the sealing resin.
The second leads include a plurality of second outer reeds exposed from the sealing resin and second inner reeds connected one-to-one with each of the second outer reeds, claims 11 to 13. The semiconductor device according to any one of the above. The sealing resin is formed in a rectangular shape in a plan view.
The first lead is arranged on the first side side of the sealing resin.
The semiconductor device according to claim 14, wherein the second lead is arranged on the second side of the sealing resin facing the first side. The semiconductor device according to claim 15, wherein the leads are not arranged on the third side of the sealing resin and the fourth side facing the third side. The second electrode of the semiconductor chip includes a relatively large first pad and a second pad having an area smaller than that of the first pad.
The wire is a plurality of first wires connecting one first pad and one first inner lead, and one wire connecting one second pad and one second inner lead. The semiconductor device according to any one of claims 14 to 16, which includes a second wire. The semiconductor device according to any one of claims 1 to 17, wherein the sealing resin is made of a material containing an epoxy resin as a main component.