JP2022027162A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2022027162A
JP2022027162A JP2020130991A JP2020130991A JP2022027162A JP 2022027162 A JP2022027162 A JP 2022027162A JP 2020130991 A JP2020130991 A JP 2020130991A JP 2020130991 A JP2020130991 A JP 2020130991A JP 2022027162 A JP2022027162 A JP 2022027162A
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solder
bonding electrode
electrode
wire bonding
semiconductor device
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充季 川野
Mitsuki Kawano
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a semiconductor device that includes electrodes for solder bonding and electrodes for wire bonding and suppresses solder adhesion to the electrodes for wire bonding.SOLUTION: Of an insulating layer 15, which covers a part of a solder bonding electrode 16 and a wire bonding electrode 17, a groove 151 separating them is provided between the solder bonding electrode 16 and the wire bonding electrode 17. As a result, when another component is soldered to the solder bonding electrode 16, even if a portion of the molten solder spreads outside the area of the solder bonding electrode 16 or flies away, it is caught by the grooves 151, which prevents the solder from adhering to the wire bonding electrodes 17.SELECTED DRAWING: Figure 2

Description

本発明は、はんだ接合用の電極とワイヤ接合用の電極とを備える半導体装置に関する。 The present invention relates to a semiconductor device including an electrode for solder bonding and an electrode for wire bonding.

従来、この種の半導体装置としては、例えば特許文献１に記載のものが挙げられる。特許文献１に記載の半導体装置は、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のデバイスが形成された半導体チップと、半導体チップの一面に形成されたはんだ接合用電極およびワイヤ接合用電極とを備える。この半導体装置は、例えば、はんだ接合用電極にはんだを介して銅などによりなるブロック体が接続され、ワイヤ接合用電極には金属ワイヤが接合されると共に、リードフレームと電気的に接続される。そして、この半導体装置は、半導体チップの他面およびブロック体それぞれにはんだを介して金属放熱板が接続されることで、両面放熱構造の半導体モジュールを構成する。 Conventionally, examples of this type of semiconductor device include those described in Patent Document 1. The semiconductor device described in Patent Document 1 includes a semiconductor chip on which a device such as an insulated gate bipolar transistor (IGBT) is formed, and a solder bonding electrode and a wire bonding electrode formed on one surface of the semiconductor chip. In this semiconductor device, for example, a block body made of copper or the like is connected to a solder bonding electrode via solder, and a metal wire is bonded to the wire bonding electrode and electrically connected to a lead frame. Then, this semiconductor device constitutes a semiconductor module having a double-sided heat dissipation structure by connecting a metal heat sink to each of the other surface of the semiconductor chip and the block body via solder.

特開２０１８－１６０６５３号公報Japanese Unexamined Patent Publication No. 2018-160653

上記の半導体モジュールを製造する際、金属放熱板に半導体チップの他面側を接合して搭載し、治具により位置合わせをした後、半導体チップのはんだ接合用電極にブロック体のはんだ接合をする。その後、半導体チップのワイヤ接合用電極とリードフレームとをワイヤボンディングにより接続し、ブロック体にもう１つの金属放熱板をはんだ接合した後、モールド樹脂を形成する。 When manufacturing the above semiconductor module, the other side of the semiconductor chip is bonded to the metal heat sink, mounted, aligned with a jig, and then the block is solder-bonded to the solder-bonding electrode of the semiconductor chip. .. After that, the wire bonding electrode of the semiconductor chip and the lead frame are connected by wire bonding, another metal heat dissipation plate is solder-bonded to the block body, and then a mold resin is formed.

しかしながら、はんだ接合においては、溶融したはんだの余剰部分が意図しない領域にまで濡れ広がったり、はんだ内部に存在する気泡等により溶融したはんだの一部が意図しない領域に飛散する、いわゆるはんだ飛びが生じたりすることがある。この場合、半導体チップの同一面にはんだ接合用電極およびワイヤ接合用電極を有する半導体装置では、はんだ接合によってワイヤ接合用電極にはんだが付着し、接合不良が生じるおそれがある。 However, in solder bonding, so-called solder skipping occurs in which the excess portion of the molten solder gets wet and spreads to an unintended region, or a part of the molten solder scatters to an unintended region due to air bubbles or the like existing inside the solder. It may happen. In this case, in a semiconductor device having a solder bonding electrode and a wire bonding electrode on the same surface of the semiconductor chip, solder may adhere to the wire bonding electrode due to solder bonding, resulting in poor bonding.

本発明は、上記の点に鑑み、はんだ接合用電極およびワイヤ接合用電極を備える半導体装置において、はんだ接合用電極に他の部材をはんだ接合した場合であっても、ワイヤ接合用電極へのはんだ付着およびこれによるワイヤ接合不良を抑制することを目的とする。 In view of the above points, the present invention relates to a semiconductor device provided with an electrode for solder bonding and an electrode for wire bonding, and even when another member is solder-bonded to the electrode for solder bonding, soldering to the electrode for wire bonding is performed. The purpose is to suppress adhesion and wire bonding failure due to this.

上記目的を達成するため、請求項１に記載の半導体装置は、半導体素子（１１）と、半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、一面の側に設けられ、絶縁層から一部が露出するはんだ接合用電極（１６）と、一面の側に設けられ、絶縁層から一部が露出するワイヤ接合用電極（１７）と、絶縁層のうちはんだ接合用電極とワイヤ接合用電極との間に配置される溝部（１５１）と、を備える。 In order to achieve the above object, the semiconductor device according to claim 1 is provided with a semiconductor element (11), an insulating layer (15) provided on one surface (11a) of the semiconductor element, and an insulating layer provided on one surface side. A solder bonding electrode (16) partially exposed from the surface, a wire bonding electrode (17) provided on one side and partially exposed from the insulating layer, and a solder bonding electrode and wire bonding of the insulating layer. A groove portion (151) arranged between the electrode and the electrode is provided.

これによれば、絶縁層のうちはんだ接合用電極とワイヤ接合用電極との間に溝部を備え、はんだ接合用電極へのはんだ接合の際に、溶融したはんだの一部が濡れ広がったり、飛んだりしても溝部により受け止められる構成の半導体装置となる。そのため、ワイヤ接合電極へのはんだ付着が抑制され、ワイヤ接合が安定する効果が得られる。 According to this, a groove is provided between the solder bonding electrode and the wire bonding electrode in the insulating layer, and when soldering to the solder bonding electrode, a part of the molten solder gets wet and spreads or flies. It is a semiconductor device with a structure that can be received by the groove even if it is soldered. Therefore, the adhesion of solder to the wire bonding electrode is suppressed, and the effect of stabilizing the wire bonding can be obtained.

請求項５に記載の半導体装置は、半導体素子（１１）と、半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、一面の側に設けられ、絶縁層から一部が露出するはんだ接合用電極（１６）と、一面の側に設けられ、絶縁層から一部が露出するワイヤ接合用電極（１７）と、絶縁層のうちはんだ接合用電極とワイヤ接合用電極との間の領域に配置される凸部（１５２）と、を備える。 The semiconductor device according to claim 5 includes a semiconductor element (11), an insulating layer (15) provided on one surface (11a) of the semiconductor element, and a solder provided on one surface side and partially exposed from the insulating layer. A bonding electrode (16), a wire bonding electrode (17) provided on one side and partially exposed from the insulating layer, and a region of the insulating layer between the solder bonding electrode and the wire bonding electrode. It comprises a convex portion (152) arranged in.

これによれば、絶縁層のうちはんだ接合用電極とワイヤ接合用電極との間の領域に凸部を備え、はんだ接合用電極へのはんだ接合の際、溶融したはんだの一部が凸部によりせき止められる構造の半導体装置となる。そのため、ワイヤ接合電極へのはんだ付着が抑制され、ワイヤ接合が安定する効果が得られる。 According to this, a convex portion is provided in the region of the insulating layer between the solder bonding electrode and the wire bonding electrode, and when soldering to the solder bonding electrode, a part of the molten solder is formed by the convex portion. It is a semiconductor device with a dammed structure. Therefore, the adhesion of solder to the wire bonding electrode is suppressed, and the effect of stabilizing the wire bonding can be obtained.

請求項６に記載の半導体装置は、半導体素子（１１）と、半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、一面の側に設けられ、絶縁層から一部が露出するはんだ接合用電極（１６）と、一面の側に設けられ、絶縁層から一部が露出するワイヤ接合用電極（１７）と、を備え、はんだ接合用電極は、他の部材とのはんだ接合に用いられる領域である接合部（１６１）と、はんだ接合の際に溶融したはんだの一部を受け止めるための領域であるはんだ受け部（１６２）とを有してなり、はんだ受け部は、接合部から外部に向けて突出している。 The semiconductor device according to claim 6 is a solder provided on the semiconductor element (11), an insulating layer (15) provided on one surface (11a) of the semiconductor element, and a part exposed from the insulating layer. It includes a bonding electrode (16) and a wire bonding electrode (17) provided on one side and partially exposed from the insulating layer, and the solder bonding electrode is used for solder bonding with other members. It has a joint portion (161), which is a region to be soldered, and a solder receiving portion (162), which is a region for receiving a part of the solder melted during solder joining, and the solder receiving portion is formed from the joint portion. It protrudes toward the outside.

これによれば、はんだ接合用電極がはんだ接合用の領域の接合部と溶融したはんだの一部を受け止めるためのはんだ受け部とを有し、はんだ接合用電極へのはんだ接合の際に、溶融したはんだの一部がはんだ受け部に流れ込む構成の半導体装置となる。はんだ受け部にはんだの一部が流れ込む結果、ワイヤ接合用電極に余剰なはんだが付着することが抑制され、ワイヤ接合電極におけるワイヤ接合が安定する効果が得られる。 According to this, the solder bonding electrode has a joint portion in the solder bonding region and a solder receiving portion for receiving a part of the molten solder, and is melted at the time of solder bonding to the solder bonding electrode. It is a semiconductor device with a structure in which a part of the solder that has been soldered flows into the solder receiving portion. As a result of a part of the solder flowing into the solder receiving portion, excess solder is suppressed from adhering to the wire bonding electrode, and the effect of stabilizing the wire bonding at the wire bonding electrode can be obtained.

なお、各構成要素等に付された括弧付きの参照符号は、その構成要素等と後述する実施形態に記載の具体的な構成要素等との対応関係の一例を示すものである。 The reference numerals in parentheses attached to each component or the like indicate an example of the correspondence between the component or the like and the specific component or the like described in the embodiment described later.

第１実施形態の半導体装置の構成例を示す断面図である。It is sectional drawing which shows the structural example of the semiconductor device of 1st Embodiment. 第１実施形態の半導体装置のうちはんだ接合用電極およびワイヤ接合用電極が形成された一面を示す上面レイアウト図である。It is a top layout view which shows one surface which formed the electrode for solder bonding and the electrode for wire bonding in the semiconductor device of 1st Embodiment. 図１のIII領域を拡大して示す拡大断面図である。FIG. 3 is an enlarged cross-sectional view showing an enlarged region III of FIG. 1. 第１実施形態の半導体装置を用いて構成された半導体モジュールの一例を示す断面図である。It is sectional drawing which shows an example of the semiconductor module configured by using the semiconductor device of 1st Embodiment. 第１実施形態の半導体装置を用いて構成された半導体モジュールの他の一例を示す断面図である。It is sectional drawing which shows the other example of the semiconductor module configured by using the semiconductor device of 1st Embodiment. 第２実施形態の半導体装置のうちはんだ接合用電極およびワイヤ接合用電極が形成された一面を示す上面レイアウト図である。FIG. 3 is a top layout view showing one side of the semiconductor device of the second embodiment in which the solder bonding electrode and the wire bonding electrode are formed. 第３実施形態の半導体装置のうちはんだ接合用電極およびワイヤ接合用電極が形成された一面を示す上面レイアウト図である。FIG. 3 is a top layout view showing one side of the semiconductor device of the third embodiment in which the solder bonding electrode and the wire bonding electrode are formed. 第４実施形態の半導体装置のうちはんだ接合用電極およびワイヤ接合用電極が形成された一面を示す上面レイアウト図である。FIG. 3 is a top layout view showing one side of the semiconductor device of the fourth embodiment in which the solder bonding electrode and the wire bonding electrode are formed. 図８のIX-IX間の断面を示す断面図である。It is sectional drawing which shows the cross section between IX and IX of FIG. 凸部の厚み方向における寸法について説明するための説明図である。It is explanatory drawing for demonstrating the dimension in the thickness direction of a convex portion. 第４実施形態の半導体装置の変形例を示す上面レイアウト図である。It is a top layout view which shows the modification of the semiconductor device of 4th Embodiment.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, the parts that are the same or equal to each other will be described with the same reference numerals.

（第１実施形態）
第１実施形態の半導体装置１について、図１～図３を参照して説明する。図１は、図２のI-I間の断面を示す断面図である。 (First Embodiment)
The semiconductor device 1 of the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a cross-sectional view showing a cross section between II of FIG.

〔半導体装置の構成〕
本実施形態の半導体装置１は、例えば図１に示すように、表裏の関係にある一面１１ａおよび他面１１ｂを有する板状の半導体素子１１と、一面１１ａの側に形成されたはんだ接合用電極１６と、ワイヤ接合用電極１７と、を備える。半導体装置１は、はんだ接合用電極１６およびワイヤ接合用電極１７の一部が絶縁層１５により覆われると共に、絶縁層１５のうちこれらの電極の間に溝部１５１が設けられている。半導体装置１は、はんだ接合用電極１６へのはんだ接合の際、溶融したはんだの一部がはんだ接合用電極１６の領域の外に流れ出した、あるいは飛散した場合に、溝部１５１が当該はんだの一部を受け止める構成となっている。 [Semiconductor device configuration]
As shown in FIG. 1, for example, the semiconductor device 1 of the present embodiment includes a plate-shaped semiconductor element 11 having one side surface 11a and another side surface 11b, which are in a front-to-back relationship, and a solder bonding electrode formed on the side of the one side surface 11a. A 16 and a wire bonding electrode 17 are provided. In the semiconductor device 1, a part of the solder bonding electrode 16 and the wire bonding electrode 17 is covered with the insulating layer 15, and a groove portion 151 is provided between these electrodes in the insulating layer 15. In the semiconductor device 1, when a part of the molten solder flows out of the region of the solder bonding electrode 16 or is scattered at the time of solder bonding to the solder bonding electrode 16, the groove portion 151 is one of the solders. It is structured to receive the part.

半導体素子１１は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistorの略）やパワーＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field Effect Transistorの略）などのパワー素子とされ、公知の半導体素子の製造プロセスにより製造される。半導体素子１１は、例えば、一面１１ａに第１電極パッド１２および第２電極パッド１３を有し、他面１１ｂに第３電極パッド１４を有してなる。 The semiconductor element 11 is a power element such as an IGBT (abbreviation of Insulated Gate Bipolar Transistor) or a power MOSFET (abbreviation of Metal-Oxide-Semiconductor Field Effect Transistor), and is manufactured by a known semiconductor element manufacturing process. The semiconductor element 11 has, for example, a first electrode pad 12 and a second electrode pad 13 on one surface 11a, and a third electrode pad 14 on the other surface 11b.

電極パッド１２～１４は、例えば、Ａｌ（アルミニウム）、あるいはＡｌ－Ｓｉ（シリコン）金属やＡｌ－Ｃｕ（銅）等の合金で構成され、蒸着やスパッタリング等の任意の真空成膜法により形成される。例えば、第１電極パッド１２および第３電極パッド１４は、対をなす電極であり、それぞれエミッタ電極、コレクタ電極とされる。第２電極パッド１３は、例えば、一面１１ａ側に複数形成され、ゲート電極や信号伝送用の電極として機能する。電極パッド１２、１３は、例えば、図１に示すように、一部が絶縁層１５により覆われると共に、絶縁層１５から露出する部分がはんだ接合用電極１６またはワイヤ接合用電極１７により覆われている。 The electrode pads 12 to 14 are made of, for example, an alloy such as Al (aluminum), Al—Si (silicon) metal, or Al—Cu (copper), and are formed by an arbitrary vacuum film forming method such as thin film deposition or sputtering. Ru. For example, the first electrode pad 12 and the third electrode pad 14 are paired electrodes, and are an emitter electrode and a collector electrode, respectively. A plurality of second electrode pads 13 are formed on one side 11a, for example, and function as a gate electrode or an electrode for signal transmission. As shown in FIG. 1, for example, the electrode pads 12 and 13 are partially covered with the insulating layer 15, and the portion exposed from the insulating layer 15 is covered with the solder bonding electrode 16 or the wire bonding electrode 17. There is.

絶縁層１５は、例えば、ポリイミドやポリアミド等の任意の絶縁性の樹脂材料により構成され、スピンコート法等の任意の湿式成膜法により形成される。絶縁層１５は、例えば、フォトリソグラフィエッチング法等により、電極パッド１２、１３の一部を露出させる任意のパターン形状とされる。絶縁層１５は、例えば図１に示すように、第１電極パッド１２の一部を覆うはんだ接合用電極１６と第２電極パッド１３の一部を覆うワイヤ接合用電極１７との間に溝部１５１を備える。 The insulating layer 15 is made of an arbitrary insulating resin material such as polyimide or polyamide, and is formed by an arbitrary wet film forming method such as a spin coating method. The insulating layer 15 has an arbitrary pattern shape that exposes a part of the electrode pads 12 and 13 by, for example, a photolithography etching method. As shown in FIG. 1, for example, the insulating layer 15 has a groove portion 151 between the solder bonding electrode 16 that covers a part of the first electrode pad 12 and the wire bonding electrode 17 that covers a part of the second electrode pad 13. To prepare for.

溝部１５１は、例えば、図１に示すように、第１電極パッド１２のうち第２電極パッド１３に隣接する端部近傍の上に形成され、第１電極パッド１２の一部を絶縁層１５から露出させる構成となっている。溝部１５１は、後述するはんだ接合用電極１６へのはんだ接合に際して、溶融したはんだの一部がはんだ接合用電極１６の領域外であって、ワイヤ接合用電極１７側にはみ出した、あるいは飛散した際に、当該はんだの一部を受け止める役割を果たす。溝部１５１は、例えば、図２に示すように、はんだ接合用電極１６と複数のワイヤ接合用電極１７との間であって、はんだ接合用電極１６とすべてのワイヤ接合用電極１７とを隔てるように形成される。言い換えると、複数のワイヤ接合用電極１７が配列された方向を配列方向として、溝部１５１は、例えば、配列方向における幅が、配列方向の両端に位置する２つのワイヤ接合用電極１７同士の距離にこれらの電極１７の幅を合わせた幅以上とされる。溝部１５１には、例えば図３に示すように、絶縁層１５から露出した第１電極パッド１２の一部を覆うダミー層１８が形成されている。 As shown in FIG. 1, the groove portion 151 is formed on the vicinity of the end portion of the first electrode pad 12 adjacent to the second electrode pad 13, and a part of the first electrode pad 12 is formed from the insulating layer 15. It is configured to be exposed. When the groove portion 151 is part of the molten solder outside the region of the solder bonding electrode 16 and protrudes or scatters on the wire bonding electrode 17 side during solder bonding to the solder bonding electrode 16 described later. In addition, it plays a role of receiving a part of the solder. As shown in FIG. 2, the groove portion 151 is between the solder bonding electrode 16 and the plurality of wire bonding electrodes 17, and separates the solder bonding electrode 16 from all the wire bonding electrodes 17. Formed in. In other words, with the direction in which the plurality of wire bonding electrodes 17 are arranged as the arrangement direction, the groove portion 151 has, for example, the width in the arrangement direction the distance between the two wire bonding electrodes 17 located at both ends in the arrangement direction. It is set to be equal to or larger than the combined width of these electrodes 17. As shown in FIG. 3, for example, the groove portion 151 is formed with a dummy layer 18 that covers a part of the first electrode pad 12 exposed from the insulating layer 15.

はんだ接合用電極１６は、はんだを介して他の部材を接合するために用いられる電極である。はんだ接合用電極１６は、例えば図２に示すように、１つ形成され、ワイヤ接合用電極１７よりも大きいサイズとされる。 The solder bonding electrode 16 is an electrode used for bonding other members via solder. As shown in FIG. 2, for example, one solder bonding electrode 16 is formed and has a size larger than that of the wire bonding electrode 17.

ワイヤ接合用電極１７は、例えば、第２電極パッド１３と同数とされ、第２電極パッド１３が複数の場合、図２に示すように、複数個設けられる。ワイヤ接合用電極１７は、例えば、Ａｕ（金）等によりなるワイヤがワイヤボンディングにより接続され、他の部材との信号伝送に用いられる。 For example, the number of wire bonding electrodes 17 is the same as that of the second electrode pads 13, and when there are a plurality of second electrode pads 13, a plurality of the second electrode pads 13 are provided as shown in FIG. The wire bonding electrode 17 is used for signal transmission with other members, for example, a wire made of Au (gold) or the like is connected by wire bonding.

ダミー層１８は、例えば、はんだ接合用電極１６およびワイヤ接合用電極１７と同時に形成され、はんだ接合用電極１６から溢れたはんだを受け止め、当該はんだがワイヤ接合用電極１７に向かうことを妨げる役割を果たす。ダミー層１８は、少なくとも絶縁層１５よりもはんだの濡れ性が高い材料、例えば、Ｎｉ（ニッケル）やＡｕなどにより構成されるが、これらに限定されるものではない。 The dummy layer 18 is formed at the same time as, for example, the solder bonding electrode 16 and the wire bonding electrode 17, and has a role of receiving the solder overflowing from the solder bonding electrode 16 and preventing the solder from heading toward the wire bonding electrode 17. Fulfill. The dummy layer 18 is made of, at least, a material having a higher solder wettability than the insulating layer 15, such as Ni (nickel) and Au, but is not limited thereto.

なお、はんだ接合用電極１６、ワイヤ接合用電極１７およびダミー層１８は、すべて同じ導電性材料により構成され得る。この場合、電極１６、１７およびダミー層１８は、例えば、ＮｉやＡｕ等のはんだの濡れ性が高く、かつワイヤ接合が可能な材料により構成され、電解めっきにより同時に形成される。また、この場合、ダミー層１８は、「ダミー電極」とも称され得る。電極１６、１７およびダミー層１８は、それぞれ異なる材料で構成されてもよく、その場合には、それぞれ別工程により形成される。 The solder bonding electrode 16, the wire bonding electrode 17, and the dummy layer 18 may all be made of the same conductive material. In this case, the electrodes 16 and 17 and the dummy layer 18 are made of a material such as Ni or Au, which has high wettability of solder and can be wire-bonded, and are simultaneously formed by electrolytic plating. Further, in this case, the dummy layer 18 may also be referred to as a “dummy electrode”. The electrodes 16 and 17 and the dummy layer 18 may be made of different materials, and in that case, they are formed by different steps.

また、はんだ接合用電極１６とワイヤ接合用電極１７との配置については、図２に示す例に限定されるものではなく、適宜変更され得る。さらに、溝部１５１は、はんだ接合用電極１６とワイヤ接合用電極１７との間に位置すればよく、これらの電極の配置に応じて位置や形状等が適宜変更され得る。 Further, the arrangement of the solder bonding electrode 16 and the wire bonding electrode 17 is not limited to the example shown in FIG. 2, and may be changed as appropriate. Further, the groove portion 151 may be located between the solder bonding electrode 16 and the wire bonding electrode 17, and the position, shape, and the like can be appropriately changed according to the arrangement of these electrodes.

以上が、本実施形態の半導体装置１の基本的な構成である。 The above is the basic configuration of the semiconductor device 1 of the present embodiment.

〔半導体モジュールの構成例〕
次に、本実施形態の半導体装置１を用いて構成される半導体モジュールの例について、図４、図５を参照して説明する。図４、図５では、見易くするため、後述するモールド樹脂８についてはその外郭のみを示すと共に、当該外郭を二点鎖線で示している。 [Semiconductor module configuration example]
Next, an example of a semiconductor module configured by using the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 4 and 5. In FIGS. 4 and 5, for easy viewing, only the outer shell of the mold resin 8 described later is shown, and the outer shell is shown by a two-dot chain line.

半導体装置１は、例えば図４に示すように、はんだ接合用電極１６側の面側に第２金属放熱板７が、その反対面側に第１金属放熱板２がそれぞれ接合され、両面放熱構造の半導体モジュールを構成するために用いられ得る。この場合、半導体モジュールは、例えば図４に示すように、半導体装置１と、第１金属放熱板２と、接合用のはんだ３と、リードフレーム４と、ブロック体５と、ワイヤ６と、第２金属放熱板７と、モールド樹脂８とを備えた構成とされ得る。 As shown in FIG. 4, for example, the semiconductor device 1 has a double-sided heat dissipation structure in which a second metal heat sink 7 is bonded to the surface side of the solder bonding electrode 16 side and a first metal heat sink 2 is bonded to the opposite surface side thereof. It can be used to construct a semiconductor module of. In this case, as shown in FIG. 4, for example, the semiconductor module includes a semiconductor device 1, a first metal heat sink 2, a solder for joining 3, a lead frame 4, a block body 5, a wire 6, and a second. 2 The configuration may include a metal heat sink 7 and a mold resin 8.

この半導体モジュールは、半導体装置１のうちはんだ接合用電極１６とは反対側の面が第１金属放熱板２の上面２ａにはんだ３を介して搭載されている。この半導体モジュールは、半導体装置１のはんだ接合用電極１６にブロック体５の一面がはんだ３を介して接合されると共に、ブロック体５の一面とは反対側の他面にはんだ３を介して第２金属放熱板７の下面７ｂが接合されている。この半導体モジュールは、例えば、第１金属放熱板２の下面２ｂおよび第２金属放熱板７の上面７ａがそれぞれモールド樹脂８から露出しており、金属放熱板２、７を介して半導体装置１の熱を外部に逃がすことが可能な構成とされる。ワイヤ接合用電極１７は、Ａｕ等の導電性の良い金属材料等によりなるワイヤ６が接合され、ワイヤ６を介してリードフレーム４と電気的に接続される。 In this semiconductor module, the surface of the semiconductor device 1 opposite to the solder bonding electrode 16 is mounted on the upper surface 2a of the first metal heat sink 2 via the solder 3. In this semiconductor module, one surface of the block body 5 is bonded to the solder bonding electrode 16 of the semiconductor device 1 via the solder 3, and the other surface on the opposite side of the block body 5 is bonded via the solder 3. 2 The lower surface 7b of the metal radiator plate 7 is joined. In this semiconductor module, for example, the lower surface 2b of the first metal heat sink 2 and the upper surface 7a of the second metal heat sink 7 are exposed from the mold resin 8, respectively, and the semiconductor device 1 is connected to the semiconductor device 1 via the metal heat sinks 2 and 7. It is configured to allow heat to escape to the outside. The wire bonding electrode 17 is bonded to a wire 6 made of a metal material having good conductivity such as Au, and is electrically connected to the lead frame 4 via the wire 6.

なお、金属放熱板２、７およびブロック体５は、例えば、熱伝導性が高いＣｕ等の金属材料により構成される。リードフレーム４は、例えば、ＣｕやＦｅ（鉄）等の任意の導電性材料により構成される。リードフレーム４は、金属放熱板２、７とは別に用意されてもよいし、第１金属放熱板２または第２金属放熱板７と一体で構成され、プレス打ち抜き加工等により図示しない連結部分を切断することで、後ほど金属放熱板２、７から分離した状態とされてもよい。モールド樹脂８は、例えば、エポキシ樹脂等の任意の絶縁性樹脂材料により構成され、コンプレッション成形等の任意の樹脂成形法により形成される。 The metal heat sinks 2 and 7 and the block body 5 are made of, for example, a metal material such as Cu having high thermal conductivity. The lead frame 4 is made of any conductive material such as Cu or Fe (iron). The lead frame 4 may be prepared separately from the metal heat sinks 2 and 7, or may be integrally formed with the first metal heat sink 2 or the second metal heat sink 7, and a connecting portion (not shown) may be formed by press punching or the like. By cutting it, it may be separated from the metal heat sinks 2 and 7 later. The mold resin 8 is made of an arbitrary insulating resin material such as an epoxy resin, and is formed by an arbitrary resin molding method such as compression molding.

この半導体モジュールは、例えば、次のように製造される。 This semiconductor module is manufactured, for example, as follows.

まず、第１金属放熱板２の上面２ａに半導体装置１をはんだ接合した後、はんだ接合用電極１６にはんだ３を塗布する。続けて、例えば、図示しない位置合わせ治具等を用いて、はんだ接合用電極１６の上にブロック体５を配置し、はんだ接合を行う。このとき、はんだ接合用電極１６とワイヤ接合用電極１７との間に溝部１５１および溝部１５１に形成されたダミー層１８が存在するため、はんだ接合用電極１６から溶融したはんだ３の一部が溢れたり、飛んだりしたとしても、溝部１５１にて受け止められる。その結果、ワイヤ接合用電極１７にはんだ３の一部が付着することが抑制される。 First, the semiconductor device 1 is solder-bonded to the upper surface 2a of the first metal heat sink 2, and then the solder 3 is applied to the solder-bonding electrode 16. Subsequently, for example, using a positioning jig (not shown) or the like, the block body 5 is arranged on the solder bonding electrode 16 and solder bonding is performed. At this time, since the dummy layer 18 formed in the groove portion 151 and the groove portion 151 exists between the solder bonding electrode 16 and the wire bonding electrode 17, a part of the solder 3 melted from the solder bonding electrode 16 overflows. Even if it flies or flies, it is received by the groove 151. As a result, it is suppressed that a part of the solder 3 adheres to the wire bonding electrode 17.

その後、図示しない位置合わせ治具を取り除き、リードフレーム４およびはんだ接合用電極１７のそれぞれにワイヤボンディングによりワイヤ６を接合し、ワイヤ６を介してこれらを電気的に接続する。そして、ブロック体５の他面にはんだ３を介して第２金属放熱板７を接合した後、モールド樹脂８の外形に沿ったキャビティを有する図示しない金型を用い、コンプレッション成形等によりモールド樹脂８を形成する。 After that, the alignment jig (not shown) is removed, the wire 6 is bonded to each of the lead frame 4 and the solder bonding electrode 17 by wire bonding, and these are electrically connected via the wire 6. Then, after joining the second metal heat sink 7 to the other surface of the block body 5 via the solder 3, the mold resin 8 is formed by compression molding or the like using a mold (not shown) having a cavity along the outer shape of the mold resin 8. To form.

この両面放熱構造の半導体モジュールは、半導体装置１を用いることにより、ワイヤ接合用電極１７におけるワイヤ接合が安定するため、ワイヤ接合の信頼性が高い構造となる。 By using the semiconductor device 1, the semiconductor module having this double-sided heat dissipation structure has a structure in which the wire bonding at the wire bonding electrode 17 is stable, so that the wire bonding is highly reliable.

また、半導体装置１は、他の部材とのはんだ接合およびワイヤ接合が同じ面で行われるものであれば適用可能であり、例えば図５に示す半導体モジュールに用いられてもよい。 Further, the semiconductor device 1 is applicable as long as it is solder-bonded and wire-bonded to other members on the same surface, and may be used, for example, in the semiconductor module shown in FIG.

図５に示す半導体モジュールは、ブロック体５および第２金属放熱板７に代わって、Ｃｕ等の導電性材料によりなる金属クリップ９を備え、はんだ接合用電極１６に金属クリップ９が接合された構造となっている。この場合であっても、ワイヤ接合用電極１７にはんだ３が付着することが抑制され、ワイヤ接合用電極１７おけるワイヤ接合が安定するため、信頼性の高い半導体モジュールとなる。 The semiconductor module shown in FIG. 5 has a structure in which a metal clip 9 made of a conductive material such as Cu is provided in place of the block body 5 and the second metal heat dissipation plate 7, and the metal clip 9 is bonded to the solder bonding electrode 16. It has become. Even in this case, the solder 3 is suppressed from adhering to the wire bonding electrode 17, and the wire bonding at the wire bonding electrode 17 is stable, so that the semiconductor module is highly reliable.

本実施形態によれば、はんだ接合用電極１６とワイヤ接合電極１７とが同一の面側に形成されると共に、これらの間に溝部１５１を備えた構造の半導体装置１となる。この半導体装置１は、はんだ接合用電極１６へのはんだ接合の際、溶融したはんだの一部がはんだ接合用電極１６から溢れたり、あるいは飛んだりしても溝部１５１により当該はんだの一部が受け止められる。そのため、ワイヤ接合用電極１７にはんだが付着すること、ひいては、はんだに起因するワイヤの接合不良を抑制でき、ワイヤ接合が安定する効果が得られる。また、この半導体装置１を用いることにより、ワイヤ接合の信頼性が向上した半導体モジュールを構成することができる。 According to the present embodiment, the solder bonding electrode 16 and the wire bonding electrode 17 are formed on the same surface side, and the semiconductor device 1 has a structure in which a groove portion 151 is provided between them. In this semiconductor device 1, even if a part of the molten solder overflows or flies from the solder bonding electrode 16 at the time of solder bonding to the solder bonding electrode 16, a part of the solder is received by the groove portion 151. Be done. Therefore, it is possible to suppress the adhesion of solder to the wire bonding electrode 17, and eventually the wire bonding failure caused by the solder, and the effect of stabilizing the wire bonding can be obtained. Further, by using this semiconductor device 1, it is possible to configure a semiconductor module having improved reliability of wire bonding.

（第２実施形態）
第２実施形態の半導体装置１について、図６を参照して説明する。 (Second Embodiment)
The semiconductor device 1 of the second embodiment will be described with reference to FIG.

図６では、後述する２つのはんだ接合用電極１６が配列する方向に沿った方向を「横方向」として、横方向を矢印で示している。以下、本明細書における「横方向」とは、特に断りがない場合、上記の方向を意味する。 In FIG. 6, the direction along the direction in which the two solder bonding electrodes 16 described later are arranged is defined as the “lateral direction”, and the lateral direction is indicated by an arrow. Hereinafter, the "horizontal direction" in the present specification means the above-mentioned direction unless otherwise specified.

本実施形態の半導体装置１は、例えば図６に示すように、はんだ接合用電極１６および溝部１５１を２つ備える点で上記第１実施形態と相違する。本実施形態では、上記の相違点について主に説明する。 As shown in FIG. 6, for example, the semiconductor device 1 of the present embodiment is different from the first embodiment in that it includes two solder bonding electrodes 16 and a groove portion 151. In this embodiment, the above differences will be mainly described.

半導体装置１は、本実施形態では、例えば図６に示すように、はんだ接合用電極１６を２つ備え、これらが所定の距離を隔てて平行配置されている。 In the present embodiment, the semiconductor device 1 is provided with two solder bonding electrodes 16 as shown in FIG. 6, for example, and these are arranged in parallel at a predetermined distance.

以下、説明の便宜上、２つのはんだ接合用電極１６のうち図６の紙面左側のものを「左のはんだ接合用電極１６」と称し、図６の紙面右側のものを「右のはんだ接合用電極１６」と称することがある。 Hereinafter, for convenience of explanation, of the two solder bonding electrodes 16 on the left side of the paper surface of FIG. 6, the one on the left side of the paper surface is referred to as “left solder bonding electrode 16”, and the one on the right side of the paper surface of FIG. 6 is referred to as “right solder bonding electrode 16”. It may be referred to as "16".

半導体装置１は、溝部１５１を２つ備え、溝部１５１の一方が左のはんだ接合用電極１６とこれに隣接するワイヤ接合用電極１７との間に配置され、溝部１５１の他方が右のはんだ接合用電極１６とこれに隣接するワイヤ接合用電極１７との間に配置されている。 The semiconductor device 1 includes two groove portions 151, one of the groove portions 151 is arranged between the left solder bonding electrode 16 and the wire bonding electrode 17 adjacent thereto, and the other of the groove portions 151 is the right solder bonding. It is arranged between the electrode 16 and the wire bonding electrode 17 adjacent thereto.

溝部１５１は、本実施形態では、例えば、２つのはんだ接合用電極１６の隙間に沿った方向（すなわち図６の横方向に直交する方向）の延長線上とは異なる位置に配置される。溝部１５１は、例えば、横方向における幅が、はんだ接合用電極１６の横方向における幅と同じとされるが、これに限定されるものではなく、ワイヤ接合用電極１７の配置に応じて適宜変更され得る。 In the present embodiment, the groove portion 151 is arranged at a position different from that on the extension line in the direction along the gap between the two solder bonding electrodes 16 (that is, the direction orthogonal to the lateral direction in FIG. 6). The width of the groove portion 151 in the lateral direction is, for example, the same as the width in the lateral direction of the solder bonding electrode 16, but the width is not limited to this and is appropriately changed according to the arrangement of the wire bonding electrodes 17. Can be done.

半導体装置１は、例えば、２つのはんだ接合電極１６の隙間に図示しない温度センサを取り付け、温度センサの配線を２つのはんだ接合電極１６および２つの溝部１５１の間に配置可能な構成である。図示しない温度センサを取り付けた場合、半導体装置１の温度分布を把握し、当該温度に応じて駆動電流を変更し、半導体装置１の過熱や熱ダメージを抑制することも可能である。 The semiconductor device 1 has, for example, a configuration in which a temperature sensor (not shown) is attached to a gap between the two solder joint electrodes 16 and the wiring of the temperature sensor can be arranged between the two solder joint electrodes 16 and the two groove portions 151. When a temperature sensor (not shown) is attached, it is possible to grasp the temperature distribution of the semiconductor device 1 and change the drive current according to the temperature to suppress overheating and thermal damage of the semiconductor device 1.

なお、上記では、半導体装置１が２つのはんだ接合用電極１６を備える場合を代表例として説明したが、これに限定されるものではなく、半導体装置１は、３つ以上のはんだ接合用電極１６を有していてもよい。この場合、溝部１５１は、はんだ接合用電極１６の数に応じて、３つ以上設けられ得る。 In the above description, the case where the semiconductor device 1 includes two solder bonding electrodes 16 has been described as a typical example, but the present invention is not limited to this, and the semiconductor device 1 is limited to three or more solder bonding electrodes 16. May have. In this case, three or more groove portions 151 may be provided depending on the number of solder bonding electrodes 16.

本実施形態によれば、上記第１実施形態と同様の効果が得られつつ、はんだ接合用電極１６の間に温度センサ等の他の部品が取り付けられ得る構造の半導体装置１となる。 According to the present embodiment, the semiconductor device 1 has a structure in which other parts such as a temperature sensor can be attached between the solder bonding electrodes 16 while obtaining the same effects as those of the first embodiment.

（第３実施形態）
第３実施形態の半導体装置１について、図７を参照して説明する。 (Third Embodiment)
The semiconductor device 1 of the third embodiment will be described with reference to FIG. 7.

本実施形態の半導体装置１は、例えば図７に示すように、溝部１５１を有しておらず、はんだ接合用電極１６を２つ備え、はんだ接合用電極１６が接合部１６１とはんだ受け部１６２とを有してなる点で上記第１実施形態と相違する。本実施形態では、上記の相違点について主に説明する。 As shown in FIG. 7, for example, the semiconductor device 1 of the present embodiment does not have a groove portion 151, includes two solder bonding electrodes 16, and the solder bonding electrodes 16 are a bonding portion 161 and a solder receiving portion 162. It is different from the above-mentioned first embodiment in that it has. In this embodiment, the above differences will be mainly described.

２つのはんだ接合用電極１６は、本実施形態では、例えば、図７に示すように、所定の距離を隔てた対称配置とされる。はんだ接合用電極１６は、他の部材とのはんだ接合に用いられる領域である接合部１６１と、接合部１６１に塗布されたはんだの余剰部分を受けるための領域であるはんだ受け部１６２とを備える。本実施形態に係るはんだ接合用電極１６は、例えば、絶縁層１５のパターン形状を変更し、電解めっきにより接合部１６１およびはんだ受け部１６２を同時に形成することにより得られる。接合部１６１は、例えば、第１電極パッド１２上に形成される。 In the present embodiment, the two solder bonding electrodes 16 are arranged symmetrically with a predetermined distance, for example, as shown in FIG. 7. The solder joining electrode 16 includes a joining portion 161 which is a region used for solder joining with other members, and a solder receiving portion 162 which is a region for receiving a surplus portion of solder applied to the joining portion 161. .. The solder bonding electrode 16 according to the present embodiment is obtained, for example, by changing the pattern shape of the insulating layer 15 and simultaneously forming the bonding portion 161 and the solder receiving portion 162 by electrolytic plating. The joint portion 161 is formed on, for example, the first electrode pad 12.

はんだ受け部１６２は、例えば図７に示すように、接合部１６１の外側に突出すると共に、複数のワイヤ接合用電極１７の配列方向における外側に配置される。この場合、はんだ接合用電極１６とワイヤ接合用電極１７との間のスペースを小さくし、半導体装置１の横方向に直交する方向における幅を小さくすることも可能となる。はんだ受け部１６２は、接合部１６１におけるはんだ接合の際に、溶融したはんだのうち余剰部分の流れを作り、はんだの一部がワイヤ接合用電極１７に向かうことを防ぐ役割を果たす。つまり、はんだ受け部１６２は、余ったはんだをワイヤ接合用電極１７とは異なる方向に誘導することで、ワイヤ接合用電極１７に意図しないはんだが付着することを抑制するために設けられる部位である。 As shown in FIG. 7, for example, the solder receiving portion 162 projects to the outside of the bonding portion 161 and is arranged outside in the arrangement direction of the plurality of wire bonding electrodes 17. In this case, it is possible to reduce the space between the solder bonding electrode 16 and the wire bonding electrode 17 and reduce the width of the semiconductor device 1 in the direction orthogonal to the lateral direction. The solder receiving portion 162 plays a role of creating a flow of a surplus portion of the molten solder at the time of solder bonding in the bonding portion 161 and preventing a part of the solder from heading toward the wire bonding electrode 17. That is, the solder receiving portion 162 is a portion provided to prevent unintended solder from adhering to the wire bonding electrode 17 by guiding the excess solder in a direction different from that of the wire bonding electrode 17. ..

なお、はんだ受け部１６２は、図７に示すようにワイヤ接合用電極１７の側に突出する配置に限定されるものではなく、ワイヤ接合用電極１７とは異なる方向に突出する配置であってもよい。はんだ受け部１６２は、第１電極パッド１２上に形成されてもよいし、一部または全部が半導体素子１１の一面１１ａ上に直接形成されてもよい。はんだ受け部１６２の一部または全部が一面１１ａ上に直接形成された場合、接合部１６１とはんだ受け部１６２との間、あるいははんだ受け部１６２内で高低差が生じ、接合部１６１でのはんだ接合の際に、余剰部分のはんだが流れ込みやすくなることが期待される。 The solder receiving portion 162 is not limited to the arrangement that protrudes toward the wire bonding electrode 17 as shown in FIG. 7, and may be arranged so as to project in a direction different from that of the wire bonding electrode 17. good. The solder receiving portion 162 may be formed on the first electrode pad 12, or may be partially or wholly formed directly on one surface 11a of the semiconductor element 11. When a part or all of the solder receiving portion 162 is formed directly on the one surface 11a, a height difference occurs between the joint portion 161 and the solder receiving portion 162 or in the solder receiving portion 162, and the solder at the joint portion 161 is soldered. It is expected that the excess solder will easily flow in during joining.

また、はんだ接合用電極１６は、１つのはんだ受け部１６２を有する例に限定されるものではなく、複数のはんだ受け部１６２を有する構成であってもよい。さらに、半導体装置１は、上記第１実施形態と同様に、１つのはんだ接合用電極１６を有する構成であってもよい。 Further, the solder bonding electrode 16 is not limited to the example of having one solder receiving portion 162, and may have a configuration having a plurality of solder receiving portions 162. Further, the semiconductor device 1 may have a configuration having one solder bonding electrode 16 as in the first embodiment.

本実施形態によれば、はんだ接合用電極１６の接合部１６１に他の部材をはんだ接合する際に、溶融したはんだのうち余剰部分がはんだ受け部１６２に流れ込み、ワイヤ接合用電極１７にはんだが付着することが抑制される半導体装置１となる。そのため、上記第１実施形態と同様に、ワイヤ接合用電極１７におけるワイヤ接合が安定する効果が得られる。また、はんだ接合用電極１６を複数備える場合には、上記第２実施形態と同様に、温度センサ等を取り付けることも可能な構成となる。 According to this embodiment, when another member is solder-bonded to the bonding portion 161 of the solder bonding electrode 16, the surplus portion of the molten solder flows into the solder receiving portion 162, and the solder is transferred to the wire bonding electrode 17. The semiconductor device 1 is prevented from adhering. Therefore, as in the first embodiment, the effect of stabilizing the wire bonding in the wire bonding electrode 17 can be obtained. Further, when a plurality of solder bonding electrodes 16 are provided, a temperature sensor or the like can be attached as in the second embodiment.

（第４実施形態）
第４実施形態の半導体装置１について、図８～図１１を参照して説明する。 (Fourth Embodiment)
The semiconductor device 1 of the fourth embodiment will be described with reference to FIGS. 8 to 11.

本実施形態の半導体装置１は、例えば図８に示すように、溝部１５１に代わって、絶縁層１５のうちはんだ接合用電極１６とワイヤ接合用電極１７との間の領域に凸部１５２を有する点で上記第１実施形態と相違する。本実施形態では、上記の相違点について主に説明する。 As shown in FIG. 8, for example, the semiconductor device 1 of the present embodiment has a convex portion 152 in a region of the insulating layer 15 between the solder bonding electrode 16 and the wire bonding electrode 17 instead of the groove portion 151. It differs from the first embodiment in that it is different from the first embodiment. In this embodiment, the above differences will be mainly described.

絶縁層１５は、本実施形態では、例えば図９に示すように、電極１６、１７の間の領域に半導体装置１の厚み方向に向かって突出する凸部１５２が形成されている。 In the present embodiment, the insulating layer 15 is formed with a convex portion 152 projecting in the thickness direction of the semiconductor device 1 in the region between the electrodes 16 and 17, for example, as shown in FIG.

凸部１５２は、例えば、任意の絶縁性材料により構成され、ディスペンサー塗布等の方法により形成され得る。凸部１５２は、はんだ接合用電極１６へのはんだ接合の際、余剰なはんだの一部が溢れたり、飛んだりした場合に、当該はんだの一部をせき止め、または受け止め、ワイヤ接合用電極１７にはんだが付着することを抑制する役割を果たす。凸部１５２は、絶縁層１５と同じ絶縁性材料で構成されてもよいし、異なる絶縁性材料で構成されてもよい。凸部１５２は、例えば図１０に示すように、その先端部１５２ａが、はんだ接合用電極１６に図示しない他部材を接合するために塗布されるはんだ３よりも突出する厚みとされる。 The protrusion 152 is made of, for example, any insulating material and can be formed by a method such as dispenser coating. When a part of the excess solder overflows or flies during solder bonding to the solder bonding electrode 16, the convex portion 152 dams or receives a part of the solder to the wire bonding electrode 17. It plays a role of suppressing the adhesion of solder. The convex portion 152 may be made of the same insulating material as the insulating layer 15, or may be made of a different insulating material. As shown in FIG. 10, for example, the convex portion 152 has a thickness at which the tip portion 152a protrudes from the solder 3 applied to bond another member (not shown) to the solder bonding electrode 16.

なお、上記では、半導体装置１が１つの凸部１５２を備え、１つのはんだ接合用電極１６とすべてのワイヤ接合用電極１７とを隔てるように形成された例について説明したが、これに限定されるものではない。例えば、凸部１５２は、図１１に示すように、複数設けられ、はんだ接合用電極１６とワイヤ接合用電極１７とのそれぞれの間に配置されてもよい。 In the above description, an example in which the semiconductor device 1 is provided with one convex portion 152 and is formed so as to separate one solder bonding electrode 16 and all wire bonding electrodes 17 has been described, but the present invention is limited to this. It's not something. For example, as shown in FIG. 11, a plurality of convex portions 152 may be provided and may be arranged between the solder bonding electrode 16 and the wire bonding electrode 17.

また、上記では、図９に示すように、はんだ接合用電極１６とワイヤ接合用電極１７との間の全域が凸部１５２とされた例について説明したが、半導体装置１は、これらの領域の一部が凸部１５２とされた構成であってもよい。 Further, in the above, as shown in FIG. 9, an example in which the entire area between the solder bonding electrode 16 and the wire bonding electrode 17 is a convex portion 152 has been described, but the semiconductor device 1 has a region of these regions. The configuration may be such that a part thereof is a convex portion 152.

本実施形態によれば、はんだ接合用電極１６へのはんだ接合の際、溶融したはんだの一部がはんだ接合用電極１６の領域側に溢れたり、飛んだりした場合であっても、凸部１５２によりせき止め、または受け止められる構造の半導体装置１となる。そのため、はんだ接合用電極１６へのはんだ接合を行っても、ワイヤ接合用電極１７にはんだが付着することが抑制され、ワイヤ接合が安定する。 According to the present embodiment, when soldering to the solder bonding electrode 16, even if a part of the molten solder overflows or flies to the region side of the solder bonding electrode 16, the convex portion 152 The semiconductor device 1 has a structure that can be dammed or received by soldering. Therefore, even if solder bonding is performed to the solder bonding electrode 16, solder is suppressed from adhering to the wire bonding electrode 17, and the wire bonding is stable.

（他の実施形態）
本発明は、実施例に準拠して記述されたが、本発明は当該実施例や構造に限定されるものではないと理解される。本発明は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらの一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本発明の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present invention has been described in accordance with the examples, it is understood that the present invention is not limited to the examples and structures. The present invention also includes various modifications and variations within a uniform range. In addition, various combinations and forms, as well as other combinations and forms including only one element thereof, more or less, are also within the scope and scope of the present invention.

（１）上記第１実施形態では、溝部１５１にはんだの濡れ性が絶縁層１５よりも高いダミー層１８を設けた例について説明したが、これに限定されるものではない。例えば、半導体装置１がダミー層１８を有さない構成であってもよいし、溝部１５１が絶縁層１５を貫通しない凹部であってもよい。これらのような場合であっても、はんだ接合用電極１６から溢れたはんだの一部が溝部１５１で受け止められ、ワイヤ接合用電極１７に付着することが抑制される。 (1) In the first embodiment, an example in which a dummy layer 18 having a solder wettability higher than that of the insulating layer 15 is provided in the groove portion 151 has been described, but the present invention is not limited thereto. For example, the semiconductor device 1 may have a configuration that does not have the dummy layer 18, or the groove portion 151 may be a recess that does not penetrate the insulating layer 15. Even in such a case, a part of the solder overflowing from the solder bonding electrode 16 is received by the groove portion 151, and the adhesion to the wire bonding electrode 17 is suppressed.

また、溝部１５１が第１電極パッド１２に達しない凹部とされた場合、当該凹部の底部にダミー層１８を設けてもよいし、当該凹部にレーザー加工等の粗化処理を施してはんだの濡れ性を絶縁層１５の他の部位よりも向上させてもよい。 Further, when the groove portion 151 is a recess that does not reach the first electrode pad 12, a dummy layer 18 may be provided at the bottom of the recess, or the recess may be roughened by laser processing or the like to wet the solder. The property may be improved more than other parts of the insulating layer 15.

（２）さらに、上記各実施形態では、半導体素子１１の一面１１ａ上にはんだ接合用電極１６およびワイヤ接合用電極１７が形成された例について説明したが、これに限定されるものではない。例えば、半導体装置１は、半導体素子１１の一面１１ａと他面１１ｂとを繋ぐ側面が封止材により覆われ、かつワイヤ接合用電極１７が封止材の上に形成された構造、いわゆるファンアウトパッケージ構造であってもよい。この場合、絶縁層１５は、例えば、第２電極パッド１３に一端が接続され、他端が半導体素子１１の一面１１ａの外郭外側にまで延設された再配線を有する構成とされ、再配線の一部を露出させるパターン形状とされる。そして、ワイヤ接合用電極１７は、例えば、再配線の他端側において絶縁層１５から露出する部分に形成され得る。 (2) Further, in each of the above embodiments, an example in which the solder bonding electrode 16 and the wire bonding electrode 17 are formed on one surface 11a of the semiconductor element 11 has been described, but the present invention is not limited thereto. For example, the semiconductor device 1 has a structure in which a side surface connecting one surface 11a and another surface 11b of a semiconductor element 11 is covered with a sealing material and a wire bonding electrode 17 is formed on the sealing material, that is, a so-called fan-out. It may be a package structure. In this case, the insulating layer 15 is configured to have, for example, a rewiring in which one end is connected to the second electrode pad 13 and the other end extends to the outside of the outer shell of one surface 11a of the semiconductor element 11. It has a pattern shape that exposes a part of it. The wire bonding electrode 17 can be formed, for example, in a portion exposed from the insulating layer 15 on the other end side of the rewiring.

１１ 半導体素子
１１ａ 一面
１５ 絶縁層
１５１ 溝部
１５２ 凸部
１６ はんだ接合用電極
１６１ 接合部
１６２ はんだ受け部
１７ ワイヤ接合用電極
１８ ダミー層
11 Semiconductor element 11a One side 15 Insulation layer 151 Groove part 152 Convex part 16 Solder bonding electrode 161 Bonding part 162 Soldering receiving part 17 Wire bonding electrode 18 Dummy layer

Claims (6)

半導体素子（１１）と、
前記半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するはんだ接合用電極（１６）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するワイヤ接合用電極（１７）と、
前記絶縁層のうち前記はんだ接合用電極と前記ワイヤ接合用電極との間に配置される溝部（１５１）と、を備える、半導体装置。 Semiconductor element (11) and
An insulating layer (15) provided on one surface (11a) of the semiconductor element and
A solder bonding electrode (16) provided on the one side and partially exposed from the insulating layer, and a solder bonding electrode (16).
A wire bonding electrode (17) provided on the one side and partially exposed from the insulating layer, and a wire bonding electrode (17).
A semiconductor device including a groove portion (151) arranged between the solder bonding electrode and the wire bonding electrode in the insulating layer. 前記溝部には、前記絶縁層よりもはんだの濡れ性が高いダミー層（１８）が形成されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a dummy layer (18) having a higher wettability of solder than the insulating layer is formed in the groove portion. 前記半導体素子の前記一面の側には、複数の前記ワイヤ接合用電極および１つの前記溝部が形成されており、
前記溝部は、前記はんだ接合用電極とすべての前記ワイヤ接合用電極とを隔てるように配置されている、請求項１または２に記載の半導体装置。 A plurality of the wire bonding electrodes and one groove portion are formed on the one side of the semiconductor element.
The semiconductor device according to claim 1 or 2, wherein the groove portion is arranged so as to separate the solder bonding electrode and all the wire bonding electrodes. 前記半導体素子の前記一面の側には、複数の前記はんだ接合用電極、前記ワイヤ接合用電極および前記溝部が形成されており、
複数の前記はんだ接合用電極は、平行配置されており、
前記溝部の数は、前記はんだ接合用電極と同じであり、
複数の前記溝部は、隣接する２つの前記はんだ接合用電極の隙間が延びる方向の延長線上とは異なる位置に配置されている、請求項１または２に記載の半導体装置。 A plurality of the solder bonding electrodes, the wire bonding electrodes, and the groove portions are formed on the one side of the semiconductor element.
The plurality of solder bonding electrodes are arranged in parallel, and the solder bonding electrodes are arranged in parallel.
The number of grooves is the same as that of the solder bonding electrode.
The semiconductor device according to claim 1 or 2, wherein the plurality of grooves are arranged at positions different from those on an extension line in a direction in which a gap between two adjacent solder bonding electrodes extends. 半導体素子（１１）と、
前記半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するはんだ接合用電極（１６）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するワイヤ接合用電極（１７）と、
前記絶縁層のうち前記はんだ接合用電極と前記ワイヤ接合用電極との間の領域に配置される凸部（１５２）と、を備える、半導体装置。 Semiconductor element (11) and
An insulating layer (15) provided on one surface (11a) of the semiconductor element and
A solder bonding electrode (16) provided on the one side and partially exposed from the insulating layer, and a solder bonding electrode (16).
A wire bonding electrode (17) provided on the one side and partially exposed from the insulating layer, and a wire bonding electrode (17).
A semiconductor device comprising a convex portion (152) arranged in a region of the insulating layer between the solder bonding electrode and the wire bonding electrode. 半導体素子（１１）と、
前記半導体素子の一面（１１ａ）に設けられる絶縁層（１５）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するはんだ接合用電極（１６）と、
前記一面の側に設けられ、前記絶縁層から一部が露出するワイヤ接合用電極（１７）と、を備え、
前記はんだ接合用電極は、他の部材とのはんだ接合に用いられる領域である接合部（１６１）と、はんだ接合の際に溶融したはんだの一部を受け止めるための領域であるはんだ受け部（１６２）とを有してなり、
前記はんだ受け部は、前記接合部から外部に向けて突出している、半導体装置。
Semiconductor element (11) and
An insulating layer (15) provided on one surface (11a) of the semiconductor element and
A solder bonding electrode (16) provided on the one side and partially exposed from the insulating layer, and a solder bonding electrode (16).
A wire bonding electrode (17) provided on the one side thereof and partially exposed from the insulating layer is provided.
The solder bonding electrode has a joint portion (161) which is a region used for solder bonding with other members, and a solder receiving portion (162) which is a region for receiving a part of molten solder during solder bonding. ) And have
The solder receiving portion is a semiconductor device that projects outward from the joint portion.
JP2020130991A 2020-07-31 2020-07-31 Semiconductor device Pending JP2022027162A (en)

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