JP2013048280A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resin sealed semiconductor package which prevents cracking of a die bonding material for mounting of a semiconductor chip.SOLUTION: A semiconductor chip CP1 is mounted on an upper surface f1 of a die pad DP1 through a die bonding material DB1, and is sealed with an insulating resin IR1. The upper surface f1 of the die pad DP1 contacted with the insulating resin IR1 is made rough, and a backside f2 of the die pad DP1 and an outer lead OL1 are not made rough.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a technology effective when applied to a semiconductor device in the form of a resin-encapsulated semiconductor package and a manufacturing method thereof.

  In a semiconductor device, a semiconductor chip is sealed (packaged) with an insulating resin material or the like to protect the semiconductor chip and maintain performance. For example, a semiconductor chip on which an integrated circuit typified by a memory circuit, a logic circuit, a power supply circuit and the like is formed is bonded (mounted) to a chip mounting portion (die pad) of a lead frame with a paste material. A part of the lead frame and the semiconductor chip are sealed with an insulating resin to constitute a semiconductor device. In recent years, copper and copper alloys having high electrical conductivity and thermal conductivity and low cost have been used as lead frame materials.

  For example, Japanese Patent Laying-Open No. 2005-191178 (Patent Document 1) discloses a technique in which dimples whose side walls protrude inward are formed on a heat spreader to improve adhesion with an insulating resin.

  Further, for example, in Japanese Patent Laid-Open No. 5-218275 (Patent Document 2), a dimple formed on a lead frame in order to improve adhesion to a sealing material is formed by pressing, thereby warping an island. A technique for eliminating the problem is disclosed.

  In addition, for example, in Japanese Patent Application Laid-Open No. 2002-83917 (Patent Document 3), a plurality of protrusions are selectively formed by etching a part of the surface of a lead frame, thereby improving adhesiveness with a resin. A technique for realizing a high lead frame is disclosed.

JP 2005-191178 A JP-A-5-218275 JP 2002-83917 A

  When the present inventors examined a package structure (semiconductor package) with high heat dissipation, a package in which the back surface f2a of the die pad DPa is exposed from the insulating resin IRa as shown in FIG. 21 is effective. I understood that. This is because the heat generation of the semiconductor chip CPa is easily dissipated to the outside by exposing the back surface f2a of the die pad DPa to the outside of the insulating resin IRa. In such a form, the back surface f2a of the die pad DPa exposed to the outside can be used as an electrode.

  However, further studies by the present inventors have revealed that the following problems arise in the package-type semiconductor device as shown in FIG. In other words, it was found that the electrical characteristics of the package semiconductor device with the back surface f2a of the die pad DPa exposed deteriorate in a temperature cycle test or the like. Furthermore, as shown in FIG. 22, it has been found that the generation of cracks ck is involved in the die bonding material DBa in the vicinity of the interface between the die pad DPa and the insulating resin IRa as shown in FIG. . FIG. 22 is an enlarged view of a main part p10a in the semiconductor device of FIG. Hereinafter, the contents considered by the present inventors will be described in detail as to the cause of the occurrence of the crack ck in the die bonding material DBa.

  In the case where the back surface f2a of the die pad DPa is exposed to the outside, moisture easily enters the insulating resin IRa when the semiconductor device is stored. Here, because the die pad DPa and the insulating resin IRa have different coefficients of thermal expansion, peeling may occur at the interface between them due to heating during reflow mounting. When the moisture enters the peeling portion, the internal pressure of the peeling portion increases and expands. Through a temperature cycle, a crack ck is generated in the die bonding material DBa due to the stress due to the difference in linear expansion of the member in the vicinity of the peeled portion.

  For example, there is a semiconductor device in which the semiconductor chip CPa has a conductive electrode on the back surface, and the back surface f2a of the die pad DPa is used as an electrode. In this case, the die bonding material DBa needs to have electrical continuity between the semiconductor chip CPa and the die pad DPa. If cracks occur in such a die bonding material DBa, there is a possibility of causing electrical conduction failure. As a result, it has been clarified by the present inventors that the electrical characteristics of the semiconductor device can be degraded and the reliability can be reduced.

  Accordingly, one of the objects of the present invention is to improve the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin, and in particular to provide a technique for preventing cracks in a die bonding material. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  According to one embodiment of the present invention, in a semiconductor device in which a semiconductor chip is mounted on an upper surface of a die pad portion via a die bonding material and sealed with an insulating resin, the upper surface of the die pad portion that contacts the insulating resin. A technique is provided in which the surface of the die pad portion and the outer lead portion are not roughened.

  Of the plurality of inventions disclosed in the present application, the effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing which shows the structure of the semiconductor device which is Embodiment 1 of this invention, Comprising: (A) is a whole top view, (B) is seen in the arrow direction along the BB line in (A). FIG. 1 is an explanatory diagram of a semiconductor device according to a first embodiment of the present invention. It is explanatory drawing which shows the other structure of the semiconductor device which is Embodiment 1 of this invention, (A) is a whole top view, (B) is an arrow direction along the BB line in (A). FIG. It is explanatory drawing which shows other structure of the semiconductor device which is Embodiment 1 of this invention, Comprising: (A) is a whole top view, (B) is an arrow along the BB line in (A). It is sectional drawing seen in the direction. It is explanatory drawing which shows other structure of the semiconductor device which is Embodiment 1 of this invention, Comprising: (A) is a whole top view, (B) is an arrow along the BB line in (A). It is sectional drawing seen in the direction. It is explanatory drawing which shows other structure of the semiconductor device which is Embodiment 1 of this invention, Comprising: (A) is a whole top view, (B) is an arrow along the BB line in (A). It is sectional drawing seen in the direction. It is a flowchart for demonstrating the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 8 is a fragmentary cross-sectional view of the semiconductor device that is Embodiment 1 of the present invention during the manufacturing step and corresponding to the roughening step s102 of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8 and corresponding to a die bonding step s103 of FIG. 7; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9 and corresponding to a wire bonding step s <b> 104 of FIG. 7. FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10 but corresponding to a molding step s105 in FIG. 7; 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11 and corresponding to a tie bar cutting step s106 of FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention, Comprising: (A) is a principal part top view, (B) is an arrow direction along the BB line in (A). FIG. It is a graph for demonstrating the characteristic of the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a graph for demonstrating the other characteristic of the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is explanatory drawing in the other manufacturing process of the semiconductor device which is Embodiment 1 of this invention, (A) is a principal part top view, (B) is along the BB line in (A). It is principal part sectional drawing seen in the arrow direction. 7A and 7B are explanatory views of still another manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which FIG. 5A is a plan view of a main part, and FIG. 5B is taken along line BB in FIG. It is principal part sectional drawing seen in the arrow direction. 7A and 7B are explanatory views of still another manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which FIG. 5A is a plan view of a main part, and FIG. 5B is taken along line BB in FIG. It is principal part sectional drawing seen in the arrow direction. 7A and 7B are explanatory views of still another manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which FIG. 5A is a plan view of a main part, and FIG. 5B is taken along line BB in FIG. It is principal part sectional drawing seen in the arrow direction. It is sectional drawing which shows the structure of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which the present inventors examined. It is a principal part enlarged view of the semiconductor device of FIG. FIG. 22 is an explanatory diagram of the semiconductor device of FIG. 21.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, first, the problems encountered in the semiconductor device having the structure studied by the present inventors and the manufacturing method thereof will be described in detail.

  As described with reference to FIGS. 21 and 22, in the package (semiconductor package) structure in which the back surface f2a of the die pad DPa is exposed from the insulating resin (mold resin) IRa, the vicinity of the boundary between the die pad DPa and the insulating resin IRa It was found that the insulating resin IRa was easy to peel off. Thereby, it had the subject of reliability fall. On the other hand, further investigations by the present inventors have revealed that the adhesiveness with the insulating resin IRa can be improved by roughening the surfaces of the die pad DPa and the plurality of lead portions LDa by etching. . By forming irregularities by roughening, the insulating resin IRa enters the irregularities, and it becomes difficult to peel off due to the anchor effect. Such an effect is remarkable when the insulating resin IRa is an epoxy resin.

  A method for manufacturing a semiconductor device including the roughening step of the lead frame LFa having such a peeling prevention effect will be briefly described.

  First, a semiconductor chip CPa is formed by dividing a semiconductor wafer on which a semiconductor element has been formed into pieces by dicing. In addition, a lead frame LFa including a die pad DPa made of copper or a copper alloy and a plurality of lead portions LDa is prepared. Then, the lead frame LFa is immersed in an etching solution and etched to roughen the surface. Subsequently, the semiconductor chip CPa is bonded to the die pad DPa of the lead frame LFa using the die bonding material DBa, and the desired electrode on the semiconductor chip CPa and the desired lead portion LDa are connected by the bonding wire BWa. Thereafter, the above-described configuration is sealed with the insulating resin IRa, and the suspension lead portion that has fixed the die pad DPa to the lead frame LFa is cut. Thereafter, resin burrs made of excess insulating resin IRa are removed, and after a desired plating step and mark step, unnecessary lead portions are finally cut and molded to form a semiconductor device.

  As described above, the adhesion with the insulating resin IRa can be improved by etching the lead frame LFa to roughen the surface. From this point of view, it has been found that the occurrence of cracks ck in the die bonding material DBa due to the temperature cycle is suppressed, and the reliability can be improved. However, further studies by the present inventors have revealed that other problems may occur in the roughening technique as described above.

  For example, consider a case where the entire upper and lower surfaces of the lead frame LFa are etched to be roughened. As a result, the back surface f2a of the die pad DPa is also roughened. That is, the insulating resin IRa is firmly adhered to the roughened back surface f2a. Here, in the semiconductor device of the first embodiment, the back surface f2a of the die pad DPa needs to be exposed from the insulating resin IRa. However, as shown in FIG. 23, the insulating resin IRa that is firmly adhered to the back surface f2a of the die pad DPa may remain as a resin burr BR even after the burr removal process. FIG. 23 is an explanatory diagram showing the appearance of the semiconductor device studied here. As described above, the resin burrs BR remaining on the exposed back surface f2a of the die pad DPa can cause mounting defects and electrical characteristic defects. Further, such a resin burr BR may drop in a subsequent cutting process or the like, which may cause foreign matter.

  In order to avoid such a problem, the present inventors examined a method in which the back surface f2a of the die pad DPa is not roughened by performing etching on one surface (upper surface) of the lead frame LFa. As a result, the effect of suppressing the occurrence of crack ck in the die bonding material DBa as described above could be obtained without leaving the resin burr BR as shown in FIG. 23 on the back surface f2a of the die pad DPa.

  However, it has been found that, even in the method of roughening one side (upper surface) of the lead frame LFa, the following problems can be caused by further studies by the present inventors.

  For example, when the inner lead portion ILa connecting the bonding wire BWa is plated, the plating may be damaged depending on the combination of the type of plating and the type of etching solution for roughening. I understood. Such damage to the main conductive portion is a cause of deterioration of electrical characteristics and can be a cause of reducing reliability.

  Further, for example, when the outer lead portion OLa outside the insulating resin IRa or the suspension lead portion that fixes the die pad to the lead frame is roughened, the insulating resin IRa that is firmly adhered also to the region. Can remain. In particular, if the resin remains in the area to be cut in the subsequent process (for example, tie bar) in the area, it may drop in the cutting process and cause foreign matter, or the cut mold may be damaged. It turns out that there is sex.

  As described above, even if the surface of one surface of the lead frame LFa is roughened by the study by the present inventors, there is a problem that the reliability of the semiconductor device is lowered when the entire surface is roughened. It has been found that this can occur. Therefore, in the first embodiment, in order to solve the above-described problem, a semiconductor device manufactured using a lead frame partially roughened on one side and a manufacturing method thereof will be described.

  FIG. 1A is an overall plan view of the semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line BB in FIG. The semiconductor device according to the first embodiment has the following configuration. In addition, in the whole top view of FIG. 1 (A), the figure which saw through insulating resin IR1 is shown.

  The semiconductor device of the first embodiment has a die pad DP1 and a plurality of lead portions LD1. The die pad DP1 is made of a conductor mainly composed of copper. As will be described in detail later in the description of the manufacturing method, the die pad DP1 and the plurality of lead portions LD1 are originally members that constitute the same lead frame LF1. Therefore, the plurality of lead portions LD1 are also made of a conductor mainly made of copper and made of the same material as the die pad DP1. The die pad DP1 is a rectangular flat plate-like member that is disposed in the central portion when the entire semiconductor device is viewed in plan. This flat die pad DP1 has an upper surface (front surface, first main surface) f1 and a back surface (second main surface) f2 located on opposite sides when viewed in the thickness direction. Further, the plurality of lead portions LD1 are arranged around the die pad DP1 so as to be along the two sides in the longitudinal direction of the rectangular die pad DP1 and so as to be arranged at intervals.

  A suspension lead portion SL1 is formed at the end portion of the rectangular die pad DP1 in the short direction. In other words, the suspension lead portion SL1 is arranged so as to protrude from the end portion of the rectangular die pad DP1 in the short direction when viewed in a plan view. The suspension lead portion SL1 is also a member that constitutes the same lead frame LF1, as with the die pad DP1 and the plurality of lead portions LD1. This point will be described in detail later in the description of the manufacturing method.

  On the upper surface f1 of the die pad DP1, a semiconductor chip CP1 including a semiconductor element constituting a desired integrated circuit or the like is mounted. The semiconductor chip CP1 is placed so as to be bonded to the upper surface f1 of the die pad DP1 by the die bonding material DB1. In other words, the semiconductor chip CP1 is mounted on the upper surface f1 of the die pad DP1 via the die bonding material DB1. The die bonding material DB1 may be a resin paste material or a conductive solder material.

  The plurality of lead portions LD1 and the semiconductor chip CP1 are connected by a plurality of bonding wires BW1. The plurality of bonding wires BW1 are connected to pad electrodes (not shown) on the semiconductor chip CP1. The pad electrode is electrically connected to the semiconductor element through the wiring formed in the semiconductor chip CP1. A part of the plurality of lead portions LD1 is plated with a conductor mainly composed of silver (Ag) or Ni, and a plurality of bonding wires BW1 are connected to the portions.

  A part of the plurality of lead portions LD1, the die pad DP1, the suspension lead portion SL1, and the semiconductor chip CP1 are integrally sealed with an insulating resin IR1. The insulating resin IR1 is a resin material made of an epoxy resin.

  As will be described in detail later in the description of the manufacturing method, the above-described suspension lead portion SL1 is a member for supporting the die pad DP1 over the entire lead frame LF1, and the sealing process with the insulating resin IR1 is completed. Later, it is cut off. Therefore, the suspension lead portion SL1 has a structure in which a part of its end surface is exposed from the insulating resin IR1.

  Further, among the plurality of lead portions LD1, the portions where the above-described plating process is performed and the plurality of bonding wires BW1 are connected are sealed with the insulating resin IR1. Thus, the part covered with the insulating resin IR1 among the plurality of lead parts LD1 is referred to as an inner lead part IL1. The other plurality of lead portions LD1 are not sealed with the insulating resin IR1, but are formed so as to be drawn out of the insulating resin IR1. Thus, the part exposed to the exterior of insulating resin IR1 among several lead part LD1 is called outer lead part OL1.

  With the above structure, the semiconductor chip CP1 can be electrically connected from the outside through the plurality of lead portions LD1 via the plurality of bonding wires BW1.

  Here, in the semiconductor device of the first embodiment, the back surface f2 of the die pad DP1 is exposed to the outside of the insulating resin IR1. Thus, by exposing the back surface f2 of the die pad DP1 to the outside, it is possible to realize a structure in which heat generated from the semiconductor chip CP1 can be easily dissipated to the outside. That is, the semiconductor device of the first embodiment has a package structure with high heat dissipation.

  In the semiconductor device of the first embodiment, some of the surfaces of the die pad DP1, the plurality of lead portions LD1, and the suspension lead portion SL1 are rough. Hereinafter, the rough surface means that the surface is roughened.

  FIG. 2 shows an explanatory view of a rough portion of the die pad DP1, the plurality of lead portions LD1, or the suspended lead portion SL1 of the semiconductor device according to the first embodiment. Here, the rough surface is a surface having irregular fine irregularities as shown in FIG. It is more desirable that the unevenness expressed when the “rough surface” is referred to in the first embodiment has an arithmetic average roughness Ra within a range of 0.2 to 0.5 μm. The reason is related to the process of roughening, and will be described in detail later. Here, the arithmetic average roughness Ra of the non-rough area is 0.1 μm or less.

  Note that the arithmetic average roughness Ra means that the reference length is extracted in the direction of the average line av from the concavo-convex curve as shown in FIG. The sum is the average value. Qualitatively, the arithmetic mean roughness Ra increases as the unevenness of the unevenness increases and the variation increases.

  Of the surfaces of the die pad DP1, the plurality of lead portions LD1, and the suspension lead portion SL1, a region that is a rough surface will be described more specifically. In the die pad DP1, the plurality of lead portions LD1 and the suspension lead portion SL1 shown in FIG. 1, the rough surface area is hatched in the overall plan view (FIG. 1A), and is a cross-sectional view of the main part ( In FIG. 1 (B)), the solid line is thicker than the others. In the semiconductor device of the first embodiment, the die pad DP1, one side (upper surface) of the inner lead portion IL1 and the suspension lead portion SL1 among the plurality of lead portions LD1, and the portion in contact with the insulating resin IR1 is a rough surface. It is. Thereby, as above-mentioned, the adhesiveness of die pad DP1, several lead part LD1, suspension lead part SL1, and insulating resin IR1 can be improved. Here, in the semiconductor device of the first embodiment, the back surface f2 of the die pad DP1 is exposed to the outside of the insulating resin IR1, and the back surface f2 of the die pad DP1 is not a rough surface.

  More specifically, in the semiconductor device of the first embodiment, the upper surface f1 of the die pad DP1 including the portion in contact with the insulating resin IR1 in the die pad DP1 is a rough surface. As a result, the adhesion between the die pad DP1 and the insulating resin IR1 is improved. This makes it difficult for the die pad DP1 and the insulating resin IR1 to peel off around the semiconductor chip CP1. Accordingly, it can be said that even if the packaging structure in which moisture easily enters such as the back surface f2 of the die pad DP1 is exposed, it is a structure in which moisture hardly enters at least the periphery of the die bonding material DB1. Thereby, generation | occurrence | production of the crack to die bonding material DB1 can be made hard to raise | generate. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be improved.

  Furthermore, in the semiconductor device according to the first embodiment, the back surface f1 of the die pad DP1 is exposed to the outside, so that the die pad DP1 itself is electrically connected to the semiconductor chip CP1 from the outside separately from the plurality of lead portions LD1. It can be applied as an electrode. Thus, when the die pad DP1 itself is used as an electrode, it is desirable that no resin burr remain on the back surface f2 of the die pad DP1. This is because, for example, the insulating resin IR1 made of an epoxy resin is an insulator, and if this burr remains on the die pad DP1 used as an electrode, an electrical failure may occur. Therefore, in the semiconductor device according to the first embodiment, the back surface f2 exposed from the insulating resin IR1 in the die pad DP1 is not a rough surface and does not have high adhesiveness with the insulating resin IR1, and thus undergoes a burr removing process. Therefore, the resin burr hardly remains. Thereby, it is possible to realize a semiconductor device that is less likely to cause an electrical failure.

  In addition, as an element formed on the semiconductor chip CP1, there is an element having a structure having electrodes on both upper and lower surfaces of the semiconductor chip. In other words, there is also an element having a structure in which an electrode is provided on a surface opposite to a surface to which a plurality of bonding wires BW1 are connected and bonded to the die pad DP1 through the die bonding material DB1. In this case, the die bonding material DB1 uses a conductive material. As such a conductive material, for example, there is a solder material. By using a conductive material as the die bonding material DB1, when the die pad DP1 is used as an electrode, it can be electrically connected to the semiconductor chip CP1 via the die bonding material DB1. From this point of view, the structure using the die bonding material DB1 itself as an electrical conduction member is more effective by applying the structure of the semiconductor device according to the first embodiment in which cracks are hardly generated in the die bonding material DB1. . This is because, when the die bonding material DB1 is used as an electrical conduction member, a crack generated there may cause an electrical conduction failure. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  Furthermore, in the semiconductor device of the first embodiment, the outer lead portion OL1 is not a rough surface among the plurality of lead portions LD1. As described above, the outer lead portion OL1 is a portion exposed from the insulating resin IR1, and is originally a portion to which the insulating resin IR1 does not adhere. When such an outer lead portion OL1 is a rough surface, the adhesiveness with the insulating resin IR1 is increased, and it is difficult to remove the resin burrs attached during the manufacturing process. If the resin adheres to the part where the resin is not originally attached, it may cause a malfunction. For example, in a tie bar cutting process (described in detail later) or the like, the resin may drop and cause generation of foreign matter, or the cut mold may be damaged. On the other hand, in the semiconductor device according to the first embodiment, the outer lead portion OL1 is not a rough surface and has a structure in which the insulating resin IR1 is difficult to adhere, so that the above-described problems are hardly caused. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  FIG. 3 is an explanatory diagram of a region similar to FIG. 1 in another semiconductor device of the first embodiment. In the semiconductor device according to the first embodiment, as shown in FIG. 3, among the plurality of lead portions LD1, the portion p11 sealed with the insulating resin IR1, that is, the inner lead portion IL1 is not rough. More preferred. This is because the inner lead portion IL1 may be subjected to a plating process for connection to the plurality of bonding wires BW1 as described above, and the plating may be damaged by a roughening process described later. Because. Therefore, damage to the plating can be reduced by not making the inner lead part IL1 rough. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  Here, as a result of verification by the present inventors, it has been found that plating with Ni is particularly susceptible to damage in combination with a step of roughening the lead frame LF1 (described in detail later). Therefore, when the inner lead portion IL1 has a structure plated with a conductor mainly composed of Ni, it is more effective to apply the above structure.

  FIG. 4 is an explanatory diagram of a region similar to FIG. 1 in another semiconductor device of the first embodiment. In the semiconductor device according to the first embodiment, as shown in FIG. 4, it is more preferable that the portion p12 sealed with the insulating resin IR1 in the suspension lead portion SL1 is not rough. The reason will be described below. As described above, the suspension lead portion SL1 is a member that integrally forms the lead frame LF1 together with the die pad DP1 and the plurality of lead portions LD1, and is cut after being sealed with the insulating resin IR1 (step). Will be explained later). At that time, if the insulating resin IR1 that is closely adhered remains in the cut portion, as described above, it may drop in the cutting process and cause foreign matter generation, or the cut mold may be damaged. Therefore, by making the suspension lead portion SL1 into a non-rough state and not increasing the adhesiveness with the insulating resin IR1, it is possible to achieve a structure that can easily avoid such problems.

  Here, in the semiconductor device having the structure described with reference to FIG. 3 and FIG. 4 described above, if the adhesiveness of the insulating resin IR1 is reduced by reducing the area that is a rough surface from another viewpoint, the above-described problem can be solved. We are anxious about the effect to solve reducing. However, according to further verification by the present inventors, it has been found that such a reduction in effect cannot occur for the following reason.

  In the semiconductor device shown in FIG. 3 and FIG. 4 in the first embodiment, the inner lead part IL1 and the suspension lead part SL1 are not roughened, so that damage to the plating and defects in the cutting process can be avoided. The adhesiveness with the insulating resin IR1 at this portion is lowered. However, the present inventors are one cause of the problem that the die pad DP1 and the insulating resin IR1 are peeled off, and moisture enters the pressure, thereby generating pressure through a thermal cycle and causing cracks in the die bonding material DB1. As heading. Therefore, the cracks in the die bonding material DB1 are caused by the peeling between the die pad DP1 around the semiconductor chip CP1 and the insulating resin IR1, and the inner lead portion IL1, the suspension lead portion SL1, and the insulating resin IR1. Is not a problem in this point of view. In other words, according to the semiconductor device of the first embodiment, the structure in which the portion surrounding the periphery of the semiconductor chip CP1 in the planar surface of the upper surface f1 of the die pad DP1 is a rough surface causes cracks in the die bonding material DB1. It is the most effective structure for suppression. As described above, as shown in FIGS. 3 and 4 of the first embodiment, the structure in which the lower multiple surface (upper surface) of the inner lead portion IL1 and the suspension lead portion SL1 is not rough does not hinder the solution of the above problem. It is a structure that can avoid damage to plating and defects in the cutting process.

  FIGS. 5 and 6 are explanatory views of the same region as in FIG. 1 in the other semiconductor device of the first embodiment. In particular, in the overall plan view of each drawing (A), for convenience, the semiconductor chip CP1 and The description of the plurality of bonding wires BW1 is omitted. In the above description, the upper surface f1 of the die pad DP1 is assumed to be a rough surface. Here, in the semiconductor device of the first embodiment, in the die pad DP1, it is effective that the surface in contact with the insulating resin IR1 is a rough surface, and the insulating resin IR1 is below the semiconductor chip CP1. The portion p13 not in contact with the surface may be a rough surface as shown in FIG. 5 or may not be a rough surface as shown in FIG. However, in the semiconductor device of the first embodiment, when the die bonding material DB1 is a resin paste material, a portion p13 of the die pad DP1 that is in contact with the die bonding material DB1 under the semiconductor chip CP1 is a rough surface. Some are more preferable. This is because the resin paste material can be expected to improve the adhesion to the rough die pad DP1 by the same anchor effect as the insulating resin IR1. In this way, the adhesion between the die bonding material DB1 made of a resin paste material and the die pad DP1 can be improved, and a structure that is more difficult to peel can be obtained. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  From another point of view, in the portion where the die pad DP1, the inner lead portion IL1 and the suspension lead portion SL1 are in contact with the insulating resin IR1, the larger the area of the rough surface is, the higher the insulating resin IR1 is. It can be said that adhesion can be realized. On the other hand, as described above, there are some places where it is desirable that the surface is not rough, such as the plurality of lead portions LD1 and the suspended lead portions SL1. Therefore, in the semiconductor device of the first embodiment, in the die pad DP1, the area of the portion that is in contact with the insulating resin IR1 and is a rough surface is the portion where the semiconductor chip CP1 is in contact with the insulating resin IR1. It is more preferable that it is larger than the area. The reason will be described below.

  The larger the semiconductor chip CP1, the larger the adhesion area with the die pad DP1 through the die bonding material DB1, so the peeling rate increases. In other words, the larger the semiconductor chip CP1, the easier it is for cracks to occur in the die bonding material DB1. Therefore, in the semiconductor device of the first embodiment, it is effective to improve the adhesion with the insulating resin IR1 by making the die pad DP1 around the semiconductor chip CP1 rough. Here, the area of the portion where the semiconductor chip CP1 is in contact with the insulating resin IR1 means the area of the portion of the upper surface f1 of the die pad DP1 that is not in contact with the insulating resin IR1. Therefore, by ensuring the area of the rough surface on the upper surface f1 of the die pad DP1 more than the area of the semiconductor chip CP1, it is possible to maintain the adhesion with the insulating resin IR1 and suppress the occurrence of cracks. it can. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  As described above, in the semiconductor device according to the first embodiment, the structure is such that the die pad DP1, the plurality of lead portions LD1, and the suspension lead portion SL1 that are in contact with the insulating resin IR1 have a rough surface. The reliability of the semiconductor device can be improved. Here, a structure having a partially rough surface, such as a plurality of lead portions LD1 that require plating, a suspended lead portion SL1 that requires cutting, and the like is not more rough.

  Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment including the step of partially roughening the die pad DP1, the plurality of lead portions LD1, and the suspension lead portion SL1 as described above will be described. explain. First, the whole manufacturing method is demonstrated using the flowchart shown in FIG. 7, and principal part sectional drawing in the element process (FIGS. 8-12). The names of the respective members correspond to the members described with reference to FIG. 1 and the like, and the corresponding members have the same specifications such as shape and material unless otherwise specified.

  First, a semiconductor chip CP1 is formed by dicing a semiconductor wafer on which semiconductor elements and wirings have been formed by various processes by dicing (dicing step s101 in FIG. 1). Separately, a lead frame LF1 having a die pad DP1, a suspension lead portion SL1, and a plurality of lead portions LD1 and made of a conductor mainly made of copper is prepared. Here, of the plurality of lead portions LD1, a portion sealed by the insulating resin IR1 in a later step (molding step s105 in FIG. 1) is exposed from the inner lead portion IL1 and not sealed from the insulating resin IR1. This portion is referred to as an outer lead portion OL1. In addition, the lead frame LF1 is provided with a tie bar tb1 (also referred to as a damper) that bridges individual leads in order to prevent the plurality of lead portions LD1 from being sealed while being in contact with the tip portions.

  Thereafter, as shown in FIG. 8, in the method of manufacturing the semiconductor device of the first embodiment, a part of the lead frame LF1 is roughened (roughening step s102 of FIG. 1). Here, the lead frame LF1 is roughened by etching with a chemical. At that time, in a region where the surface is not roughened, the lead frame LF1 is covered with a protective member so as not to cause etching. Examples of the protective member include a tool and a masking tape MT. Further, a photoresist film patterned by a photolithography method or the like may be used. However, in the method of manufacturing the semiconductor device according to the first embodiment, it is more preferable to apply the masking tape MT as the protective member. This is because, by applying the masking tape MT, the portion covered with the protective member and the portion not covered can be formed with higher accuracy on the lead frame LF1. A specific method of etching and its effect for realizing the roughening, and a specific region for roughening and its effect will be described in detail later.

  Subsequently, as shown in FIG. 9, the semiconductor chip CP1 is bonded to the upper surface f1 of the die pad DP1 via the die bonding material DB1 (die bonding step s103 in FIG. 1). The die bonding material DB1 may be a conductive solder material or a resin paste material made of an epoxy resin. Thereafter, as shown in FIG. 10, the plurality of lead portions LD1 and the semiconductor chip CP1 are connected by the bonding wires BW1 (wire bonding step s104 in FIG. 1). Here, the bonding wire BW1 is connected to the inner lead part IL1 of the plurality of lead parts LD1. The inner lead portion IL1 is preliminarily plated.

  Next, as shown in FIG. 11, the inner lead portion IL1, the part of the die pad DP1, the suspension lead portion SL1, and the semiconductor chip CP1 of the plurality of lead portions LD1 are integrally sealed with the insulating resin IR1. Stop (molding step s105 in FIG. 1). Here, as a part of the die pad DP1, the upper surface f1 is sealed with the insulating resin IR1, and the back surface f2 is not sealed with the insulating resin IR1. Thereby, it is possible to realize a structure in which the back surface f2 of the die pad DP1 is exposed to the outside of the insulating resin IR1.

  In the subsequent step, the tie bar tb1 installed so that the individual leads are not touched in the lead frame LF1 is cut (tie bar cutting step s106 in FIG. 1). In this step, the suspension lead portion SL1 outside the insulating resin IR1 is also cut. Next, a resin burr is removed (a deburring step s107 in FIG. 1), and a plating step s108 and a mark step 109 are performed. Finally, through the lead cutting / forming step s110, as shown in FIG. 12, the plurality of lead portions LD1 outside the insulating resin IR1 are cut and the outer lead portion OL1 is bent, whereby the semiconductor according to the first embodiment. Forming device.

  The above roughening step s102 will be described in more detail. FIG. 13 is a plan view and a cross-sectional view of the main part of the lead frame LF1 during the roughening step s102, and each of the regions (A) and (B) indicates a region corresponding to FIG. . As shown in FIG. 13, in the method of manufacturing the semiconductor device according to the first embodiment, the surface of the lead frame LF1 that is in contact with the insulating resin IR1 is subjected to roughening in a later molding step s105. More specifically, the inner lead portion IL1 of the plurality of lead portions LD1 on the upper surface of the lead frame LF1 is roughened. In other words, in the semiconductor device manufacturing method of the first embodiment, in the roughening step s102, the back surface of the lead frame LF1 including the back surface f2 of the die pad DP1 is not roughened, and a plurality of lead portions LD1. The outer lead portion OL1 is roughened. Thereby, as described above, the adhesion between the lead frame LF1 and the insulating resin IR1 can be improved.

  In particular, the upper surface f1 of the die pad DP1 including the portion in contact with the insulating resin IR1 in the die pad DP1 is roughened. Thereby, the structure described with reference to FIG. 1 can be realized, the adhesiveness between the two is improved at the interface between the die pad DP1 and the insulating resin IR1, and peeling does not easily occur. And even if it is a packaging form in which the back surface f2 of the die pad DP1 is exposed and moisture easily enters, it is possible to make it difficult for the die bonding material DB1 to be cracked due to peeling of the portion. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be improved.

  Here, if only the purpose is to improve the adhesion between the lead frame LF1 and the insulating resin IR1, the entire front and back surfaces of the lead frame LF1 are roughened regardless of whether they are in contact with the insulating resin IR1. The process is easier. This is because the step of forming the masking tape MT or the like for partial roughening described in FIG. 8 in the roughening step s102 can be omitted by doing so. However, in the method of manufacturing the semiconductor device according to the first embodiment, the partial roughening process is applied in order to obtain the effect described with reference to FIG. The reason will be described in detail below.

  As described with reference to FIG. 1, the semiconductor device according to the first embodiment has a structure in which the back surface f2 of the die pad DP1 is exposed from the insulating resin IR1, and therefore the back surface f2 of the die pad DP1 is used as an electrode. it can. And it is better that the resin burr which is a nonconductor does not remain in the back surface f2 of die pad DP1 used as an electrode. From this point of view, the method of manufacturing the semiconductor device according to the first embodiment is more effective. This is because the back surface f2 of the die pad DP1 is not roughened, so even if the insulating resin IR1 wraps around the back surface f2 in the molding step s105 and a resin burr is generated, it does not adhere firmly and is easy to remove. Because.

  Furthermore, in the method of manufacturing the semiconductor device according to the first embodiment, the outer lead portion OL1 of the plurality of lead portions LD1 is not roughened. As a result, even if the insulating resin IR1 adheres to the outer lead portion OL1, the tie bar tb1, or the like for the same reason as described above, the adhesion does not become strong and is easy to remove. For example, when the insulating resin IR1 adheres firmly by roughening the outer lead portion OL1 and the tie bar tb1, and cannot be removed, the insulating property is increased in the subsequent tie bar cutting step s106, the lead cutting / molding step s110, etc. Problems such as generation of foreign matter due to the dropping of the resin IR1 and breakage of the cut mold may occur. In the manufacturing method of the first embodiment, since the outer lead portion OL1 is not roughened, such a problem can be avoided. As described above, in the manufacturing process, the number of steps for forming the masking tape MT and the like is increased because a part of the plurality of lead portions LD1 is not roughened. This can improve the reliability of the semiconductor device. An effect is obtained.

  For the reasons described above, in the method of manufacturing the semiconductor device according to the first embodiment, a partial roughening step in which a part of the lead frame LF1 is roughened and the other parts are not roughened. Apply.

  Further, there are various methods for etching with a chemical solution for roughening the lead frame LF1 made of copper, and the effects as described above can be expected from each. However, in the method of manufacturing the semiconductor device according to the first embodiment, a method of performing the roughening step s102 with an etching solution mainly composed of a mixed solution of hydrogen peroxide and sulfuric acid is more preferable. This is based on the following verification by the present inventors.

  FIG. 14 shows a graph for explaining the dependency of the surface roughening treatment on the change in the insulating resin peeling rate with respect to the change in the number of temperature cycles. Here, the number of temperature cycles indicates how many times one cycle of heating and cooling the semiconductor device to be tested was performed. Further, the degree of the roughening treatment is changed by the time (etching time) in which the frame is immersed in the mixed solution of hydrogen peroxide and sulfuric acid. Shown are etching times of 0 seconds (ie, no roughening), 15 seconds, 30 seconds, and 60 seconds. Here, according to the verification by the present inventors, the copper frame has an arithmetic average roughness Ra of about 0.2 μm when the etching time is 15 seconds, and an arithmetic average roughness Ra of about 30 μm when the etching time is 30 seconds. When the etching time was 0.3 μm and the etching time was 60 seconds, the arithmetic average roughness Ra was about 0.45 μm. In further verification, it was found that the increase in arithmetic average roughness Ra began to saturate in about 60 seconds with respect to the increase in etching time. Therefore, according to the etching of the first embodiment, it is possible to form a rough surface having irregularities with an arithmetic average roughness Ra of 0.2 to 0.5 μm on the lead frame LF1. In addition, the present inventors have confirmed that the arithmetic average roughness Ra of the lead frame LF1 is 0.1 μm or less in the region not roughened by the etching.

  As shown in FIG. 14, when the surface is not roughened, the insulating resin peeling rate exceeds 80% at a temperature cycle number of about 500 times. On the other hand, when the surface is roughened, the insulating resin peeling rate is less than 40% under the same conditions, which is effective. In particular, it was found that almost no peeling was observed in a sample having an arithmetic average roughness Ra of about 0.45 μm after 60 seconds of etching.

  FIG. 15 shows a graph for explaining the difference in the thermal conductivity change rate with respect to the change in the number of temperature cycles with and without the roughening treatment. Here, the rate of change in thermal conductivity indicates the rate of change in thermal conductivity between the semiconductor chip CP1 and the die pad DP1, for example, in the semiconductor device as shown in FIG. The more cracks are generated in the die bonding material DB1, the lower the thermal conductivity between the upper and lower semiconductor chips CP1 and the die pad DP1. That is, the rate of change in thermal conductivity can be regarded as the rate of occurrence of cracks in the die bonding material DB1.

  As shown in FIG. 15, when the surface is not roughened, an increase in the rate of change in thermal conductivity is observed from the point where the number of temperature cycles exceeds 500, and it is considered that cracks are generated in the die bonding material DB1. It is done. On the other hand, when the surface is roughened, the thermal conductivity change rate is maintained at almost 0% even when the number of temperature cycles exceeds 750, and it is understood that the occurrence of cracks in the die bonding material DB1 is suppressed. .

  From the above verification, in the method of manufacturing the semiconductor device of the first embodiment, it was confirmed that the roughening of the lead frame LF1 by etching is effective in suppressing the occurrence of cracks in the die bonding material DB1. . In particular, it has been found that it is more effective to roughen a part of the lead frame LF1 by etching with an etching solution mainly composed of a mixed solution of hydrogen peroxide and sulfuric acid. It has been found that the surface of the lead frame LF1 etched using such a mixed solution has a rough surface with an arithmetic average roughness Ra of about 0.2 to 0.5 μm. In other words, it has been confirmed that the above-described effects can be obtained in the lead frame LF1 partially including a rough surface having irregularities with an arithmetic average roughness Ra of about 0.2 to 0.5 μm.

  Next, the region to be roughened will be described in detail. 16 to 18 are a plan view and a cross-sectional view of relevant parts of the semiconductor device during the roughening step s102 of FIG. 7, respectively, and (A) and (B) are respectively the regions shown in FIG. The same area is shown.

  In the method of manufacturing the semiconductor device according to the first embodiment, in the roughening step s102, as shown in FIG. 16, among the plurality of lead portions LD1, the sealing resin IR1 is sealed by the subsequent molding step s105. It is more preferable that the portion p11 (that is, the inner lead portion IL1) is covered with the masking tape MT and is not roughened. This is because the semiconductor device having the structure described with reference to FIG. 3 can be formed in this manner. That is, damage to the plating can be reduced by not roughening the inner lead portion IL1. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  Here, according to the verification by the present inventors, when a mixed liquid of hydrogen peroxide and sulfuric acid is used as etching for roughening the lead frame LF1 as in the first embodiment, depending on the plating material It turns out that there is a difference in the degree of damage. For example, the plating with Ag did not cause damage to the electrical characteristics due to the etching solution. On the other hand, it has been found that the plating with Ni causes damage to the electrical properties due to the etching solution. Therefore, as described above, the method in which the inner lead portion IL1 is not roughened is applied more effectively when the inner lead portion IL1 is a lead frame LF1 plated with a conductor mainly composed of Ni. It is.

  Further, in the method of manufacturing the semiconductor device according to the first embodiment, in the roughening step s102, as shown in FIG. 17, it is preferable that the suspension lead portion SL1 is covered with a masking tape MT and is not roughened. . The reason is that the insulating resin IR1 attached to the suspension lead portion SL1 does not remain firmly and can be easily removed, and the insulation resin IR1 drops when the suspension lead portion SL1 is cut. This is because it is possible to avoid problems such as the generation of foreign matter due to the occurrence of damage and damage to the cut mold. Thereby, the semiconductor device as shown in FIG. 4 can be formed.

  In the above description, it is assumed that the entire upper surface f1 of the die pad DP1 is a rough surface. Here, in the method of manufacturing the semiconductor device according to the first embodiment, it is effective that the surface in contact with the insulating resin IR1 in the die pad DP1 is a rough surface, which is an insulating layer below the semiconductor chip CP1. The portion p13 not in contact with the conductive resin IR1 may be a rough surface as shown in FIG. 18, or may not be a rough surface as shown in FIG. However, when a resin paste material is applied as the die bonding material DB1 in the method of manufacturing the semiconductor device according to the first embodiment, a portion p13 of the die pad DP1 that is in contact with the die bonding material DB1 under the semiconductor chip CP1. Is more preferably roughened. This is because the resin paste material can be expected to improve the adhesion to the rough die pad DP1 by the same anchor effect as the insulating resin IR1. In this way, the adhesion between the die bonding material DB1 made of a resin paste material and the die pad DP1 can be improved, and a structure that is more difficult to peel can be obtained. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  From another point of view, it can be said that at the portion where the lead frame LF1 and the insulating resin IR1 are in contact with each other, the larger the area to be roughened, the higher the adhesion with the insulating resin IR1. On the other hand, as described above, there are places where it is desirable not to roughen the surface, such as the plurality of lead portions LD1 and the suspended lead portions SL1. Therefore, in the method of manufacturing the semiconductor device according to the first embodiment, the area of the portion of the die pad DP1 that is in contact with the insulating resin IR1 and is to be roughened is that the semiconductor chip CP1 is in contact with the insulating resin IR1. It is more preferable that the area is larger than the area of the portion. The reason will be described below.

  The larger the semiconductor chip CP1, the larger the adhesion area with the die pad DP1 through the die bonding material DB1, so the peeling rate increases. In other words, the larger the semiconductor chip CP1, the easier it is for cracks to occur in the die bonding material DB1. Therefore, in the method of manufacturing the semiconductor device of the first embodiment, as shown in FIG. 19, it is effective to improve the adhesion with the insulating resin IR1 by making the die pad DP1 around the semiconductor chip CP1 rough. It is. Here, the area of the portion where the semiconductor chip CP1 is in contact with the insulating resin IR1 means the area of the portion of the upper surface f1 of the die pad DP1 that is not in contact with the insulating resin IR1. Therefore, by ensuring the area of the rough surface on the upper surface f1 of the die pad DP1 more than the area of the semiconductor chip CP1, it is possible to maintain the adhesion with the insulating resin IR1 and suppress the occurrence of cracks. it can. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, the lead frame LF1 in the portion that contacts the insulating resin IR1 is roughened in the molding step s105, and the back surface f2 of the die pad DP1 and the outer lead portion are formed. By not roughening the OL1 or the like, the reliability of the semiconductor device can be improved. Here, a technique that does not roughen the inner lead portion IL1 that requires plating, the suspended lead portion SL1 that requires cutting, and the like is more effective.

(Embodiment 2)
A cross-sectional view of the semiconductor device according to the second embodiment is shown in FIG. The semiconductor device of the second embodiment has a plurality of lead portions LD2 and a die pad DP2, and a semiconductor chip CP2 is bonded to the upper surface f1 of the die pad DP2 by a die bonding material DB2. These members are sealed with an insulating resin IR2. However, among the plurality of lead portions LD2, the inner lead portion IL2 is sealed with the insulating resin IR2, and the outer lead portion OL2 is exposed. Inner lead part IL2 and semiconductor chip CP2 are connected by a plurality of bonding wires BW2. With these configurations, the outer lead portion OL2 and the semiconductor chip CP2 are electrically connected via the inner lead portion IL2 and the plurality of bonding wires BW2. Further, the plurality of lead portions LD2 and the die pad DP2 are originally members constituting the same lead frame LF2, and are made of the same copper material. In addition, the semiconductor device of the second embodiment has the same members as those described in the first embodiment as members that do not appear on the drawing. However, the semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in the following points. That is, in the semiconductor device of the second embodiment, all of the die pad DP2 is sealed with the insulating resin IR2.

  In the full mold type packaging form like the semiconductor device of the second embodiment, the heat dissipation is low but the moisture resistance is high as compared with the back surface exposed packaging form of the first embodiment. In other words, since the die pad DP2 has a structure that is not exposed to the outside of the insulating resin IR2, it is a structure in which moisture hardly enters. Therefore, the full mold type packaging structure is a structure in which cracking of the die bonding material DB2 due to stress hardly occurs even if peeling occurs at the interface between the die pad DP2 and the insulating resin IR2. However, improving the adhesion at the interface between the die pad DP2 and the insulating resin IR2 is effective from the viewpoint of preventing deterioration of mechanical strength due to package cracks.

  Therefore, also in the semiconductor device according to the second embodiment, desired portions of the die pad DP2, the plurality of lead portions LD2, and the suspended lead portions are roughened in the same manner as in the first embodiment. As shown in FIG. 20, on the upper surface f1 and the rear surface f2 of the die pad DP2, the portions that are in contact with the insulating resin IR2 (indicated by a thick solid line in the drawing) are roughened, thereby improving the mutual adhesion. Can do. Thereby, it becomes difficult to produce a crack in insulating resin IR2. As a result, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  Also in the semiconductor device of the second embodiment, for the same reason as described in the first embodiment, the outer lead portion OL2 of the plurality of lead portions LD2 and the plurality of lead portions LD2 A structure in which the plated portion (in the case of Ni plating) of the inner lead portion IL2 and the suspended lead portion are not roughened is more preferable. Similarly, when a resin paste material is used as the die bonding material DB2, a structure in which the portion of the die pad DP2 under the semiconductor chip CP2 is roughened is more preferable. Accordingly, the reliability of a semiconductor device having a structure in which a semiconductor chip is sealed with an insulating resin can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

av Average line BR Resin burr BW1, BW2 Multiple bonding wires ck Crack CP1, CP2 Semiconductor chip DB1, DB2 Die bonding material DP1, DP2 Die pad f1 surface (first main surface)
f2 Back side (second main surface)
IL1, IL2 Inner lead portion IR1, IR2 Insulating resin LD1, LD2 Multiple lead portions LF1, LF2 Lead frame MT Masking tape OL1, OL2 Outer lead portion Ra Arithmetic average roughness s101 Dicing step s102 Roughening step s103 Die bonding step s104 Wire bonding process s105 Molding process s106 Tie bar cutting process s107 Deburring process s108 Plating process s109 Marking process s110 Lead cutting / forming process SL1 Hanging lead part tb1 Tie bar

Claims (4)

(A) preparing a lead frame comprising a die pad and a plurality of leads arranged around the die pad;
(B) mounting a semiconductor chip on the first main surface of the die pad;
(C) electrically connecting a plurality of pad electrodes on the surface of the semiconductor chip and the plurality of leads through a plurality of bonding wires, respectively;
(D) The semiconductor chip, a part of the die pad, a portion of the plurality of leads to which the plurality of bonding wires are connected, and the plurality of bonding wires are sealed with a sealing resin to form a sealing body. And having a process
In the step (d), a sealing body is formed so that the second main surface opposite to the first main surface of the die pad is exposed,
The roughness of the first main surface of the die pad of the lead frame prepared in the step (a) is larger than the roughness of the second main surface, and the plurality of bonding wires of the plurality of leads are respectively A method for manufacturing a semiconductor device, which is larger than the roughness of a connected portion. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein plating is performed on portions of the plurality of leads of the lead frame prepared in the step (a) where the plurality of bonding wires are connected. In the manufacturing method of the semiconductor device according to claim 2,
The said plating is a manufacturing method of the semiconductor device currently formed with the conductor which has silver as a main component. (A) preparing a lead frame comprising a die pad and a plurality of leads arranged around the die pad;
(B) mounting a semiconductor chip on the first main surface of the die pad;
(C) electrically connecting a plurality of pad electrodes on the surface of the semiconductor chip and the plurality of leads through a plurality of bonding wires, respectively;
(D) The semiconductor chip, a part of the die pad, a portion of the plurality of leads to which the plurality of bonding wires are connected, and the plurality of bonding wires are sealed with a sealing resin to form a sealing body. And having a process
In the step (d), a sealing body is formed so that the second main surface opposite to the first main surface of the die pad is exposed,
A method of manufacturing a semiconductor device, wherein the first main surface of the die pad of the lead frame prepared in the step (a) is roughened.

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