JP2007080889A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can enhance mounting strength of the semiconductor device and improve temperature cycle property. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip 2, a plurality of leads 1a arranged around the semiconductor chip 2, a wire 4 to connect pads 2a of the semiconductor chip 2 and the leads 1a, and a packaging body 3 formed of a packaging resin. Each of the leads 1a is provided with a through-hole 1d that is open in the upper surface 1b and the mounting surface 1c of the lead 1a, and is made by half-etching from both sides of the upper surface 1b and the mounting surface 1c. Thus, the strength of the lead itself can be kept and the small hole 1d be also formed, and when mounting a semiconductor device (QFN 5) by soldering, a solder 8 is inserted into the through-hole 1d to allow it to spread over the upper surface of the lead as a result. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a non-lead type semiconductor device.

  In a surface-mount type semiconductor device having a plurality of external terminals protruding in parallel with each other from a package body, a groove is provided on the lower surface of the external terminal, and the external terminal penetrates from the upper surface to the lower surface and communicates with the groove. There is a technique of providing a hole (for example, see Patent Document 1).

In the lead frame, a plurality of leads are formed with through holes penetrating in the thickness direction of the lead frame, and a cutting line A for electrically separating the leads passes through the through holes. (For example, refer to Patent Document 2).
JP 2002-359336 A (FIG. 1) JP 2004-319996 A (FIG. 2)

  In semiconductor devices such as QFN (Quad Flat Non-leaded Package) and SON (Small Outline Non-leaded package), a part of each lead is exposed as an external terminal on the back side of the sealing body. The semiconductor device is called a non-lead type semiconductor package.

  In a non-lead type semiconductor device, since the area of the lead portion originally exposed on the back surface of the sealing body is small, the mounting strength at the time of solder mounting on the mounting substrate of the semiconductor device is weak. Therefore, as in Patent Documents 1 and 2 above, it is conceivable to simply form holes or grooves in the leads to increase the wet area of the solder and increase the mounting strength. However, if holes or grooves are formed in the leads, In addition, the mechanical strength (bending, warping, etc.) of the lead itself is reduced.

  In the temperature cycle test after assembling the package, as shown in the comparative example of FIG. 12, both the product (semiconductor device) and the mounting substrate 7 expand at a high temperature and contract at a low temperature. 7 is larger, warping 10 occurs in the mounting substrate 7, and stress concentrates on the solder connection portion between the lead 1a and the mounting substrate 7. As a result, as shown in the comparative example of FIG. The problem is that the crack 11 is formed.

  Therefore, it is necessary to increase the mounting strength during solder mounting while maintaining the strength of each lead.

  In addition, as shown in FIG. 12, it is conceivable to increase the mounting strength without reducing the strength of the lead itself by applying a large amount of solder 8 under the lead. The problem is that a solder short circuit occurs between adjacent leads spread under the back surface of the device. This solder short problem is caused by the following two causes. The first cause is that the distance between the leads facing each other has become shorter (narrower) with the miniaturization of the semiconductor device. The second cause is that the solder 8 applied under the leads starts to harden from the outside of the semiconductor device by the heat treatment process. This is because the heat generated by the heat treatment process is more likely to be accumulated on the back surface of the semiconductor device than on the outside of the semiconductor device. In other words, since the warmed solder 8 is difficult to be cooled, it takes time to cure, and the solder 8 spreads under the back surface of the semiconductor device.

  In addition, although the structure which provides a hole and a groove part is disclosed in the said patent document 1 (Unexamined-Japanese-Patent No. 2002-359336), since both a hole and a groove part are provided, the mechanical strength of a lead | read | reed is sufficient. The problem is weakening. Furthermore, it seems to be very difficult to form a straight hole penetrating a narrow lead by drilling, laser processing or pressing.

  Further, Patent Document 2 (Japanese Patent Application Laid-Open No. 2004-319996) discloses a structure in which a semicircular hole is formed in the cut surface of the lead tip. The problem of heat shrinkage is not described. If this lead structure is used for solder connection and subjected to a temperature cycle test, the solder formed in the semi-circular hole is effective as a wedge during thermal expansion, but the lead becomes a solder wedge during thermal contraction. As a result, the solder connection portion is stressed and cracks are formed.

  In addition, since the hole formed at the tip of the lead is semicircular, the area of the solder is reduced (halved) and the mounting strength is sufficient compared to the through hole whose entire periphery is surrounded by the inner wall. There is a problem that it cannot be raised.

  An object of the present invention is to provide a semiconductor device capable of increasing the mounting strength.

  Another object of the present invention is to provide a semiconductor device capable of improving temperature cycle performance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a semiconductor chip, a sealing body that seals the semiconductor chip, a surface electrode of the semiconductor chip that is electrically connected to the periphery of the semiconductor chip, and the back surface of the sealing body. And a plurality of leads, each of which has a through hole that opens to the upper surface and the mounting surface of the lead, and the through hole is half-etched from both sides of the upper surface and the mounting surface. It is a hole formed by processing.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the semiconductor device, each of the plurality of leads has a through hole formed in the upper surface and the mounting surface of the lead and formed by half-etching from both sides of the upper surface and the mounting surface, so that the solder is formed into the through hole. As a result, the mounting strength of the semiconductor device can be increased. In addition, even if stress due to thermal expansion or contraction occurs in the temperature cycle test and the warping is formed on the mounting board, the lead and solder are locked by the solder pillars arranged in the through holes. The formation of cracks can be prevented, and as a result, the mounting strength of the semiconductor device can be improved and the temperature cycle performance can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
1 is a perspective view showing an example of the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1, and FIG. 3 shows the structure of the semiconductor device shown in FIG. 4 is an enlarged partial sectional view showing an example of the shape of the through hole in the lead of the semiconductor device shown in FIG. 1, and FIG. 5 is an example of the shape of the through hole in the width direction of the lead of the semiconductor device shown in FIG. FIG. 6 is an enlarged partial plan view showing an example of the position of the through hole of the lead of the semiconductor device shown in FIG. 7 is a sectional view showing an example of the mounting structure of the semiconductor device shown in FIG. 1, FIG. 8 is a sectional view showing a mounting structure of a modification of the semiconductor device shown in FIG. 1, and FIG. 9 is an embodiment of the present invention. FIG. 10 is a side view showing the structure of the semiconductor device of the modification shown in FIG. 9, and FIG. 11 is a back view showing the structure of the semiconductor device of the modification shown in FIG. It is. 12 is a cross-sectional view showing the mounting structure of the semiconductor device of the comparative example, and FIG. 13 is a cross-sectional view showing the occurrence of cracks in the mounting structure of the comparative example shown in FIG. 14 is an enlarged partial cross-sectional view showing an example of the structure after exterior plating is formed on the lead of the semiconductor device shown in FIG. 1, and FIG. 15 is a comparative example of the shape of the through hole in the lead of the semiconductor device shown in FIG. It is an expanded partial sectional view which shows a) and modification (b), (c).

  The semiconductor device of the present embodiment shown in FIGS. 1 to 3 is a resin-sealed and small-sized semiconductor package. As shown in FIG. 3, a plurality of semiconductor devices are provided on the periphery of the back surface 3 a of the sealing body 3. The lead 1a is of a non-lead type in which the mounting surfaces 1c are exposed and arranged side by side. In the present embodiment, QFN 5 will be described as an example of the semiconductor device.

  In the QFN 5, the back surface 3a of the sealing body 3 is formed in a square shape, and a plurality of leads 1a are arranged along each of the four sides of the peripheral portion of the back surface 3a.

  The configuration of the QFN 5 will be described. A semiconductor chip 2 having a semiconductor element and a plurality of pads (surface electrodes) 2a on its main surface 2b, a tab (chip mounting portion) 1h for mounting the semiconductor chip 2, a semiconductor chip 2 and a tab 1h is sealed with a resin 3 and the pad 2a of the semiconductor chip 2 is electrically connected to the periphery of the semiconductor chip 2 and mounted on the back surface 3a of the sealing body 3 (partially And a plurality of leads 1a from which 1c is exposed.

  Furthermore, it has the wire 4 which is the some conductive wire which each electrically connects the some pad 2a of the semiconductor chip 2, and the some lead | lead 1a corresponding to this, and the some wire 4 is also a sealing body. 3 is resin-sealed.

  Further, each of the plurality of leads 1a of the QFN 5 has a through hole 1d opened in the upper surface 1b and the mounting surface 1c of the lead 1a as shown in FIG. Each through hole 1d is a hole formed by half-etching from both sides of the upper surface 1b and the mounting surface 1c. Further, the tip portions (end portions far from the semiconductor chip 2) of the leads 1 a are exposed from the sealing body 3. A sealing body 3 is formed between the adjacent leads 1a.

  Further, as shown in FIG. 7, the QFN 5 is a tab-embedded semiconductor package in which the tab 1h is embedded in the sealing body 3, and therefore, the tab 1h is arranged at a high position. In accordance with this, the vicinity of the end of each lead 1a on the chip side is bent upward, thereby forming a step portion 1g, and the wire 4 is connected to the step portion 1g of each lead 1a. .

  The semiconductor chip 2 is made of, for example, silicon, and the back surface 2c thereof is fixed to the tab 1h via the die bond material 6.

  Each lead 1a and tab 1h are made of, for example, a thin plate-like copper alloy.

  Furthermore, the wire 4 is, for example, a gold wire. The sealing resin forming the sealing body 3 is, for example, an epoxy-based thermosetting resin.

  In the QFN 5 of the present embodiment, through holes 1d formed by half-etching from both the upper surface 1b and the mounting surface 1c are formed near the outer tips of the leads 1a. As shown in FIG. 7, the solder 8 disposed between the lead 1a and the terminal 7a of the mounting substrate 7 wraps around the solder 8 to the upper surface 1b side of the lead 1a through the through hole 1d. This increases the mounting strength when stress is applied to the solder connection part due to thermal expansion / shrinkage in a temperature cycle test after solder mounting on the solder. One of the causes of the problem of the crack 11 due to thermal expansion and contraction is the use of a copper alloy as the lead frame material. In order to increase the speed of the semiconductor device, it is desired to lower the resistance of the lead 1a which is an electric signal transmission path. Therefore, in the present embodiment, a copper alloy having a resistance component lower than that of an alloy alloy made of iron (Fe) and nickel (Ni) is used. However, the thermal expansion coefficient of copper alloys is higher than that of iron alloys. Therefore, in the temperature cycle test, the lead 1a itself expands and contracts, so that stress concentrates on the solder joint and the crack 11 is formed. However, as in the present embodiment, by forming through holes 1d formed by half-etching from both sides of the upper surface 1b and the mounting surface 1c in each of the plurality of leads 1a, a copper alloy is used as the lead frame material. Even when is used, the problem of the crack 11 can be suppressed.

  At this time, the through hole 1d is preferably formed as small as possible so that the mechanical strength of the lead itself against lead bending and warping can be maintained. However, in a small and non-lead type semiconductor package such as QFN5, the width of the lead 1a is very narrow, for example, 0.28 mm, so that the hole diameter is small in the lead 1a by drilling, laser processing or pressing. It is very difficult to form the hole 1d.

  Therefore, the through hole 1d is formed by etching, but if the through hole 1d is simply formed by etching from one side of the lead 1a to form the through hole 1d, the metal portion is greatly wound to penetrate the hole. Therefore, the mechanical strength of the lead 1a is weakened.

  Therefore, in the present embodiment, as shown in FIG. 4, by forming the through-hole 1d by shaving from the both surfaces of the lead 1a toward the inside by half-etching, the upper surface 1b and the mounting surface 1c The actual through-hole 1d inside can be made smaller than the respective openings 1e and 1f. That is, a desired depth is cut by half-etching from both sides of the lead 1a under predetermined etching conditions, and a through hole 1d is formed when the cutting from both sides penetrates. As a result, a through hole 1d having a small hole diameter can be formed.

  By forming the through hole 1d by half-etching from both sides of the lead 1a in this way, the through hole 1d is formed as small as possible so that the mechanical strength of the lead itself can be maintained, leaving many metal portions. It becomes possible. When the through hole has a straight shape, no metal portion remains in the region inside the opening diameter. On the other hand, in the case of the present embodiment, half etching is performed from both sides of the lead 1a, and the etching process is stopped when the lead 1a penetrates. Therefore, as shown in FIG. Can remain. That is, the mechanical strength of the lead 1a can be improved as compared with the case where the through hole is formed in a straight shape by the amount of the remaining metal portion.

  At this time, in the present embodiment, as shown in FIG. 4, the hole diameter (A) of the opening 1e of the upper surface 1b of the lead 1a in the through hole 1d and the hole diameter (B) of the opening 1f of the mounting surface 1c are as follows. They are different (A ≠ B). This is because when the hole diameters of the openings 1e and 1f are the same (A = B) on the upper surface 1b side and the mounting surface 1c side, the through holes 1d are formed in the depth direction with the same amount of scraping from both sides. This is because the hole diameter (C) becomes larger than necessary and the mechanical strength of the lead itself decreases. Therefore, in order to avoid this, half-etching is performed under etching conditions in which the hole diameters of the openings 1e and 1f change (A ≠ B) between the upper surface 1b and the mounting surface 1c of the lead 1a. That is, half-etching is performed on the upper surface 1b side and the mounting surface 1c side by changing the etching conditions such as the etching time and the flow rate of the etching solution.

  Therefore, as shown in FIG. 5, the hole diameter (A) of the opening 1e on the upper surface 1b of the through hole 1d is preferably larger than the hole diameter (B) of the opening 1f of the mounting surface 1c (A> B). .

  As shown in the cross-sectional shape in the width direction of the lead 1a (FIG. 5), under the etching conditions when etching the side surface 1i of the lead 1a, the etching scraping amount from the mounting surface 1c side is the upper surface 1b. The width (G) of the upper surface 1b of the lead 1a is larger than the width (H) of the mounting surface 1c (G> H). That is, half etching is performed by changing the etching conditions on the upper surface 1b side and the mounting surface 1c side of the lead 1a so that the cross-sectional shape of the lead 1a in the width direction becomes an inverted trapezoid as shown in FIG. This prevents the lead 1a from falling off (removing the lead) from the back surface 3a of the sealing body 3.

  Therefore, the hole diameter (A) of the opening 1e of the upper surface 1b is formed larger than the hole diameter (B) of the opening 1f of the mounting surface 1c in accordance with the size in the width direction of the upper surface 1b and the mounting surface 1c of the lead 1a. Is appropriate.

  For example, assuming that the lead width is 0.28 mm and the lead thickness is 0.125 mm, A (hole diameter of the opening 1e on the upper surface 1b) = 0.17 mm, B (hole diameter of the opening 1f on the mounting surface 1c) shown in FIG. Assuming that = 0.1 mm, C (diameter of the through-hole 1d) can be formed at 0.03 mm.

  In addition, when Sn-Bi plating is adopted as the exterior plating 12 applied to the lead 1a, as shown in FIG. 14, in this embodiment, the film thickness of Sn-Bi plating is 0.01 mm. By forming the diameter (C) of the narrowest portion of the through hole 1d to be larger than 20 μm (0.02 mm), it is possible to prevent the through hole 1d from being blocked by the Sn—Bi plating film.

  From the above, the through hole 1d is larger than twice the thickness of the exterior plating 12 and smaller than the hole diameter (A) of the opening 1e as shown in FIG. Compared to the case where 1d is not blocked by the exterior plating 12 and has a straight shape as shown in FIG. 15A, a larger amount of metal can be secured in the region inside the opening 1e by the amount of the remaining portion 20. Thereby, the mechanical strength of the lead 1a can be improved and the mounting strength by the temperature cycle test can be improved. More preferably, as shown in FIG. 15 (c), it is larger than twice the thickness of the exterior plating 12 and smaller than the hole diameter (B) of the opening 1f, so that it is larger than that of FIG. 15 (b). As many metal portions as the remaining portions 21 can be secured in the region inside the opening 1e. As a result, the mechanical strength of the lead 1a and the mounting strength by the temperature cycle test can be improved as compared with the case of FIG.

  Next, FIG. 6 illustrates a preferable formation position of the through hole 1d on the upper surface 1b of the lead 1a. The distance (D) from the edge of the sealing body 3 to the through hole 1d is determined from the through hole 1d. It is preferable to form it at a position that is longer than the distance (F) to the tip of the lead 1a (D> F).

  This is because when the resin burr is formed in the through-hole 1d, the subsequent exterior plating 12 is not formed. However, by using this embodiment, the cavity of the resin molding die (not shown) is sealed during resin sealing. The resin burr due to the sealing resin that has flowed out of the lead 1a prevents the inconvenience of reaching the through hole 1d on the upper surface 1b of the lead 1a and closing the through hole 1d.

  Therefore, by forming the through hole 1d at a position where D> F, the hole can be a through hole 1d surrounded by the inner wall of the entire circumference, and by taking a long distance (D), Generation | occurrence | production of the malfunction that a resin burr enters the through-hole 1d and plugs the through-hole 1d can be prevented.

  Specifically, since the outflow length of the resin burr from the edge of the sealing body 3 is about several tens of μm, the distance (D from the edge of the sealing body 3 to the through hole 1d on the upper surface 1b of each lead (D ) Of 20 μm (0.02 mm) or more, it is possible to prevent the resin burr from entering the through-hole 1d and causing a mounting failure.

  In the QFN 5 of the present embodiment, each of the plurality of leads opens through the upper surface 1b and the mounting surface 1c of the lead 1a, and has a through hole 1d formed by half etching from both sides of the upper surface 1b and the mounting surface 1c. By having it, the mechanical strength of the lead itself can be maintained and a small through hole 1d can be formed.

  As a result, as shown in FIG. 7, when the solder 8 is interposed between the lead 1a of the QFN 5 and the terminal 7a of the mounting board 7 and the QFN 5 is mounted on the mounting board 7 by solder connection, the solder 8 is inserted into the through hole. The lead 1a can be passed through the upper surface 1b of the lead 1a. Thereby, the mounting strength of the QFN 5 can be increased. On the surface of the mounting substrate 7, a terminal 7a and a solder resist film 7b, which is an insulating film surrounding the terminal 7a, are formed.

  Further, since the solder 8 is disposed in the through hole 1d formed in the lead 1a, and this solder 8 wraps around to the upper surface 1b of the lead 1a, stress due to thermal expansion / contraction is generated in the temperature cycle test, and the mounting substrate 7 Even if the warpage 10 is formed, the lead 1a and the solder 8 are locked by the pillars of the solder 8 disposed in the through hole 1d, so that cracks 11 as shown in the comparative example of FIG. Can be prevented. As a result, the mounting strength of the QFN 5 can be improved, and the temperature cycle performance can be improved.

  Further, when the QFN 5 is mounted on the mounting substrate 7 by solder connection, as shown in FIG. 8, each of the leads 1a is mounted on the mounting substrate via the solder 8 disposed outside the center in the extending direction. 7, the amount of solder 8 under the lead 1 a is reduced. Therefore, when the solder 8 is melted, the solder 8 does not reach the adjacent lead 1 a, and the lead by the solder 8 Inter-bridge formation can be prevented.

  That is, when the solder 8 is disposed between the lead 1a of the QFN 5 and the terminal 7a of the mounting substrate 7, the solder 8 is interposed only in the vicinity of the tip portion where the through hole 1d of the lead 1a is formed. is there. Since the solder 8 between the lead 1a and the terminal 7a is visually inspected after mounting, it is preferable to arrange the solder 8 only in the vicinity of the outer end of the lead 1a so that visual confirmation is possible. .

  Thus, each of the plurality of leads 1a of the QFN 5 is solder-connected to the terminal 7a of the mounting substrate 7 via the solder 8 arranged outside the center in the extending direction of each of the leads. It is possible to prevent the formation of a solder short by preventing the formation of a bridge. As a result, the mounting reliability of the QFN 5 can be improved.

  Next, modified examples shown in FIGS. 9 to 11 will be described. The semiconductor device of the modification shown in FIGS. 9 to 11 is a SON 9 in which a plurality of leads 1 a are arranged along two opposing sides of the four sides of the peripheral portion of the back surface 3 a of the rectangular sealing body 3. is there.

  Also in such a SON 9, each of the plurality of leads has a through-hole 1d that is open to the upper surface 1b and the mounting surface 1c of the lead 1a and is formed by half-etching from both sides of the upper surface 1b and the mounting surface 1c. Therefore, the mechanical strength of the lead itself can be maintained and the small through hole 1d can be formed, and the mounting strength of the SON 9 can be increased as in the case of the QFN5. Furthermore, as with QFN5, the temperature cycle performance of SON9 can be improved.

  Next, a method for manufacturing the QFN 5 (semiconductor device) of the present embodiment will be described.

  First, a lead frame (not shown) having a plurality of device regions and having through holes 1d formed in each of the plurality of leads 1a in each device region is prepared.

  The through-hole 1d of each lead 1a is formed by half-etching under different etching conditions from the upper surface 1b side and the mounting surface 1c side of the lead 1a. For example, the half etching process is performed under the etching conditions in which the hole diameters of the openings 1e and 1f change (A ≠ B) as shown in FIG. 5 between the upper surface 1b and the mounting surface 1c. That is, the half etching process is performed on the upper surface 1b side and the mounting surface 1c side by changing the etching conditions such as the etching time and the flow rate of the etching solution.

  Further, half etching is performed by changing the etching conditions on the upper surface 1b side and the mounting surface 1c side of the lead 1a so that the cross-sectional shape of each lead 1a in the width direction becomes an inverted trapezoid (G> H) as shown in FIG. By performing the processing, it is possible to prevent the lead 1a from dropping out (lead missing) on the back surface 3a of the sealing body 3 after the assembly of the package.

  Thereafter, die bonding is performed. That is, the semiconductor chip 2 is mounted on each tab 1h via the die bonding material 6, and the semiconductor chip 2 is fixed.

  Wire bonding is performed after die bonding. That is, the pads 2a of the semiconductor chip 2 and the corresponding step portions 1g of the leads 1a are electrically connected by the wires 4.

  Resin molding is performed after wire bonding. Since the QFN 5 of the present embodiment is a tab-embedded semiconductor package, here, as shown in FIG. 3, the mounting surface 1c of each of the leads 1a is exposed at the peripheral portion of the back surface 3a of the sealing body 3. In addition, the sealing body 3 is formed by resin-sealing the semiconductor chip 2, the tab 1h, and the plurality of wires 4 so that the tab 1h is not exposed.

  At that time, in each lead 1a, as shown in FIG. 6, the distance (D) from the edge of the sealing body 3 to the through hole 1d is longer than the distance (F) from the through hole 1d to the tip of the lead 1a. By forming the position (D> F) and the distance (D) to be 20 μm or more, the resin burr formed by the sealing resin flowing out from the cavity of the resin molding die during resin sealing can be obtained. Generation | occurrence | production of the malfunction of entering into the through-hole 1d and plugging up the through-hole 1d can be prevented.

  After the resin sealing, each of the leads 1a is separated from the lead frame and separated into individual pieces, thereby completing the assembly of the QFN 5 shown in FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the QFN 5 is a tab embedded type semiconductor package has been described. However, the QFN 5 may be a tab exposed type semiconductor package in which the tab 1 h is exposed on the back surface 3 a of the sealing body 3. .

  The present invention is suitable for an electronic device that performs solder mounting.

It is a perspective view which shows an example of the structure of the semiconductor device of embodiment of this invention. FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1. FIG. 2 is a back view showing the structure of the semiconductor device shown in FIG. 1. FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a shape of a through hole in a lead of the semiconductor device illustrated in FIG. 1. FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a shape of a through hole in a width direction of a lead of the semiconductor device illustrated in FIG. 1. FIG. 2 is an enlarged partial plan view showing an example of a position of a through hole of a lead of the semiconductor device shown in FIG. 1. It is sectional drawing which shows an example of the mounting structure of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view showing a mounting structure of a modification of the semiconductor device shown in FIG. 1. It is a top view which shows the structure of the semiconductor device of the modification of embodiment of this invention. FIG. 10 is a side view showing the structure of the semiconductor device of the modification shown in FIG. 9. FIG. 10 is a back view showing the structure of the semiconductor device of the modification shown in FIG. 9. It is sectional drawing which shows the mounting structure of the semiconductor device of a comparative example. It is sectional drawing which shows the generation | occurrence | production state of the crack in the mounting structure of the comparative example shown in FIG. FIG. 2 is an enlarged partial cross-sectional view showing an example of a structure after exterior plating is formed on leads of the semiconductor device shown in FIG. 1. (A), (b), (c) is the expanded partial sectional view which shows the comparative example (a) and the modification (b), (c) of the shape of the through-hole in the lead | read | reed of the semiconductor device shown in FIG.

Explanation of symbols

1a Lead 1b Upper surface 1c Mounting surface (part)
1d Through hole 1e, 1f Opening 1g Stepped portion 1h Tab 1i Side surface 2 Semiconductor chip 2a Pad (surface electrode)
2b Main surface 2c Back surface 3 Sealed body 3a Back surface 4 Wire 5 QFN (semiconductor device)
6 Die bond material 7 Mounting substrate 7a Terminal 7b Solder resist film 8 Solder 9 SON (semiconductor device)
10 Warpage 11 Crack 12 Exterior plating 20, 21 Remaining part

Claims (13)

A semiconductor chip having a plurality of surface electrodes formed on the main surface;
A sealing body for sealing the semiconductor chip;
A plurality of leads electrically connected to the front surface electrode of the semiconductor chip and disposed around the semiconductor chip, and each of which is exposed on the back surface of the sealing body;
Each of the plurality of leads has a through hole that opens to the upper surface and the mounting surface of the lead, and the through hole is a hole formed by half-etching from both sides of the upper surface and the mounting surface. A featured semiconductor device. 2. The semiconductor device according to claim 1, wherein a hole diameter of the opening on the upper surface of the lead in the through hole is different from a hole diameter of the opening on the mounting surface.   3. The semiconductor device according to claim 2, wherein a hole diameter of the opening on the upper surface of the through hole is larger than a hole diameter of the opening on the mounting surface.   2. The semiconductor device according to claim 1, wherein a distance from an edge of the sealing body to the through hole is longer than a distance from the through hole to the tip of the lead on the upper surface of each of the plurality of leads. A semiconductor device.   2. The semiconductor device according to claim 1, wherein a distance from an edge of the sealing body to the through hole on each of the upper surfaces of the plurality of leads is 20 μm or more.   2. The semiconductor device according to claim 1, wherein a hole diameter at a narrowest portion in the through hole is larger than 20 [mu] m.   2. The semiconductor device according to claim 1, wherein the back surface of the sealing body is formed in a quadrangular shape, and the plurality of leads are arranged along each of the four sides of the peripheral portion of the back surface. apparatus.   2. The semiconductor device according to claim 1, wherein a back surface of the sealing body is formed in a quadrangular shape, and the plurality of leads are arranged along any two opposing sides of the four sides of the peripheral portion of the back surface. A semiconductor device characterized by that. A semiconductor chip having a plurality of surface electrodes formed on the main surface;
A sealing body for sealing the semiconductor chip;
A plurality of leads electrically connected to the front surface electrode of the semiconductor chip and disposed around the semiconductor chip, and each of which is exposed on the back surface of the sealing body;
Each of the plurality of leads has a through hole that opens to the upper surface and the mounting surface of the lead, and the through hole is a hole formed by half-etching from both sides of the upper surface and the mounting surface,
The semiconductor device is characterized in that the plurality of leads are mounted on a mounting substrate via solder disposed outside the center in the extending direction. 10. The semiconductor device according to claim 9, wherein a hole diameter of the opening on the upper surface of the lead in the through hole is different from a hole diameter of the opening on the mounting surface.   11. The semiconductor device according to claim 10, wherein a hole diameter of the opening on the upper surface of the through hole is larger than a hole diameter of the opening on the mounting surface.   10. The semiconductor device according to claim 9, wherein a distance from an edge of the sealing body to the through hole is longer than a distance from the through hole to the tip of the lead on the upper surface of each of the plurality of leads. A semiconductor device.   10. The semiconductor device according to claim 9, wherein a distance from an edge portion of the sealing body to the through hole on the upper surface of each of the plurality of leads is 20 μm or more.

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