JP2003338601A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability and to standardize a lead frame. <P>SOLUTION: A device is provided with a plurality of inner leads 1b extending around a semiconductor chip 2, a tape substrate 5 which supports the semiconductor chip 2 and is bonded to ends of the inner leads 1b, a wire connecting a pad formed on the main surface 2c of the semiconductor chip 2 with the inner leads 1b, a sealing part formed by resin-sealing the semiconductor chip 2 and a wire, and a plurality of outer leads which are connected to the inner leads 1b and protrude outside in four directions from the sealing part. A relation between a short length (a) of the semiconductor chip 2 and a clearance (b) of the inner lead 1b whose tip is most apart from the semiconductor chip 2 with the semiconductor chip 2 is a≤2b. Thus, a pad pitch becomes narrow, the small semiconductor chip 2 can be loaded and the lead frame can be standardized. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to improve reliability of a semiconductor device having a small semiconductor chip with a narrow pad pitch.

[0002]

2. Description of the Related Art As a technique for fixing an inner lead to a metal plate or a ceramic plate with an adhesive or the like, Japanese Patent Application Laid-Open No. 8-1
16012, JP-A-5-160304, JP-A-5-36862, and JP-A-11-289040.
Japanese Patent Laid-Open No. 11-514149 and Japanese Patent Laid-Open No. 7-
This is described in JP-A-153890, JP-A-6-291217 and JP-A-5-235246.

First, in JP-A-8-116012, a resin for fixing an inner lead to an aluminum plate through an adhesive by using an aluminum plate as a heat dissipation plate and providing an insulating layer on the surface of the aluminum plate. A sealed semiconductor device is described. In this semiconductor device, heat dissipation is improved,
The purpose is to reduce material costs and manufacturing time.

Japanese Unexamined Patent Publication (Kokai) No. 5-160304 discloses a semiconductor device having a structure in which an aluminum plate is used as a heat dissipation plate and leads are bonded to the aluminum plate with an adhesive for the purpose of improving thermal characteristics. .

Japanese Unexamined Patent Publication (Kokai) No. 5-36862 discloses a semiconductor device having a structure in which a ceramic plate is bonded to an inner lead, and heat from a semiconductor chip is radiated to the outside through the ceramic plate and the inner lead. The purpose is to improve the heat dissipation of the semiconductor device.

Japanese Patent Laid-Open No. 11-289040 discloses a lead frame in which an inner lead is joined to one surface of a heat sink through an electrically insulating layer and an adhesive layer, and a semiconductor device using the lead frame has improved quality. It is described for the purpose of reducing the manufacturing cost.

Japanese Patent Publication No. 11-514149 discloses an electronic package having a structure in which a semiconductor chip and a lead are fixed to a heat slug whose surface is coated with an electrically insulating anode treatment for the purpose of improving thermal characteristics. Has been done.

Japanese Unexamined Patent Publication (Kokai) No. 7-153890 discloses a lead frame for a semiconductor device in which an inner lead is fixed to a heat dissipation plate made of a metal plate subjected to an insulation treatment with an adhesive. The purpose is to improve heat dissipation, speed up signal processing, and prolong the life of semiconductor devices.

Japanese Unexamined Patent Publication (Kokai) No. 6-291217 discloses a heat dissipation type lead frame in which a ceramic plate is used as a heat dissipation plate, and inner leads are fixed to the ceramic plate via an adhesive. It is intended to suppress residual stress due to heat when the package structure is used and prevent deformation of the frame shape at the manufacturing stage.

In Japanese Patent Laid-Open No. 5-235246, the main surface of a semiconductor chip is fixed to one surface of an insulating tape with an adhesive, and the inner lead is fixed to the other surface with an adhesive. A semiconductor device having a structure in which a surface electrode of a semiconductor chip is exposed in a hole of an insulating tape and an inner lead and a surface electrode are connected by a wire through the hole is described. The purpose is to speed up transmission.

[0011]

However, Japanese Unexamined Patent Publication No.
The techniques described in the above-mentioned seven publications except 235246 publication are intended to improve heat dissipation by using a metal plate or a ceramic plate, and fix the inner leads to the metal plate or the ceramic plate via an adhesive. Multi-pin technology,
Moreover, the idea of using it for a semiconductor device having a narrow pad pitch is not described.

Further, Japanese Patent Application Laid-Open No. 5-235246 discloses a technique of fixing the inner leads to an insulating tape. However, the structure described here (one surface of the insulating tape is the main surface of the semiconductor chip). And the inner lead is fixed to the other surface, the pad of the semiconductor chip is exposed in the hole of the insulating tape, and the inner lead and the pad are connected by the wire through the hole). The small size and the large number of pins causes a problem that the tape area on the chip is reduced and the area for forming holes in the insulating tape is eliminated.

Therefore, there is a problem that it is difficult to realize a small chip and multi-pin structure with the structure described in Japanese Patent Laid-Open No. 5-235246.

Further, in the structure disclosed in Japanese Patent Laid-Open No. 235246/1993, since holes must be formed in the insulating tape, an insulating tape having a size corresponding to the chip size is required. It is necessary to prepare a lead frame to which is attached, and it is a problem that the lead frame cannot be standardized.

An object of the present invention is to provide a semiconductor device which has a narrowed pad pitch and improved reliability.

Further, another object of the present invention is to provide a semiconductor device which enables standardization of a lead frame.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor device of the present invention has a plurality of inner leads extending around the semiconductor chip and a thin plate-like insulating property that supports the semiconductor chip and is joined to the ends of the inner leads. A member, a conductive wire that connects the surface electrode of the semiconductor chip and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, The semiconductor chip has a plurality of outer leads that are continuous with the inner leads and are exposed from the sealing portion. The length of the short side of the main surface of the quadrangle of the semiconductor chip is such that the tip is farthest from the center line in the plane direction of the semiconductor device. The distance is equal to or less than twice the distance from the tip of the inner lead arranged at the location to the semiconductor chip.

Further, the semiconductor device of the present invention has a plurality of inner leads extending around the semiconductor chip, and a thin plate-like insulating material that supports the semiconductor chip and is joined to the ends of the inner leads. A member, a conductive wire that connects the surface electrode of the semiconductor chip and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, The semiconductor chip has a plurality of outer leads that are continuous with the inner leads and are exposed from the sealing portion. It is not less than the distance from the tip of the inner lead arranged at the location to the semiconductor chip and not more than twice this distance.

Further, the semiconductor device of the present invention has a plurality of inner leads extending around the semiconductor chip, and a thin plate-like insulating material that supports the semiconductor chip and is joined to the end portions of the inner leads. A member, a conductive wire that connects the surface electrode of the semiconductor chip and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, A plurality of outer leads connected to the inner leads and exposed from the sealing portion, and the installation pitch of the surface electrodes of the semiconductor chip is ½ of the minimum value of the pitch of the tips between the adjacent inner leads. It is the following.

In the semiconductor device of the present invention, an insulating member having an upper surface and a lower surface, a semiconductor integrated circuit chip having a plurality of bonding pads, and the semiconductor integrated circuit chip in the plane direction of the semiconductor integrated circuit chip. A first, a second, a third and a fourth conductive lead arranged on the left side, the right side, the upper side and the lower side respectively, each of the first to fourth conductive leads being the insulating member. A first end having a lower surface connected to the surface of the first pad and an upper surface in a wire connectable state with one of the bonding pads, the first end of each of the first and second conductive leads being The dimension of a portion of the virtual line that crosses the semiconductor integrated circuit chip is arranged along a virtual line that extends across the semiconductor integrated circuit chip from the left side to the right side of the semiconductor integrated circuit chip. The total of the distance between the semiconductor integrated circuit chip and the first conductive lead and the distance between the semiconductor integrated circuit chip and the second conductive lead is equal to or less than the sum, and the first end Section, the semiconductor integrated circuit chip, and the insulating member, and a resin that exposes the other end opposite to the first end.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

In the following embodiments, when there is a need for convenience, description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, One has a relationship such as a modification of some or all of the other, details, and supplementary explanation.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.) of elements, it is clearly limited to a specific number when explicitly stated and in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not always essential unless otherwise specified or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., except when explicitly stated or when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included. This also applies to the above numerical values and ranges.

Further, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(First Embodiment) FIG. 1 is a diagram showing an example of the structure of a semiconductor device according to the first embodiment of the present invention.
Is a sectional view, (b) is a plan view, FIG. 2 is a partial plan view showing an example of the distance between the semiconductor chip and the inner leads in the semiconductor device shown in FIG. 1, and FIG. 3 is a view of the semiconductor chip in the semiconductor device shown in FIG. FIG. 4 is an enlarged partial plan view showing an example of the pad pitch and the lead pitch of the inner leads.
FIG. 5 is a partial plan view showing an example of the structure of a matrix frame used for assembling the semiconductor device shown in FIG. 6 is a partial plan view showing an example of the structure after die bonding in the assembly of the semiconductor device using the matrix frame shown in FIG.
7 is an enlarged partial sectional view showing the structure of a section taken along line BB, FIG. 8 is an enlarged partial sectional view showing the structure after die bonding of a modified example with respect to FIG. 7, and FIG. 9 uses the matrix frame shown in FIG. FIG. 11 is a partial plan view showing an example of the structure after wire bonding in the assembly of the semiconductor device partially broken away, FIG. 10 is an enlarged partial cross-sectional view showing the structure of the cross section taken along the line CC of FIG. 9, and FIG. An enlarged partial cross-sectional view showing a structure after wire bonding of a modified example with respect to FIG.
12 is a partial plan view showing an example of the structure after resin sealing in the assembly of the semiconductor device using the matrix frame shown in FIG. 4, partially broken, and FIG. 13 is a DD view shown in FIG.
FIG. 14 is a partial plan view showing an example of the structure of the frame body of the single-row lead frame used for assembling the semiconductor device shown in FIG. 1, and FIG. FIG. 16 is an enlarged partial plan view showing the structure of a single-row lead frame in which an insulating member is attached to the frame body. FIG. 16 is an example of a structure after wire bonding in assembling a semiconductor device using the single-row lead frame shown in FIG. 17 is an enlarged partial plan view showing an example of the structure after resin sealing in assembling a semiconductor device using the single-row lead frame shown in FIG. 15, and FIG. 18 is a single-row lead shown in FIG. FIG. 19 is a side view showing an example of a structure after cutting and molding in assembling a semiconductor device using a frame. FIG. 19 shows a mounted state of the semiconductor device shown in FIG. 1 and another semiconductor device. Enlarged partial plan view showing an example, FIG. 2
0 is an enlarged partial cross-sectional view showing the structure of a modified example with respect to FIG.
21 is a sectional view showing the structure of the semiconductor device of the modification of the first embodiment of the present invention, FIG. 22 is a sectional view showing the detailed structure of the semiconductor device of the modification of FIG. 21, and FIG. 23 is shown in FIG. FIG. 24 is a sectional view showing a detailed structure of a modified semiconductor device, FIG. 24 is a sectional view showing a detailed structure of a modified semiconductor device shown in FIG. 21, and FIG. 25 is a modified semiconductor device of the first embodiment of the present invention. It is a figure which shows the structure of a certain QFN, (a) is sectional drawing, (b) is a bottom view.

The semiconductor device according to the first embodiment is a resin-sealed type and a surface-mounted type, and has a relatively small size and a narrow pad pitch (for example, a pad pitch of 80 μm or less). The chip 2 is incorporated, and in the first embodiment, as an example of this semiconductor device, a QFP (Quad Flat Package) 6 shown in FIG. 1 will be taken up and described.

Furthermore, the QFP 6 of the first embodiment is a multi-pin type.

Explaining the basic structure of the QFP6,
As shown in FIGS. 1A and 1B, a plurality of inner leads 1 b extending around the semiconductor chip 2 and the semiconductor chip 2 are provided.
A thin plate-like insulating member that supports the inner leads 1b and is joined to the ends of the inner leads 1b, the pads 2a that are surface electrodes formed on the main surface 2c of the semiconductor chip 2, and the inner leads 1b corresponding thereto. A bonding wire 4 for electrically connecting the semiconductor chip 2, the wire 4 and the insulating member with a sealing portion 3 formed by resin-sealing, and connected to the inner lead 1b and sealing. It is composed of a plurality of outer leads 1c which are external terminals protruding from the portion 3 in the four directions, and the outer leads 1c are bent into a gull wing shape.

The QFP 6 is a tape substrate 5 in which the insulating member is a tape substrate 5a made of, for example, an insulating epoxy tape base material 5a and an insulating adhesive layer 5b made of a thermoplastic resin. Since the semiconductor chip 2 is supported by the supporting surface 5c and the end portions of the inner leads 1b are fixed to the insulating member 5 by the adhesive layer 5b,
The structure is such that wire flow and fluttering of the inner leads 1b due to the flow of molding resin during molding (resin sealing) are suppressed.

Therefore, the feature of the QFP 6 of the first embodiment is that, in addition to the fixing of the inner leads 1b by the thin plate-shaped tape substrate 5, as shown in FIG. 2, the rectangular main surface 2c of the semiconductor chip 2 is short. The length (a) of the side is the center line 6a in the plane direction of the QFP 6 with the tip (center line 6a of the X axis or the Y axis).
Is less than twice the distance (b) from the tip of the inner lead 1b arranged at the farthest position from the semiconductor chip 2.

That is, the short side length (a) of the semiconductor chip 2
And a clearance (b) between the semiconductor chip 2 and the inner lead 1b whose tip is most distant from the semiconductor chip 2.
And the relation is a ≦ 2b.

Further, it is preferable that b ≦ a ≦ 2b.

As a result, in the multi-pin QFP 6 on which the semiconductor chip 2 having a small and narrow pad pitch is mounted, the effect of suppressing the wire flow and the fluttering of the inner lead 1b can be surely exerted.

As a result, the reliability of the QFP 6 can be improved.

Further, in the QFP 6, the semiconductor chip 2 can be mounted on the tape substrate 5 even if the size of the semiconductor chip 2 becomes small. Therefore, the matrix frame 1 (see FIG. 4) or a single row is provided for each chip size. It is not necessary to prepare a lead frame such as the lead frame 1g (see FIG. 15), and as a result, the lead frame can be standardized.

Further, in FIG. 3, in the QFP 6, the pad pitch (P) of the semiconductor chip 2 having a narrow pad pitch mounted therein and the tip pitch of the inner lead 1b having the smallest (narrow) lead pitch between adjacent tips are shown. The relationship with (L) is shown, and P ≦ L / 2.

That is, since the pad pitch of the semiconductor chip 2 is less than 1/2 of the minimum value of the tip pitch between the adjacent inner leads 1b, it is effective for the QFP 6 mounted with the semiconductor chip 2 having a narrow pad pitch. You can improve your sex.

The pad pitch (P) of the semiconductor chip 2 is, for example, 60 μm, and the inner lead 1b
The minimum value (L) of the tip pitch of is, for example, 180 μm, and in this case, (P = 60 μm) ≦ (L = 180 μ
m) / 2.

The QFP 6 of the first embodiment has a narrow pad pitch and a large number of pins. Therefore, the effectiveness for the QFP 6 is obtained when the size of the sealing portion 3 in the plane direction is, for example, 20 mm × 20 mm or more and the number of pins (the number of external terminals) is 176 or more. ,
High effectiveness can be obtained.

However, the pad pitch (P), the minimum value (L) of the tip pitch of the inner leads 1b, the size of the sealing portion 3 in the plane direction, and the number of pins are not limited to the above numerical values. Absent.

The main surface 2c of the semiconductor chip 2 is
A desired semiconductor integrated circuit is formed on the main surface 2c, and the pads 2a formed on the main surface 2c and the inner leads 1 corresponding to the pads 2a are formed.
b is connected by a wire 4, and the outer lead 1c connected to the inner lead 1b is output to the outside as an external terminal of the QFP 6.

Therefore, the signal is transmitted between the semiconductor chip 2 and the outer lead 1c by the wire 4 and the inner lead 1b.
Done through.

The wire 4 is, for example, a gold wire.

Further, the inner leads 1b and the outer leads 1c are, for example, iron-Ni alloys or copper alloys.

The sealing portion 3 is formed by molding (resin sealing) using, for example, an epoxy-based thermosetting resin, and then thermosetting it.

Next, a method of manufacturing the QFP 6 of the first embodiment will be described.

A case where the matrix frame 1 shown in FIG. 4 is used as the lead frame used in the method of manufacturing the QFP 6 will be described first.

First, a plurality of inner leads 1b are joined to the inner leads 1b, and a thin plate-shaped tape substrate 5 (insulating member) capable of supporting the semiconductor chip 2 and being joined to the ends of the inner leads 1b. A matrix frame 1 shown in FIG. 4 in which a plurality of package regions 1h including a plurality of outer leads 1c are formed in a matrix arrangement is prepared.

That is, in each package region 1h of the frame body 1a made of iron-Ni alloy or copper alloy,
As shown in FIG. 5, the matrix frame 1 to which the tape substrate 5 is attached is prepared.

For example, a tape substrate 5 having an adhesive layer 5b formed by applying an adhesive of a thermoplastic resin to the tape base 5a is prepared, and each package area 1h of the matrix frame 1 is prepared.
In, the end portion of each inner lead 1b and the tape substrate 5 are fixed by the thermocompression bonding method via the adhesive layer 5b.

At this time, the adhesive layer 5 is formed over the surface of the tape substrate 5 on the inner lead arrangement side, that is, the entire chip supporting surface 5c.
b, and each inner lead 1 is formed by this adhesive layer 5b.
b and the tape substrate 5 are joined.

As a result, the matrix frame 1 shown in FIG. 4 is completed.

In addition, in one matrix frame 1,
A package region 1h corresponding to one QFP 6 is formed in a matrix arrangement, and an insulating adhesive layer 5b is formed at an end of each inner lead 1b in each package region 1h.
The tape base material 5a is joined via the.

In each package area 1h, a plurality of inner leads 1b in the four directions around the tape substrate 5 and outer leads 1c, which are external terminals integrally formed so as to be continuous with the inner leads 1b, are formed. A dam bar 1i for preventing the mold resin from flowing out is arranged, and each outer lead 1c is supported by the frame portion 1f of the frame body 1a.

Furthermore, the matrix frame 1 is formed on the frame portion 1f during die bonding or wire bonding.
Slot 1d for guiding and positioning hole 1e for transporting paper
Are formed.

Thereafter, as shown in FIGS. 6 and 7, die bonding (also referred to as pellet bonding or chip mounting) for mounting the semiconductor chip 2 on the chip supporting surface 5c of the tape substrate 5 is performed in each package region 1h.

That is, the back surface 2b of the semiconductor chip 2 and the chip supporting surface 5c of the tape substrate 5 are fixed.

At this time, the semiconductor chip 2 may be fixed by the adhesive layer 5b of the tape substrate 5 as shown in FIG. 7, or a resin such as silver paste as in the modification shown in FIG. You may fix with the paste 8.

In the tape substrate 5 of each package area 1h, the semiconductor chip 2 is mounted on the surface of the tape substrate 5 on the inner lead arrangement side, and the semiconductor chip 2 is also mounted.
The length of the short side of the main surface 2c of the quadrangle is not more than twice the distance from the tip of the inner lead 1b arranged at the tip farthest from the center line 6a in the plane direction of the QFP 6 to the semiconductor chip 2. To be installed.

That is, the relationship of a≤2b shown in FIG. 2 is established.

The semiconductor chip 2 incorporated in the QFP 6 of the first embodiment is small in size, and
The pad pitch is, for example, a narrow pad pitch of less than 80 μm, preferably 60 μm or less.

Thereafter, as shown in FIGS. 9 and 10, the pad 2a of the semiconductor chip 2 and the inner lead 1b corresponding thereto are connected by wire bonding.

That is, wire bonding is performed by using the bonding wire 4 such as a gold wire.
The pad 2a and the corresponding inner lead 1b are connected by the wire 4.

The modification shown in FIG. 11 is a case where the glass-containing epoxy substrate 5d is used as the insulating member.

After the wire bonding is completed, the semiconductor chip 2, the wires 4 and the inner leads 1 are formed by the molding method.
b and the tape substrate 5 are resin-sealed to form the sealing portion 3 as shown in FIGS. 12 and 13.

The mold resin used for the mold is, for example, an epoxy thermosetting resin.

After completion of the resin sealing, the protrusion 1 from the sealing portion 3
The 76 outer leads 1c are separated from the frame portion 1f of the frame body 1a of the lead frame 1 by cutting using a cutting mold (not shown), and further, as shown in FIG. Bend into a gull wing shape.

As a result, the QFP6 (semiconductor device) shown in FIG. 1 can be manufactured.

Next, a case where the single-row lead frame 1g shown in FIG. 15 is used as the lead frame for manufacturing will be described.

The single-row lead frame 1g is composed of a plurality of inner leads 1b, a tape substrate 5 which is an insulating member in the form of a thin plate capable of supporting the semiconductor chip 2 while being joined to the ends of the inner leads 1b. A plurality of package regions 1h shown in FIG. 14, which are composed of a plurality of outer leads 1c connected to the leads 1b, are formed in a row so as to form a multiple line.

That is, in each package area 1h of the frame main body 1a shown in FIG. 14, a plurality of package areas 1h including a plurality of inner leads 1b and a plurality of outer leads 1c connected to the inner leads 1b are formed in a row. As in the case of the matrix frame 1 shown in FIG.
Is attached.

Thereafter, die bonding and wire bonding are performed by the same procedure as the manufacturing method using the matrix frame 1 to obtain the state shown in FIG.

Further, the resin is sealed with a mold to obtain the state shown in FIG. 17, and thereafter, cutting molding is performed to obtain the state shown in FIG.
QFP6 shown in FIG.

The completed QFP 6 is, as shown in FIG. 19, a SOP (Small Ou) which is another semiconductor package.
It is possible to mix-mount the same together with the electronic package 9 on the same mounting board 7 by, for example, solder reflow.

Next, a modification of the first embodiment shown in FIGS. 20 to 25 will be described.

FIG. 20 shows an example in which a ceramic substrate 5e is used as a thin plate-shaped insulating member.
e and the inner lead 1b are joined by the adhesive layer 5b. Even if the ceramic substrate 5e is used, the tape substrate 5
It is possible to obtain the same effect as when using.

The QFP 6 shown in FIG. 21 has a structure in which a metal plate 5f is attached to the surface of the insulating member such as the tape substrate 5 opposite to the surface (chip supporting surface 5c) on the inner lead arrangement side. 22 to 24 show specific examples thereof.

In FIG. 22, the adhesive layer 5b is used as an insulating member.

That is, an insulating adhesive is applied to one surface of the metal plate 5f to form the adhesive layer 5b.
The inner lead 1b and the metal plate 5f are joined together via b.

In FIG. 23, the adhesive layer 5b is of a two-layer type composed of a hard adhesive layer 5g and a soft adhesive layer 5h, and the inner lead 1b and the hard adhesive layer 5g are joined by the soft adhesive layer 5h. In addition, the hard adhesive layer 5g prevents the inner lead 1b from penetrating to the metal plate 5f side due to burrs.

Further, in FIG. 24, adhesive layers 5b are formed on both front and back surfaces of the tape base 5a, whereby the inner lead 1b and the tape base 5a are joined and the tape base 5a.
And the metal plate 5f are joined together.

In addition, in the case of the modified examples shown in FIGS. 21 to 24, in addition to the same effect as the case of using the tape substrate 5 shown in FIG. The heat dissipation can be improved.

In the modification shown in FIGS. 25A and 25B, the semiconductor device has a QFN (Quad Flat Non-leaded Packag).
In the case of e) 10, the semiconductor device of the first embodiment can achieve the purpose even with the QFN 10.

As shown in FIG. 25 (b), the QFN 10 has a structure in which the outer leads 1c serving as external terminals are arranged on the peripheral portion of the back surface 3a of the sealing portion 3.
As shown in (a), an insulating member (ceramic substrate 5) such as a tape substrate 5 is provided at the end of the inner lead 1b.
e or a glass-filled epoxy substrate 5d) may be fixed, and the semiconductor chip 2 is fixed to the chip supporting surface 5c thereof.

Also in this QFN 10, the relationship between the semiconductor chip 2 and the inner leads 1b is as shown in FIG.
Alternatively, in addition to this, by setting the conditions of the pad pitch and the tip pitch of the inner leads 1b shown in FIG. 3, the same effect as that of the QFP 6 shown in FIG. 1 can be obtained.

(Second Embodiment) FIG. 26 is a sectional view showing an example of the structure of a semiconductor device according to a second embodiment of the present invention.
26 is a partial sectional view showing an example of a structure of a lead frame used for assembling the semiconductor device shown in FIG. 26, and FIGS. 28 to 33 are partial sectional views showing a structure of a lead frame of a modified example of the second embodiment of the present invention. FIG. 34 is a partial cross-sectional view showing an example of the relationship between the thickness of the semiconductor chip, the insulating member and the adhesive layer when the semiconductor chip is mounted on the insulating member of the lead frame according to the second embodiment of the present invention. 35 and 36 are enlarged partial plan views showing the structure of the lead frame of the modification of the second embodiment of the present invention.

The semiconductor device of the second embodiment shown in FIG. 26 is a QFP 11 having substantially the same basic structure as the QFP 6 of the first embodiment, but the semiconductor device shown in FIG.
And the conditions shown in FIG. 3 are not included.

The basic structure of the QFP 11 is the semiconductor chip 2
A plurality of inner leads 1b extending around the semiconductor chip 2 and a thin plate-like insulating member that supports the semiconductor chip 2 and is joined to the end portions of the respective inner leads 1b;
And a resin paste 8 for joining the insulating member and the adhesive layer 5b for joining the inner lead 1b and the insulating member.
And a bonding wire 4 for connecting the pad 2a of the semiconductor chip 2 and the corresponding inner lead 1b.
And a plurality of outer leads 1 continuous with the inner lead 1b and exposed from the encapsulation part 3, and a encapsulation part 3 formed by encapsulating the semiconductor chip 2 wire 4 and the insulating member with a resin.
It consists of c and.

Therefore, the feature of the QFP 11 of the second embodiment is that the formation location of the adhesive layer 5b and the material or shape of the insulating member are changed.

First, in FIG. 27, the tape substrate 5 is used as the insulating member, and the adhesive layer 5b is arranged only on the lead joint portion 5l on the surface of the tape substrate 5 on the inner lead arrangement side. The tape base material 5a of the substrate 5 and the inner lead 1b are joined by the adhesive layer 5b.

As a result, the amount of the adhesive forming the adhesive layer 5b can be reduced and the cost can be reduced.

Further, FIG. 28 shows a case where a glass-containing epoxy substrate 5d is used as the insulating member, and FIG. 29 shows an adhesive layer when the glass-containing epoxy substrate 5d is used as the insulating member. 5b is arranged only on the lead joint portion 5l on the surface on the inner lead arrangement side of the glass-filled epoxy substrate 5d.

In FIGS. 28 and 29, the glass-containing epoxy substrate 5d and the inner lead 1b are joined by the adhesive layer 5b.

30 and 31 show the case where a glass-filled epoxy substrate 5d is used as the insulating member. The glass-filled epoxy substrate 5d and the inner lead 1 are used.
b is joined by an adhesive layer 5b of a double-sided adhesive tape 5i having a tape base material 5a having adhesive layers 5b arranged on both front and back surfaces.

At this time, FIG. 30 shows the double-sided adhesive tape 5i.
Are arranged over the entire surface (chip supporting surface 5c) of the glass-filled epoxy substrate 5d on the inner lead arrangement side. Further, FIG. 31 shows that the double-sided adhesive tape 5i is provided only on the lead joint portion 5l of the inner lead 1b. Is arranged.

32 and 33, the insulating member is a glass-containing epoxy substrate 5d containing alumina particles 5j, and the glass-containing epoxy substrate 5d and the inner lead 1b are the adhesive layer of the double-sided adhesive tape 5i. It is joined by 5b.

At this time, FIG. 32 shows the double-sided adhesive tape 5i.
Are arranged over the entire surface (chip support surface 5c) on the inner lead arrangement side of the glass-filled epoxy substrate 5d, and FIG. 33 shows the side opposite to the double-sided adhesive tape joining side of the glass-filled epoxy substrate 5d. The metal plate 5f is attached to the surface.

By using the glass-filled epoxy substrate 5d containing the alumina particles 5j as the insulating member, the coefficient of thermal expansion of the glass-filled epoxy substrate 5d can be made closer to that of silicon of the semiconductor chip 2 and the heat radiation can be improved. You can improve the property. Further, as shown in FIG. 33, the heat dissipation can be further improved by attaching the metal plate 5f.

Further, FIG. 34 shows the insulating member as
When the glass-containing epoxy substrate 5d is used (the tape substrate 5 may be used), the thickness (C) of the semiconductor chip 2 becomes larger than the combined thickness (D) of the glass-containing epoxy substrate 5d and the adhesive layer 5b. The structure is such that C>
It is D.

As a result, heat conduction during die bonding of the semiconductor chip 2 can be improved.

Furthermore, since the semiconductor chip 2 is thicker than the combined thickness of the insulating member such as the glass-filled epoxy substrate 5d and the adhesive layer 5b, the thickness of the insulating member can be reduced. The QFP 11 of the second embodiment can be formed thin.

As a result, the material cost can be reduced, and the cost of the QFP 11 can be reduced.

Further, in the modified examples shown in FIGS. 35 and 36, when the tape substrate 5 (the epoxy substrate 5d containing glass may be used) as the insulating member, the tape substrate 5 has through holes 5k of various shapes. It is formed and the mold resin for resin sealing is embedded in the through hole 5k.

FIG. 35 shows the case where a plurality of circular through holes 5k are provided in the tape substrate 5, and FIG. 36 shows the elongated through holes 5k provided in a cross shape.

With the structure shown in FIGS. 35 and 36, it is possible to prevent the inner lead 1b from fluttering, prevent wire flow, and improve the adhesion between the mold resin and the tape substrate 5, thereby improving the reliability of the QFP 11. Can be improved.

The shape and forming region of the through hole 5k in the tape substrate 5 are not particularly limited as long as they are of a size (shape) and a region in which wire flow due to the molding resin is not generated.

According to the QFP 11 of the second embodiment, the end portion of the inner lead 1b is joined to the thin plate-like insulating member such as the tape substrate 5 or the glass-filled epoxy substrate 5d, so that the wire caused by the flow of the mold resin is formed. The flow and inner lead flutter can be suppressed, and as a result, the pad pitch of the inner lead 1b can be narrowed and the wire 4 can be prevented from being broken due to the flutter of the inner lead 1b.

Further, by joining the end portion of the inner lead 1b to the thin plate-shaped insulating member, the tip of the inner lead 1b at the time of solder reflow caused by the difference in thermal expansion coefficient between the mold resin and the inner lead 1b. Expansion and contraction in the vicinity can be suppressed.

Thus, the inner lead 1b of the wire 4 is
It is possible to prevent wire breakage that occurs at the joint with and, as a result, QF
The reliability of P11 can be improved.

In the QFP 11, the inner lead 1b is connected to the thin plate-like insulating member (glass-containing epoxy substrate 5).
d, glass-containing epoxy substrate 5 containing alumina particles 5j
d or the tape substrate 5), the matrix frame 1 (FIG. 4) to which the thin plate-shaped insulating member is attached is compared with the case where the inner lead 1b is fixed to a thin metal plate such as a copper plate. (See FIG. 15) and the single-row lead frame 1g (see FIG. 15) can be made light and low cost.

Further, while the copper plate has a thickness of about 120 μm and the thickness of the semiconductor device at that time is about 2.8 to 3 mm, as in the second embodiment, the thin plate shape is used. Since the insulating member can be formed with a thickness of about 50 μm, the QFP 11 assembled by using the insulating member can have a thickness of about 1 to 1.2 mm.

Therefore, according to the second embodiment, it is possible to realize a light and thin QFP 11 having a large number of pins.

Since the manufacturing method of the QFP 11 of the second embodiment is the same as the manufacturing method of the QFP 6 described in the first embodiment, duplicate description thereof will be omitted.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and does not depart from the scope of the invention. It goes without saying that various changes can be made with.

For example, in the second embodiment, the QFP 11 is taken up as the semiconductor device for description, but the semiconductor device of the second embodiment may be one in which the outer leads 1c other than the QFP 11 project in two directions. .

Further, the semiconductor device and the method of manufacturing the same according to the present invention may have a content obtained by combining the first embodiment and the second embodiment.

[0121]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). The inner lead is joined to the insulating member, and the short side length of the main surface of the semiconductor chip is determined by the distance from the tip of the inner lead located farthest from the center line of the semiconductor device to the semiconductor chip. When the amount is 2 times or less, the effect of suppressing the wire flow and the inner lead flutter due to the flow of the molding resin can be surely exerted by fixing the inner lead to the insulating member. As a result, the reliability of the semiconductor device having the structure in which the inner lead is joined to the insulating member can be improved.

(2). The inner leads are joined to the insulating member, and the short side length of the main surface of the semiconductor chip is determined by the distance from the tip of the inner lead located farthest from the center line of the semiconductor device to the semiconductor chip. By being less than twice, the semiconductor chip can be mounted on the insulating member even if the chip size becomes small, and it is not necessary to prepare a lead frame for each chip size, and as a result, standardization of the lead frame is possible. Can be planned.

(3). By bonding the end of the inner lead to a thin plate-shaped insulating member, it is possible to suppress wire flow and inner lead flutter due to the flow of the molding resin, and as a result, it is possible to reduce the pad pitch of the inner lead. At the same time, it is possible to prevent the wire from breaking due to the flapping of the inner leads.

(4). By joining the end portion of the inner lead to the thin plate-shaped insulating member, it is possible to suppress expansion and contraction of the tip of the inner lead during solder reflow, which occurs due to the difference in thermal expansion coefficient between the mold resin and the inner lead. As a result, it is possible to prevent disconnection that occurs at the joint between the wire and the inner lead, and as a result, the reliability of the semiconductor device can be improved.

(5). When the semiconductor chip is thicker than the combined thickness of the insulating member and the adhesive layer, heat conduction during die bonding can be improved.

(6). Since the thickness of the semiconductor chip is thicker than the total thickness of the insulating member and the adhesive layer, the thickness of the insulating member can be reduced, so that the thickness of the semiconductor device can be reduced. As a result, the material cost can be reduced and the cost of the semiconductor device can be reduced.

[Brief description of drawings]

1A and 1B are views showing an example of a structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 1A is a sectional view,
(B) is a plan view.

2 is a partial plan view showing an example of a distance between a semiconductor chip and an inner lead in the semiconductor device shown in FIG.

3 is an enlarged partial plan view showing an example of a pad pitch of a semiconductor chip and a lead pitch of inner leads in the semiconductor device shown in FIG.

4 is a partial plan view showing an example of a structure of a matrix frame used for assembling the semiconductor device shown in FIG.

5 is an enlarged partial cross-sectional view showing the structure of a cross section taken along the line AA shown in FIG.

6 is a partial plan view showing an example of a structure after die bonding in the assembly of a semiconductor device using the matrix frame shown in FIG. 4 with a part thereof broken away.

7 is an enlarged partial cross-sectional view showing the structure of a cross section taken along line BB shown in FIG.

FIG. 8 is an enlarged partial cross-sectional view showing a structure after die bonding of a modified example of FIG.

9 is a partial plan view showing a partially cutaway example of the structure after wire bonding in assembling the semiconductor device using the matrix frame shown in FIG. 4;

10 is an enlarged partial cross-sectional view showing the structure of a cross section taken along line CC shown in FIG.

11 is an enlarged partial cross-sectional view showing a structure after wire bonding of a modified example with respect to FIG.

12 is a partial plan view showing a partially cutaway example of the structure after resin sealing in assembly of a semiconductor device using the matrix frame shown in FIG.

13 is an enlarged partial cross-sectional view showing the structure of a cross section taken along line DD shown in FIG.

14 is a partial plan view showing an example of the structure of a frame body of a single-row lead frame used for assembling the semiconductor device shown in FIG.

FIG. 15 is an enlarged partial plan view showing the structure of a single-row lead frame in which an insulating member is attached to the frame body in FIG.

16 is an enlarged partial plan view showing an example of a structure after wire bonding in assembling a semiconductor device using the single-row lead frame shown in FIG.

17 is an enlarged partial plan view showing an example of a structure after resin sealing in assembly of a semiconductor device using the single-row lead frame shown in FIG.

18 is a side view showing an example of a structure after cutting and molding in assembling the semiconductor device using the single-row lead frame shown in FIG.

FIG. 19 is an enlarged partial plan view showing an example of a mounted state of the semiconductor device shown in FIG. 1 and another semiconductor device.

20 is an enlarged partial cross-sectional view showing the structure of a modified example with respect to FIG.

FIG. 21 is a sectional view showing a structure of a semiconductor device according to a modification of the first embodiment of the present invention.

22 is a cross-sectional view showing the detailed structure of the semiconductor device of the modification shown in FIG.

FIG. 23 is a cross-sectional view showing the detailed structure of the semiconductor device of the modification example shown in FIG. 21.

FIG. 24 is a cross-sectional view showing the detailed structure of the semiconductor device of the modified example shown in FIG. 21.

25 (a) and 25 (b) are views showing a structure of a QFN which is a semiconductor device of a modified example of the first embodiment of the present invention,
(A) is sectional drawing, (b) is a bottom view.

FIG. 26 is a sectional view showing an example of a structure of a semiconductor device according to a second embodiment of the present invention.

27 is a partial cross-sectional view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG.

FIG. 28 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 29 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 30 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 31 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 32 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 33 is a partial cross-sectional view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 34 is a partial cross-sectional view showing an example of the relationship between the thickness of the semiconductor chip when the semiconductor chip is mounted on the insulating member of the lead frame of the second embodiment of the present invention, and the insulating member and the adhesive layer. is there.

FIG. 35 is an enlarged partial plan view showing the structure of the lead frame of the modified example of the second embodiment of the present invention.

FIG. 36 is an enlarged partial plan view showing the structure of the lead frame of the modification of the second embodiment of the present invention.

[Explanation of symbols]

1 Matrix frame (lead frame) 1a frame body 1b Inner lead 1c outer lead Long hole for 1d guide 1e Positioning hole 1f frame 1g single row lead frame (lead frame) 1h Package area 1i Dambar 2 semiconductor chips 2a Pad (surface electrode) 2b back side 2c Main surface 3 Sealing part 3a back side 4 wires 5 Tape substrate (insulating material) 5a Tape base material 5b adhesive layer 5c Chip support surface 5d epoxy board with glass (insulating material) 5e Ceramic substrate (insulating member) 5f metal plate 5g hard adhesive layer 5h Soft adhesive layer 5i double-sided adhesive tape 5j Alumina particles 5k through hole 5l lead joint 6 QFP (semiconductor device) 6a center line 7 Mounting board 8 resin paste 9 SOP 10 QFN (semiconductor device) 11 QFP (semiconductor device)

Claims (13)

[Claims] 1. A plurality of inner leads extending around a semiconductor chip, a thin plate-like insulating member that supports the semiconductor chip and is joined to end portions of the inner leads, and A conductive wire connecting the surface electrode and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, and connected to the inner lead, An inner lead having a plurality of outer leads exposed from the encapsulation portion, wherein the length of the short side of the quadrangular main surface of the semiconductor chip is such that the tip is located farthest from the center line in the plane direction of the semiconductor device. 2. A semiconductor device characterized in that the distance is less than twice the distance from the tip to the semiconductor chip. 2. A plurality of inner leads extending around a semiconductor chip, a thin plate-shaped insulating member that supports the semiconductor chip and is joined to end portions of the inner leads, and A conductive wire connecting the surface electrode and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, and connected to the inner lead, An inner lead having a plurality of outer leads exposed from the encapsulation portion, wherein the length of the short side of the quadrangular main surface of the semiconductor chip is such that the tip is located farthest from the center line in the plane direction of the semiconductor device. A semiconductor device having a distance from the tip to the semiconductor chip which is equal to or more than twice the distance. 3. A plurality of inner leads extending around a semiconductor chip, a thin plate-like insulating member that supports the semiconductor chip and is joined to end portions of the inner leads, and A conductive wire connecting the surface electrode and the inner lead corresponding to the surface electrode, a sealing portion in which the semiconductor chip, the wire, and the insulating member are resin-sealed, and connected to the inner lead, A plurality of outer leads exposed from the encapsulation portion, and the installation pitch of the surface electrodes of the semiconductor chip is 1 / m of the minimum value of the pitch of the tips between the adjacent inner leads.
A semiconductor device characterized by being 2 or less. 4. An insulating member having an upper surface and a lower surface, a semiconductor integrated circuit chip having a plurality of bonding pads, a left side, a right side, an upper side of the semiconductor integrated circuit chip with respect to a plane direction of the semiconductor integrated circuit chip, and A first, a second, a third, and a fourth conductive lead disposed on each of the lower sides, and each of the first to fourth conductive leads is a bottom surface connected to the surface of the insulating member. And a top surface in a wire connectable state with one of the bonding pads
An end portion, and the first end portion of each of the first and second conductive leads is arranged along a virtual line extending from the left side to the right side of the semiconductor integrated circuit chip across the semiconductor integrated circuit chip. The dimension of the imaginary line that crosses the semiconductor integrated circuit chip is determined by the distance between the semiconductor integrated circuit chip and the first conductive lead, and the semiconductor integrated circuit chip and the second conductive lead.
Is equal to or less than the total distance from the conductive lead, and further covers the first end portion, the semiconductor integrated circuit chip and the insulating member, and is provided on the other side opposite to the first end portion. A semiconductor device having a resin exposing an end portion. 5. The semiconductor device according to claim 1, 2, 3, or 4, wherein the insulating member is a tape substrate. 6. The semiconductor device according to claim 1, 2, 3, or 4, wherein the insulating member is a glass-filled epoxy substrate. 7. The semiconductor device according to claim 1, 2, 3, or 4, wherein the semiconductor chip is mounted on a surface of the insulating member on the inner lead arrangement side. 8. The semiconductor device according to claim 1, 2, 3, or 4, wherein the inner lead and the insulating member are joined by an adhesive layer, and the semiconductor chip has a thickness of
A semiconductor device, which is thicker than a total thickness of the insulating member and the adhesive layer. 9. The semiconductor device according to claim 1, 2, 3 or 4, wherein the insulating member and the inner lead have a tape base material in which adhesive layers are arranged on both front and back surfaces. A semiconductor device, wherein the semiconductor device is bonded by the adhesive layer. 10. The semiconductor device according to claim 1, 2, 3 or 4, wherein the inner lead and the insulating member are joined by an adhesive layer, and the adhesive layer is the inner lead of the insulating member. A semiconductor device provided on the arrangement side so as to connect the inner leads. 11. The semiconductor device according to claim 1, 2, 3 or 4, wherein the inner lead and the insulating member are joined by an adhesive layer, and the adhesive layer is the inner lead of the insulating member. A semiconductor device, which is provided over the entire surface on the arrangement side. 12. The semiconductor device according to claim 1, 2, 3, or 4, wherein the inner lead and the insulating member are joined by an adhesive layer, and the adhesive layer is the inner lead of the insulating member. A semiconductor device characterized in that it is arranged only at a junction. 13. The semiconductor device according to claim 6, wherein:
A semiconductor device, wherein the glass-containing epoxy substrate is a glass-containing epoxy substrate containing alumina particles.