JP2020184591A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2020184591A JP2020184591A JP2019088834A JP2019088834A JP2020184591A JP 2020184591 A JP2020184591 A JP 2020184591A JP 2019088834 A JP2019088834 A JP 2019088834A JP 2019088834 A JP2019088834 A JP 2019088834A JP 2020184591 A JP2020184591 A JP 2020184591A
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Abstract
Description
20 半導体ユニット
21 第1半導体チップ
22 第2半導体チップ
23 回路パターン
24 絶縁基板
30 端子ケース
31 上部枠体部
32 下部本体部
32a 収納開口部
32b 第1端子領域
32c 第2端子領域
33,34,35,36 外部接続端子
37 制御IC
38 封止部材
40,50 平板状枠体
41 本体部
41a,52 開口部
41b,41c,41d,41e 端子パターン
42,43 半硬化端子支持部
42b,42c,42d,43e 端子支持パターン
51 枠体部
Claims (10)
- 基板及び外部接続端子を用意する用意工程と、
平板状であって、おもて面及び裏面を貫通する開口部が形成され、前記おもて面に窪みのパターンが形成された、半硬化状態の熱硬化性樹脂を含む第1半硬化部材を成形する平板状枠体成形工程と、
前記第1半硬化部材の前記開口部を覆うように前記基板を前記裏面に配置し、前記パターンに前記外部接続端子を配置し、加熱して、前記第1半硬化部材を硬化して、前記基板及び前記外部接続端子が固着された第1平板状枠体を含むケースを製造するケース製造工程と、
を有する半導体装置の製造方法。 - 前記平板状枠体成形工程では、液状の熱硬化性樹脂と粉末状の無機フィラーとを混合し、加熱して、粉末状の半硬化原料を形成する工程を含む、
請求項1に記載の半導体装置の製造方法。 - 前記平板状枠体成形工程では、前記半硬化原料を所定の第1金型内に充填し、前記第1金型内の前記半硬化原料を押圧して前記第1半硬化部材を成形する工程を含む、
請求項2に記載の半導体装置の製造方法。 - 前記ケース製造工程では、前記外部接続端子及び前記基板が配置された前記第1半硬化部材を加熱する、
請求項3に記載の半導体装置の製造方法。 - 前記ケース製造工程における加熱温度は、120℃以上、180℃以下である、
請求項4に記載の半導体装置の製造方法。 - 前記平板状枠体成形工程において、平板状であり、前記第1半硬化部材の外周縁に対応した環状であって、半硬化状態の熱硬化性樹脂を含む第2半硬化部材を成形し、
前記ケース製造工程において、前記基板及び前記外部接続端子が配置された前記第1半硬化部材の前記おもて面に前記第2半硬化部材を配置して、加熱し、前記第1半硬化部材及び前記第2半硬化部材を硬化し、前記第1平板状枠体に一体化された第2平板状枠体をさらに含む前記ケースを製造する、
請求項2乃至5のいずれかに記載の半導体装置の製造方法。 - 前記第2平板状枠体は、前記第1平板状枠体と同じ材料により構成されている、
請求項6に記載の半導体装置の製造方法。 - 前記平板状枠体成形工程では、前記半硬化原料を所定の第2金型内に充填し、前記第2金型内の前記半硬化原料を押圧して前記第2半硬化部材を成形する工程を含む、
請求項7に記載の半導体装置の製造方法。 - 前記平板状枠体成形工程は、前記第1半硬化部材と共に、平板状であって、おもて面に窪みの支持パターンが形成された、半硬化状態の熱硬化性樹脂を含む半硬化端子支持部材を形成する工程を含み、
前記ケース製造工程において、前記第1半硬化部材に配置された前記外部接続端子の前記第1半硬化部材からはみ出した部分を前記半硬化端子支持部材の前記支持パターンに配置し、前記半硬化端子支持部材を前記第1半硬化部材と共に加熱する工程を含む、
請求項1乃至8のいずれかに記載の半導体装置の製造方法。 - 前記ケース製造工程の終了後、前記ケースに囲まれる領域を封止部材で封止する封止工程をさらに有する、
請求項1乃至9のいずれかに記載の半導体装置の製造方法。
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US20110049558A1 (en) * | 2008-03-25 | 2011-03-03 | Lin Charles W C | Semiconductor chip assembly with post/base heat spreader, signal post and cavity |
US20110201157A1 (en) * | 2008-03-25 | 2011-08-18 | Bridge Semiconductor Corporation. | Method of making a semiconductor chip assembly with a post/base heat spreader and a multilevel conductive trace |
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