JP2020155755A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which fluctuations in a resistance value of a resistor to which a high voltage is applied are suppressed.SOLUTION: The semiconductor device includes: a first conductive type first semiconductor layer 10 set to a first potential; a second conductive type second semiconductor layer 20 laminated on the first semiconductor layer 10 and set to a second potential; an interlayer insulating film 40 arranged on a main surface of the second semiconductor layer 20; a resistor 30 arranged above the first semiconductor layer 10 via the second semiconductor layer 20 and the interlayer insulating film 40; and a power supply terminal 50 electrically connected to the second semiconductor layer 20.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to semiconductor devices including resistors.

In a semiconductor device in which a semiconductor integrated circuit is formed on a semiconductor substrate, a high voltage generated inside the semiconductor device may be used in the semiconductor integrated circuit. For example, in a semiconductor device having a non-volatile semiconductor storage element, a high voltage of about 10V to 35V is generated in the semiconductor device during operation. Under the condition of using such a high voltage, a resistor having a high resistance value and a high withstand voltage is used. In order to obtain a stable output, the resistance value of the resistor to which a high voltage is applied needs to be stable.

Japanese Unexamined Patent Publication No. 1-243570

An object to be solved by the present invention is to provide a semiconductor device in which fluctuations in the resistance value of a resistor to which a high voltage is applied are suppressed.

The semiconductor device according to the embodiment has a first conductive type first semiconductor layer set to a first potential and a second conductive type second semiconductor layer laminated on the first semiconductor layer and set to a second potential. A semiconductor layer, an interlayer insulating film arranged on the main surface of the second semiconductor layer, a resistor arranged above the first semiconductor layer via the second semiconductor layer and the interlayer insulating film, and a second semiconductor layer. It has an electrically connected power supply terminal.

It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device of the comparative example. It is a graph which shows the relationship between the voltage applied to a resistor and the fluctuation of the resistance value of a resistor. It is a graph which shows the relationship between the potential of a resistor and the fluctuation of the resistance value of a resistor. It is a graph which compared the fluctuation of the resistance value of the resistor between the semiconductor device which concerns on 1st Embodiment and the semiconductor device of a comparative example. It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 1). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 2). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 3). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 4). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 5). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 6). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 7). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 8). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 9). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 10). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 11). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 12). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (13). It is a schematic process sectional view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 14). It is a schematic cross-sectional view which shows the example which formed the resistor and a transistor on the same semiconductor substrate. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a schematic plan view which shows the other structure of the semiconductor device which concerns on 2nd Embodiment. It is a schematic cross-sectional view along the XX-XX direction of FIG.

Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

(First Embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a first conductive type first semiconductor layer 10 and a second conductive type second semiconductor laminated on the first semiconductor layer 10. The layer 20, the interlayer insulating film 40 arranged on the main surface of the second semiconductor layer 20, and the resistor 30 arranged above the first semiconductor layer 10 via the second semiconductor layer 20 and the interlayer insulating film 40. To be equipped. The first semiconductor layer 10 is set to the first potential, and the second semiconductor layer 20 is set to the second potential. The second potential is the first potential, or a potential intermediate between the first potential and the potential of the resistor 30 (hereinafter referred to as "resistance potential"). The potential difference between the first potential and the second potential is smaller than the withstand voltage of the pn junction formed at the interface between the first semiconductor layer 10 and the second semiconductor layer 20.

The first conductive type and the second conductive type are opposite conductive types to each other. That is, if the first conductive type is p-type, the second conductive type is n-type, and if the first conductive type is n-type, the second conductive type is p-type. Hereinafter, a case where the first conductive type is a p-type and the second conductive type is an n-type will be described.

In the semiconductor device shown in FIG. 1, the p-type first semiconductor layer 10 is set to the ground potential. That is, the first potential is the ground potential. The n-type second semiconductor layer 20 is formed by diffusing, for example, the n-type impurities injected into the upper part of the first semiconductor layer 10. The second semiconductor layer 20 is electrically connected to a power supply terminal 50 arranged on the upper surface of the interlayer insulating film 40 via a power supply via 61 that penetrates the interlayer insulating film 40 and reaches the second semiconductor layer 20. There is. By applying a second potential to the power supply terminal 50, the second semiconductor layer 20 is set to the second potential.

The semiconductor device shown in FIG. 1 is an embodiment in which the resistor 30 is mounted on the same semiconductor substrate as the non-volatile semiconductor storage element (not shown). That is, the first semiconductor layer 10 corresponds to the semiconductor substrate on which the non-volatile semiconductor storage element is formed. The recess of the second semiconductor layer 20 corresponds to the element separation groove of the transistor, and the depth of the recess is about 100 nm to 600 nm. As described above, the upper surface of the second semiconductor layer 20 has an uneven shape. The resistor 30 is arranged above the convex portion on the upper surface of the second semiconductor layer 20.

The interlayer insulating film 40 below the resistor 30 corresponds to a gate insulating film. The interlayer insulating film 40 is, for example, a silicon oxide film or a silicon oxynitride film. The film thickness of the interlayer insulating film 40 below the resistor 30 is, for example, about 13 nm to 50 nm.

The resistor 30 is formed by utilizing the manufacturing process of the gate electrode of the transistor. For example, a polysilicon film having a film thickness of about 40 nm to 400 nm is doped with impurities such as phosphorus (P) having a concentration of 1E 19 atoms / cm ³ or more to form a resistor 30. At this time, by forming the resistor 30 having a width of 150 nm to 500 nm and a length of about 0.5 μm to 40 μm, the resistor 30 having a resistance value of several kΩ to several tens of kΩ can be obtained. In this way, the resistor 30 is formed by doping the semiconductor film with impurities. The resistor 30 may be formed by doping a semiconductor film other than the polysilicon film with p-type impurities or n-type impurities.

In a NAND flash memory to which a high voltage is applied during operation, a high voltage is generated inside the semiconductor device. Therefore, a resistor having a high resistance value through which no current flows is used. When the semiconductor film is doped with impurities to achieve a high resistance value, the shape of the resistor is elongated in consideration of the temperature dependence of the resistivity of the semiconductor. For example, the ratio of the length to the width of the resistor is set to about 100: 1.

Then, for example, by connecting a plurality of resistors 30 to each other as shown in FIG. 2, a combined resistor having a resistance value of several kΩ to several hundred kΩ is formed. FIG. 1 is a cross-sectional view taken along the I-I direction of FIG. FIG. 2 shows an example of a composite resistor in which four resistors 30 are connected in series by a wiring 70 arranged on the upper surface of the interlayer insulating film 40, but the form of the composite resistor is not limited to this. Is. That is, a combined resistor having a desired resistance value can be realized by arbitrarily combining the parallel connection and the series connection of the resistors 30.

In FIG. 2, the resistor 30 is displayed through the interlayer insulating film 40. The resistor 30 and the wiring 70 are electrically connected by a wiring via 62 formed in the interlayer insulating film 40 below the wiring 70.

As described above, the composite resistor is configured by connecting the resistors 30 to each other by wiring 70 arranged in a wiring layer having a plane level different from that of the layer on which the resistor 30 is formed. In the example shown in FIG. 2, the resistors 30 are connected in series by the wiring 70 arranged on the upper surface of the interlayer insulating film 40. That is, the wiring 70 arranged on the upper surface of the interlayer insulating film 40 formed above the resistor 30 and the resistor 30 are alternately connected via the wiring via 62 penetrating the interlayer insulating film 40.

A voltage (hereinafter referred to as "resistor voltage Vp") is generated between the first terminal 301 and the second terminal 302 connected to the end of the combined resistor shown in FIG. 2 by wiring 70 during operation of the semiconductor device. It is applied. For example, the first terminal 301 is set to the ground potential, and the resistance voltage Vp is applied to the second terminal 302. When the resistance voltage Vp is large, the resistor 30 is set to a high potential. The resistance voltage Vp is, for example, about 10V to 35V. Therefore, if the second semiconductor layer 20 is not arranged between the first semiconductor layer 10 and the resistor 30, it is large between the first semiconductor layer 10 and the resistor 30 set to the ground potential. An electric field is generated.

The present inventors have formed a resistor by doping a semiconductor film with impurities, and when a large electric field is generated between a region adjacent to the resistor and the resistor, the resistance value of the resistor fluctuates. It was found that (hereinafter referred to as "resistance shift") occurs. This is because the state of charge on the surface of the resistor changes under the influence of the electric field. That is, the resistance value shift occurs when the potential difference between the potential of the region adjacent to the resistor via the insulating film (hereinafter, referred to as “board potential”) and the potential of the resistor is large.

On the other hand, according to the semiconductor device shown in FIG. 1, the resistance of the resistor 30 even when the resistor 30 is a semiconductor film doped with impurities and a high voltage is applied to the resistor 30. Value shift can be suppressed. The suppression of the resistance shift by the semiconductor device shown in FIG. 1 will be described below in comparison with the semiconductor device of the comparative example shown in FIG.

In the semiconductor device of the comparative example shown in FIG. 3, a p-type first semiconductor layer 10 set to a ground potential and a resistor 30 arranged above the first semiconductor layer 10 via an interlayer insulating film 40 are provided. Be prepared. The first semiconductor layer 10 is electrically connected to a power supply terminal 50 having a ground potential via a power supply via 61. The portion of the first semiconductor layer 10 immediately below the resistor 30 extends upward, and the distance between the resistor 30 and the first semiconductor layer 10 is narrowed. This interval is the same as the interval between the resistor 30 of the semiconductor device and the second semiconductor layer 20 according to the first embodiment.

That is, the semiconductor device of the comparative example is different from the semiconductor device according to the embodiment shown in FIG. 1 in that the second semiconductor layer 20 is not arranged between the first semiconductor layer 10 and the resistor 30. Since the potential of the first semiconductor layer 10 is the ground potential, the substrate potential of the semiconductor device of the comparative example is 0V. Therefore, when a high voltage is applied to the resistor 30, a large electric field is generated between the first semiconductor layer 10 and the resistor 30.

FIG. 4 shows the relationship between the resistance voltage Vp applied to the resistor 30 and the fluctuation of the resistance value of the resistor 30. The vertical axis of the graph shown in FIG. 4 is the resistance ratio (dR / R0) of the fluctuation amount dR of the resistance value to the resistance value R0 of the resistor 30 when the substrate potential is 0V.

As shown in FIG. 4, the resistance value of the resistor 30 fluctuates as the resistance voltage Vp increases. That is, the larger the potential difference between the substrate potential and the resistance potential, the larger the change in the resistance value of the resistor 30 due to the resistance value shift. Further, in the semiconductor device of the comparative example, the voltage applied to the resistor 30 is substantially applied to the interlayer insulating film 40 immediately below the resistor 30. Therefore, the interlayer insulating film 40 may deteriorate over time.

On the other hand, in the semiconductor device according to the first embodiment, a second semiconductor layer 20 capable of setting a potential between the first semiconductor layer 10 and the resistor 30 independently of the potential of the first semiconductor layer 10 is provided. Have been placed. The second potential of the second semiconductor layer 20 is the substrate potential, and the second potential is the first potential or a potential intermediate between the first potential of the first semiconductor layer 10 and the resistance potential of the resistor 30. Is set to. Therefore, the potential difference between the substrate potential and the resistance potential is reduced as compared with the semiconductor device of the comparative example. As a result, the resistance value shift of the resistor 30 is suppressed. Further, the voltage applied to the interlayer insulating film 40 immediately below the resistor 30 is reduced.

The second potential is set so that the potential difference between the first potential and the second potential is lower than the withstand voltage of the pn junction formed at the interface between the first semiconductor layer 10 and the second semiconductor layer 20. .. This is to suppress the leakage current between the first semiconductor layer 10 and the second semiconductor layer 20.

FIG. 5 shows the relationship between the potential of the resistor 30 and the fluctuation of the resistance value of the resistor 30. The vertical axis of the graph shown in FIG. 5 is the resistance ratio (dR / R0) of the fluctuation amount dR of the resistance value to the resistance value R0 of the resistor 30 when the second potential, which is the substrate potential, is 0V. The horizontal axis is the potential difference dV (dV = Vr-Vsi) between the resistance potential Vr and the second potential Vsi which is the substrate potential.

As shown in FIG. 5, the larger the potential difference dV, the larger the resistance ratio (dR / R0). That is, the smaller the second potential Vsi, the larger the change in the resistance value of the resistor 30 due to the resistance value shift. In the semiconductor device of the comparative example shown in FIG. 3, it corresponds to the case where the second potential Vsi is 0V, and the potential difference dV is large.

On the other hand, in the semiconductor device according to the first embodiment, since the second semiconductor layer 20 set to the second potential Vsi is arranged below the resistor 30, the semiconductor device of the comparative example shown in FIG. 3 is shown. The potential difference dV can be made smaller than that. As described above, according to the semiconductor device according to the first embodiment, the resistance value shift can be suppressed.

As shown in FIG. 5, as the second potential Vsi of the second semiconductor layer 20 is brought closer to the resistance potential Vr to reduce the potential difference dV, the resistance ratio (dR / R0) becomes smaller and the resistance value shift is suppressed. To. However, the second potential Vsi is set so that the potential difference between the first semiconductor layer 10 and the second semiconductor layer 20 is lower than the withstand voltage of the pn junction formed at the interface between the first semiconductor layer 10 and the second semiconductor layer 20. Set. As a result, the leakage current between the first semiconductor layer 10 and the second semiconductor layer 20 is suppressed, and the deterioration of the performance and reliability of the semiconductor device is suppressed.

FIG. 6 shows an example of the relationship between the resistance voltage Vp and the fluctuation of the resistance value of the resistor 30 in the semiconductor device of the comparative example shown in FIG. 3 and the semiconductor device according to the first embodiment. In FIG. 6, the magnitude of variation in the resistance value is defined as the resistance ratio (dR / R0), and the resistance ratio (dR / R0) of the semiconductor device of the comparative example is shown by the characteristic S1. The resistivity ratio (dR / R0) is shown by the characteristic S2. The characteristic S1 is the same as the fluctuation of the resistance value shown in FIG.

As shown in FIG. 6, in the semiconductor device according to the first embodiment, the resistance ratio (dR / R0) shifts in a direction smaller than that of the semiconductor device of the comparative example shown in FIG. That is, according to the semiconductor device according to the first embodiment, the fluctuation of the resistance value of the resistor 30 is suppressed in the range W of the resistance voltage Vp of the resistor 30 during the operation shown in FIG. For example, when the resistance voltage Vp is less than 5 V, the potential of the second semiconductor layer 20 is the same potential as the first potential, and the resistance value shift of the semiconductor device according to the first embodiment is the same as that of the semiconductor device of the comparative example. Equivalent. On the other hand, when the resistance voltage Vp is 5 V or more and the potential of the second semiconductor layer 20 is 10 V in the case of FIG. 6, the resistance value shift of the semiconductor device according to the first embodiment is the semiconductor device of the comparative example. It is equivalent to the case of Vp-5V. That is, the fluctuation of the resistance value of the resistor 30 in the semiconductor device according to the first embodiment is the same as that of the semiconductor device of the comparative example when the resistance voltage Vp is −5V to + 5V.

Further, in the semiconductor device according to the first embodiment, the voltage applied to the interlayer insulating film 40 arranged below the resistor 30 is reduced. Therefore, deterioration of the interlayer insulating film 40 with time can be prevented.

As described above, according to the semiconductor device according to the first embodiment, the resistance value shift of the resistor 30 can be suppressed. Further, the deterioration of the interlayer insulating film 40 with time is suppressed, and the reliability of the semiconductor device is improved.

For example, when the potential difference between the first semiconductor layer 10 and the resistor 30 where the first potential is the ground potential is about 10V to 35V, the second potential is set to about 5V. The semiconductor device according to the first embodiment is suitably used for a semiconductor device or the like in which a resistor 30 is formed on the same semiconductor substrate as a non-volatile semiconductor storage element that uses a high voltage during operation.

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. 7 to 10 and 11A to 15A are cross-sectional views taken along the AA direction of FIG. 2, and FIGS. 11B to 15B are cross-sectional views taken along the II direction of FIG. 2 unless otherwise specified. It is a figure. The semiconductor device manufacturing method described below is an example, and can be realized by various other manufacturing methods including this modification.

As shown in FIG. 7, the photoresist film 100 patterned using a photolithography technique or the like is used as a mask, and n-type impurities are selectively injected into the upper portion of the p-type first semiconductor layer 10 to form a second semiconductor. The layer 20 is formed. Next, as shown in FIG. 8, the first insulating film 41 is formed on the main surface of the second semiconductor layer 20. The first insulating film 41 corresponds to the interlayer insulating film 40 below the resistor 30.

As shown in FIG. 9, the polysilicon film 31 is formed on the upper surface of the first insulating film 41. Impurities in the polysilicon film 31 may be mixed, for example, during film formation of the polysilicon film 31. Alternatively, impurities may be ion-implanted into the polysilicon film 31. After that, as shown in FIG. 10, a second insulating film 42 is formed on the upper surface of the polysilicon film 31.

Next, as shown in FIGS. 11A and 11B, the polysilicon film 31 is patterned using a photolithography technique or the like to form the resistor 30. At this time, the first insulating film 41 and the second semiconductor layer 20 around the resistor 30 are removed by etching in accordance with the process of forming the element separation groove of the transistor. The etching-removed region is embedded by the third insulating film 43.

When there is a step of stacking the polysilicon films, the second insulating film 42 is patterned as shown in FIGS. 12A and 12B. After that, the additional polysilicon film 32 is formed. FIG. 12B is a cross-sectional view taken along the XII-XII direction of FIG. 12A.

Next, as shown in FIGS. 13A and 13B, the second insulating film 42, the polysilicon film 31 and the first insulating film 41 in the region forming the power supply via 61 are removed, and a part of the upper surface of the second semiconductor layer 20 is removed. To expose. Similarly, when there is a step of stacking the polysilicon film, a part of the upper surface of the second semiconductor layer 20 is exposed as shown in FIGS. 14A and 14B. FIG. 14B is a cross-sectional view taken along the XIV-XIV direction of FIG. 14A.

After that, the fourth insulating film 44 is formed on the entire surface. Then, as shown in FIGS. 15A and 15B, a power supply via 61 penetrating the fourth insulating film 44 is formed by using photolithography technology and etching. Further, a wiring via 62 penetrating the second insulating film 42 and the fourth insulating film 44 is formed. Further, the power supply terminal 50 and the wiring 70 are formed to complete the semiconductor device according to the first embodiment. The first insulating film 41, the second insulating film 42, the third insulating film 43, and the fourth insulating film 44 correspond to the interlayer insulating film 40 shown in FIG.

When the resistor 30 and the non-volatile semiconductor memory element are mixedly mounted on the same semiconductor substrate, a memory cell is formed before the fourth insulating film 44 is formed. Further, when forming one layer of the polysilicon film, a metal layer such as silicide may be formed at the interface where the polysilicon film and the bottom of the via are in contact with each other.

In the above, the case where the first semiconductor layer 10 is a semiconductor substrate has been described, but the semiconductor device according to the first embodiment can also be applied to semiconductor devices having other configurations.

Further, the resistor 30 may be formed on a semiconductor substrate on which a low withstand voltage transistor and a high withstand voltage transistor having different gate insulating films are formed. FIG. 16 shows an example of a low withstand voltage transistor LV, a high withstand voltage transistor HV, and a resistor 30 formed on the same semiconductor substrate. In both the low withstand voltage transistor LV and the high withstand voltage transistor HV, an n-type region 205 is formed between the n-type source electrode 201 and the drain electrode 202, and a gate is formed above the n-type region 205 via a gate insulating film 204. The electrode 203 is arranged. The low withstand voltage transistor LV is a transistor in which switching speed is prioritized, and the film thickness of the gate insulating film 204 is about several nm. The high withstand voltage transistor HV is a transistor that gives priority to withstand voltage, and the film thickness of the gate insulating film 204 is about 13 nm to 50 nm.

The film thickness of the interlayer insulating film 40 below the resistor 30 is formed to be the same as that of the gate insulating film 204 of the high withstand voltage transistor HV. As shown in FIG. 16, the upper surface of the gate electrode 203 of the high withstand voltage transistor HV and the upper surface of the resistor 30 are at the same plane level. In order to make the structure easy to understand, in FIG. 16, as the interlayer insulating film 40 around the resistor 30, only the interlayer insulating film 40 below the resistor 30 is shown.

(Second Embodiment)
The semiconductor device according to the second embodiment includes one composite resistor in which a plurality of resistors 30 are connected in series via a wiring via 62 and a wiring 70. FIG. 17 shows an example in which four resistors 30 are connected in series to form a composite resistor. Then, the second semiconductor layer 20 is electrically connected to any one of the resistors 30, and the second semiconductor layer 20 is set to the second potential. That is, the semiconductor device according to the second embodiment is different from the first embodiment shown in FIG. 1 in that a second potential is generated by resistance division of the composite resistor. Other configurations of the second embodiment are the same as those of the first embodiment.

In the semiconductor device shown in FIG. 17, one of the mutual connection points of the resistors 30 and the second semiconductor layer 20 are electrically connected via the wiring 70 and the power supply via 61 arranged on the upper surface of the interlayer insulating film 40. Has been done. FIG. 18 shows a circuit diagram of the semiconductor device according to the second embodiment. The second potential is generated by dividing the resistance voltage Vp applied to both ends of the combined resistor into resistors. Further, a connection terminal may be set at an arbitrary position of the composite resistor, and the potential generated at the connection terminal may be used for the circuit operation of the semiconductor device. FIG. 18 shows an example in which connection terminals 310 and 320 are set at the mutual connection points of the resistors 30. The combined resistor with the connection terminals 310 and 320 set is used for voltage generation by resistance division, pull-down resistance, ripple countermeasures, and the like.

According to the semiconductor device according to the second embodiment, it is not necessary to arrange a special circuit for generating the second potential set in the second semiconductor layer 20. Therefore, it is possible to suppress an increase in the circuit configuration and the chip size.

A plurality of resistors 30 having the same shape, which are periodically arranged, may be connected to form a composite resistor to generate a second potential corresponding to the resistivity ratio of the composite resistors. As a result, a second potential can be generated as a potential having a constant ratio with respect to the resistance voltage Vp. Therefore, it is possible to suppress the manufacturing variation of the second potential. Further, a potential at a constant ratio with respect to the resistance voltage Vp is applied to the interlayer insulating film 40, and deterioration of the interlayer insulating film 40 with time can be suppressed.

Further, in FIG. 17, a semiconductor device for electrically connecting the second semiconductor layer 20 to any of the mutual connection points of the resistors 30 is shown, but an arbitrary position of the specific resistor 30 and the second semiconductor layer 20 are shown. May be electrically connected. In this case, for example, as shown in FIGS. 19 and 20, a resistor via 63 connected to the resistor 30 is formed, and the resistor 30 and the second semiconductor layer 20 are formed via the resistor via 63, the wiring 70, and the power supply via 61. Can be electrically connected.

Although some embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments are various other embodiments. It can be carried out in various forms, and various omissions, rewrites, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention as well as the invention described in the claims and the equivalent scope thereof.

10 ... 1st semiconductor layer 20 ... 2nd semiconductor layer 30 ... Resistor 40 ... Interlayer insulating film 50 ... Power supply terminal

Claims (8)

The first conductive type first semiconductor layer set to the first potential, and
A second conductive type second semiconductor layer laminated on the first semiconductor layer and set to a second potential, and
An interlayer insulating film arranged on the main surface of the second semiconductor layer and
A resistor arranged above the first semiconductor layer via the second semiconductor layer and the interlayer insulating film.
A semiconductor device including the second semiconductor layer and a power supply terminal electrically connected to the second semiconductor layer. The second potential is the first potential, or a potential intermediate between the first potential and the potential of the resistor, and the potential difference between the first potential and the second potential is The semiconductor device according to claim 1, wherein the withstand voltage of the pn junction formed at the interface between the first semiconductor layer and the second semiconductor layer is smaller. The semiconductor device according to claim 1 or 2, wherein the resistor is a semiconductor film doped with impurities. A composite resistor is constructed by connecting a plurality of the resistors.
The invention according to any one of claims 1 to 3, wherein the second semiconductor layer is electrically connected to any one of the plurality of resistors to set the potential of the second semiconductor layer. Semiconductor device. The semiconductor device according to claim 4, wherein a plurality of the resistors having the same shape arranged periodically are connected to form the combined resistor. The semiconductor device according to claim 4 or 5, wherein the second semiconductor layer is electrically connected to any of the mutual connection points of the plurality of resistors. The composite resistor is configured according to claim 4 to 6, wherein the wiring arranged on the upper surface of the insulating film formed above the resistor and the resistor are alternately connected to each other. The semiconductor device according to any one item. The upper surface of the second semiconductor layer has a concave-convex shape with a recess depth of 100 nm to 600 nm, and the resistor is arranged above the convex portion of the upper surface of the second semiconductor layer. The semiconductor device according to any one of claims 1 to 7.

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