TWI559451B - Three-dimensional memory and method for manufacturing the same - Google Patents

Description

Three-dimensional memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a three-dimensional memory and a method of fabricating the same.

A typical thin film transistor can be erased by providing a hole to increase the channel potential. In a conventional planar structure, the substrate can play the role of providing a hole. In contrast, in a three-dimensional structure (for example, a three-dimensional inverse and a flash memory), the thin film transistor may not directly contact the substrate, and thus it is not easy to obtain a hole from the substrate. One way to provide holes to such thin film transistors is to create holes by gate-induced drain leakage (GIDL). However, this method is susceptible to local electric fields and takes a long time to provide a sufficient number of holes. In addition, GIDL stress can damage the gate oxide and deteriorate reliability. Another method is to use a p-type source instead of an n-type source. However, when reading a thin film transistor using a p-type source, a voltage drop occurs.

In the present specification, a new structure that solves the above problems is provided. In the present specification, a manufacturing method thereof is also provided.

According to an embodiment, a three-dimensional memory is provided. Such three-dimensional The memory layer includes a thin film transistor. The thin film transistor has a source region and a drain region which are separately disposed. The source region includes a first source region and a second source region, and the second source region is disposed between the first source region and the drain region. The first source region is p-type doped, the second source region is n-type doped, and the drain region is n-type doped.

According to another embodiment, a method of fabricating a three-dimensional memory is provided. This method includes the following steps. First, a stack of a plurality of electrically conductive layers and a plurality of insulating layers alternately stacked is formed on a substrate. A source region of a thin film transistor forming a three-dimensional memory. The step includes forming a via through the stack, forming an n-type doped layer on the sidewall of the via, and filling a p-type dopant material onto the n-doped layer in the via. A drain region of the thin film transistor and the source regions are separated from each other. This step includes: forming a series of vias respectively connected to the conductive layers of the stack; and filling an n-type dopant material into the series of vias.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧film transistor

104‧‧‧ source area

106‧‧‧Bungee Area

108‧‧‧First source region

110‧‧‧Second source area

112‧‧‧ bit line

114‧‧‧ character line

116‧‧‧汲 contact

118A‧‧‧Source contact

118B‧‧‧Source contact

202‧‧‧Substrate

204‧‧‧buried layer

206‧‧‧ Conductive layer

208‧‧‧Insulation

210‧‧‧Stacking

212‧‧‧Perforation

214‧‧‧n-type doped layer

216‧‧‧p-type doping material

218‧‧‧Perforation

220‧‧‧Insulation

222‧‧‧n type doping material

224‧‧‧ bit line

226‧‧‧ trench

228‧‧‧Oxide-nitride-oxide structure

230‧‧‧Electrical materials

232‧‧‧ character line

236‧‧‧ source contact

238‧‧‧汲 contacts

D‧‧‧Bungee Area

L ₁ ‧‧‧ Length of the first source region

L ₂ ‧‧‧ Length of the second source region

L _t ‧‧‧ total length of the source region

S‧‧‧ Source Area

1A-1C illustrate a portion of a three-dimensional memory in accordance with an embodiment.

2A-2B are diagrams showing the characteristics of an example and a comparative example according to an embodiment.

Figure 3 shows the characteristics of an example and a comparative example according to an embodiment.

4A-11B illustrate a method of fabricating a three-dimensional memory according to an embodiment.

Please refer to FIG. 1A-1C, which illustrates a three-dimensional representation according to an embodiment. A part of the memory, in which the 1B and 1C are enlarged views of the portion A in the 1A. The three-dimensional memory includes a thin film transistor 102. For ease of description and drawing, the three-dimensional memory system in the drawing is drawn into a 3D NAND flash memory, and the thin film transistor 102 can be used for a memory cell as a memory cell. However, the present invention is applicable to other types of thin film transistors including a three-dimensional memory of a thin film transistor and other uses.

The thin film transistor 102 has a source region 104 and a drain region 106 which are separately disposed. The source region 104 includes a first source region 108 and a second source region 110. The second source region 110 is disposed between the first source region 108 and the drain region 106. The length of the first source region 108 is L ₁ , the length of the second source region 110 is L ₂ , and the total length of the source region 104 is L _t . In one example, L _t is equal to 0.3 microns. The first source region 108 is p-type doped, the second source region 110 is n-type doped, and the drain region 106 is n-type doped.

Since the source region 104 includes the p-type first source region 108, a stable and fast source of holes is provided. Unlike the example in which only the p-type source is used, the source region 104 also includes the n-type second source region 110. Therefore, when the thin film transistor 102 according to the embodiment is read, a pressure drop does not occur. In addition, the disadvantages caused by the use of holes generated by GIDL, such as instability, time consuming, structural damage, etc., can also be avoided.

The three-dimensional memory can also include a source contact and a drain contact 116. In one embodiment, as shown in FIG. 1B, the source contact 118A simultaneously connects the first source region 108 and the second source region 110. In another embodiment, as shown in FIG. 1C, the source contact 118B is only connected to the first source region 108 and not to the second source region 110. In both embodiments, the length L _{2 of the} second source region 110 may be equal to or less than 0.02 microns. The drain contact 116 is connected to the drain region 106.

The three-dimensional memory may further include a substrate (as shown in FIG. 4B), a bit line 112 and a word line 114. The bit line 112 is disposed on the substrate, and the word line 114 is disposed on the substrate and orthogonal to Bit line 112. Source region 104 and drain region 106 may be disposed along bit line 112 and are not in direct contact with the substrate.

2A-2B shows characteristics of an example according to an embodiment and a comparative example thereof when reading thin film transistors according to the examples and comparative examples. In the example shown in FIG. 2A, the source contact 118A is simultaneously connected to the p-type first source region 108 and the n-type second source region 110. In the comparative example shown in FIG. 2B, the source contact 118B is only connected to the p-type first source region 108. In the example shown in Fig. 2A and the comparative example shown in Fig. 2B, L _t is equal to 0.3 μm, and both L ₁ and L _{2 are} equal to 0.15 μm. In the comparative example, since the pn junction between the first source region 108 and the second source region 110 is reverse biased during reading, the I _D current is dominated by tunneling between the energy bands. And strongly affected by the Vd bias. In the example where source contact 118A is also connected to the n-type source region, the I _D -V _G curve exhibits typical characteristics of n-channel read.

Fig. 3 is a view showing characteristics of an exemplary embodiment and a comparative example thereof when erasing the thin film transistors according to the examples and the comparative examples, according to an embodiment. In all of the examples and comparative examples, L _{t was} equal to 0.3 μm. When the length of the n-type second source region 110 is sufficiently short, for example, equal to or less than 0.02 microns, the holes provided by the p-type first source region 108 can pass through the second source region 110 more easily and quickly. Therefore, the erasing speed can be further improved. According to an embodiment, the source contact can simultaneously connect both the p-type first source region 108 and the n-type second source region 110. Alternatively, according to another embodiment, the source contact may only be connected to the p-type first source region 108.

Referring now to FIGS. 4A-11B, there is illustrated a method of fabricating a three-dimensional memory according to an embodiment, wherein the pattern indicated by "B" is along the B- in the pattern indicated by "A". A cross-sectional view of the B' line. First, as shown in FIGS. 4A and 4B, a substrate 202 is provided, and a stack 210 of a plurality of electrically conductive layers 206 and a plurality of insulating layers 208 alternately stacked is formed on the substrate 202. In an embodiment, a buried layer 204 may be formed between the substrate 202 and the stack 210.

A source region S of a thin film transistor forming a three-dimensional memory is shown in Figures 5A-6B. Referring to Figures 5A and 5B, a perforation 212 is formed through the stack 210. Referring to FIGS. 6A and 6B, an n-type doping layer 214 is formed on the sidewall of the via 212 and a p-type dopant material 216 is filled into the n-doped layer 214 of the via 212. In an embodiment, the thickness of the n-type doped layer 214 may be equal to or less than 0.02 microns.

One of the drain regions D of the thin film transistor is formed as shown in Figures 7A-7B. The drain region D and the source region S are separated from each other. A series of perforations 218 are formed that are respectively connected to the conductive layer 206 of the stack 210. An insulating layer 220 may be formed on the sidewalls of the vias 218. Etching is then performed to remove excess material and fill an n-type dopant material 222 into the series of vias 218.

Bit line 224 and word line 232 are formed as shown in Figures 8A-10B. Referring to FIGS. 8A and 8B, the stack 210 is patterned to form a plurality of bit lines 224 that are separated by trenches 226. The source region S and the drain region D respectively pass through at least a portion of one of the plurality of bit lines 224. Referring to FIGS. 9A and 9B, an oxide-nitride-oxide (ONO) structure 228 is formed on the sidewalls of the trenches 226 between the bit lines 224, and a conductive material 230 (eg, polysilicon) is filled into the trenches. In the slot 226. Referring to FIGS. 10A and 10B, a plurality of patterned conductive materials 230 are formed. Word line 232.

The order in which the source region S, the drain region D, the bit line 224, and the word line 232 are formed may be exchanged with each other. Next, referring to FIGS. 11A and 11B, a source contact 236 and a plurality of gate contacts 238 are formed. In an embodiment, the source contact 236 is simultaneously connected to the p-type dopant material 216 and the n-type doping layer 214. Alternatively, in another embodiment, source contact 236 is connected to p-type dopant material 216 but not to n-type doped layer 214. The drain contact 238 connects the n-type dopant material 222 in the series of vias 218.

According to the above method, a three-dimensional memory in which a stable and fast source of holes is provided according to an embodiment can be easily constructed. However, this method is for explanation only, and other methods of manufacturing the three-dimensional memory according to the embodiment can be implemented.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧film transistor

104‧‧‧ source area

106‧‧‧Bungee Area

108‧‧‧First source region

110‧‧‧Second source area

112‧‧‧ bit line

114‧‧‧ character line

116‧‧‧汲 contact

L ₁ ‧‧‧ Length of the first source region

L ₂ ‧‧‧ Length of the second source region

L _t ‧‧‧ total length of the source region

Claims (10)

A three-dimensional memory comprising: a thin film transistor having a source region and a drain region separately disposed, wherein the source region includes a first source region and a second source region, the second source a polar region is disposed between the first source region and the drain region, and wherein the first source region is p-type doped, the second source region is n-type doped, and the drain region is n Type doping; wherein the source region and the drain region respectively pass through at least a portion of one of the plurality of bit lines. The three-dimensional memory of claim 1, further comprising: a source contact connecting the first source region and the second source region; and a drain contact connecting the drain region. The three-dimensional memory of claim 1, further comprising: a source contact connecting the first source region but not connecting the second source region; and a drain contact connecting the drain region. The three-dimensional memory of claim 3, wherein the length of the second source region is equal to or less than 0.02 microns. The three-dimensional memory of claim 1, wherein the length of the second source region is equal to or less than 0.02 microns. The three-dimensional memory of claim 1, further comprising: a substrate; and a bit line disposed on the substrate; wherein the source region and the drain region are disposed along the bit line and are not in direct contact The substrate. A method for manufacturing a three-dimensional memory, comprising: forming a stack of a plurality of electrically conductive layers and a plurality of insulating layers alternately stacked on a substrate; forming a source region of a thin film transistor of the three-dimensional memory, comprising: forming Passing through a via of the stack; forming an n-type doped layer on the sidewall of the via; and filling a p-type dopant material onto the n-type doped layer in the via; and forming a bond between the thin film transistor A drain region separated from each other by the source regions includes: forming a series of vias respectively connected to the conductive layers of the stack; and filling an n-type dopant material into the series of vias. The method of manufacturing the three-dimensional memory of claim 7, further comprising: forming a source contact that simultaneously connects the p-type dopant material and the n-type doped layer; and forming the n-type dopant in the series of vias The complex bungee contact of the miscellaneous material. The method of fabricating the three-dimensional memory of claim 7, further comprising: forming a source contact connecting the p-type doping material but not connecting the n-type doped layer; and forming the n-type connected to the series of through holes A plurality of dipole contacts of the doped material. A method of manufacturing a three-dimensional memory according to claim 7, wherein the thickness of the n-type doped layer is equal to or smaller than 0.02 μm.