JP6343052B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a resistance element that is a component of a semiconductor integrated circuit.

  In general, in a semiconductor integrated circuit, a resistance element is widely used for voltage control such as voltage division or step-down of a power supply voltage or a signal voltage. Such a resistance element is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-111311 (Patent Document 1).

FIG. 1 is a schematic cross-sectional view of a semiconductor device including a resistance element disclosed in Patent Document 1. The semiconductor device shown in FIG. 1 includes an n-type silicon substrate 101, a plurality of p ⁺ -type diffusion resistance regions 103 formed on the surface layer of the silicon substrate 101, and a thin oxide film formed on the silicon substrate 101. A film 121 and a polycrystalline silicon layer (low resistance layer) 107 covering the portion of the upper surface of the oxide film 121 excluding the portion directly above the diffusion resistance region 103 are provided. The resistance element is constituted by a plurality of diffusion resistance regions 103. The diffusion resistance region 103 is formed by implanting impurity ions such as boron ions into the silicon substrate 101 through the thin oxide film 121. Since the polycrystalline silicon layer 107 is fixed to a predetermined power supply voltage, even if an electric field is formed directly below the polycrystalline silicon layer 107 by wiring (not shown) above the silicon substrate 101, the diffusion resistance Leakage current due to the formation of the p-type inversion layer between the regions 103 and 103 can be prevented.

Japanese Patent Laid-Open No. 7-111111 (paragraphs 0002 to 0003 and FIG. 1 etc.)

  In recent years, analog integrated circuits have been required to have high precision in voltage control, and accordingly, stabilization of the characteristics of resistance elements (reduction in variation in resistance values between resistance elements in the circuit) has been strongly demanded. . In the resistance element composed of the plurality of diffusion resistance regions 103 of Patent Document 1, since the oxide film 121 is thin, the characteristics of the resistance element fluctuate due to the fluctuation of the power supply voltage applied to the polycrystalline silicon layer 107. There is a problem that it is easy.

  In view of the above, an object of the present invention is to provide a semiconductor device capable of realizing stabilization of resistance characteristics.

A semiconductor device according to an aspect of the present invention includes a plurality of well regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, and a first insulating film formed over the first insulating film. A resistive layer, a second resistive layer formed on the first insulating film and spaced apart from the first resistive layer, and the first resistive layer between the first resistive layer and the second resistive layer A conductive layer formed above a semiconductor substrate; a first well contact formed in one of the plurality of well regions and electrically connected to the first resistance layer; and the first well contact And a second well contact electrically connected to the second resistance layer , wherein the plurality of well regions are formed in the semiconductor substrate. An impurity diffusion region of the first conductivity type formed in the conductive layer , Characterized in that it is fixed to the not form an inversion layer of the first conductivity type semiconductor region of the semiconductor substrate potential between the plurality of well regions.
A semiconductor device according to another aspect of the present invention includes a plurality of well regions formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a first insulating film formed on the first insulating film. 1 resistive layer, a second resistive layer formed on the first insulating film and spaced apart from the first resistive layer, and between the first resistive layer and the second resistive layer A conductive layer formed above the semiconductor substrate; a first well contact formed in any of the plurality of well regions and electrically connected to the first resistance layer; and the first well. A second well contact formed in one of the plurality of well regions and spaced apart from the contact and electrically connected to the second resistance layer, and between the first insulating film and the conductive layer And an interlayer insulating film interposed therebetween.

  According to the present invention, the conductive layer is formed immediately above the semiconductor region between the first well region and the second well region, and the intermediate insulating film is formed between the conductive layer and the semiconductor region. ing. Since the conductive layer is fixed at a potential that does not cause an inversion layer in the semiconductor region, it is possible to suppress the occurrence of leakage current due to conduction between the first well region and the second well region. it can. In addition, the presence of the intermediate insulating film can stabilize the characteristics of the first and second resistance elements while preventing the occurrence of leakage current.

FIG. 1 is a schematic cross-sectional view of a semiconductor device including a resistance element disclosed in Patent Document 1. It is a figure which shows schematically a part of layout of the semiconductor device of embodiment concerning this invention by upper surface view. It is a schematic sectional drawing in the III-III line of the semiconductor device of FIG. It is a schematic sectional drawing in the IV-IV line of the semiconductor device of FIG. FIG. 5 is a schematic cross-sectional view taken along line VV of the semiconductor device of FIG. 2. FIG. 3 is a schematic cross-sectional view taken along line VI-VI of the semiconductor device of FIG. 2. It is a figure which shows the equivalent circuit containing the resistive element of the semiconductor device of this Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 2 is a diagram schematically showing a part of the layout of the semiconductor device 1 of the present embodiment in a top view. The semiconductor device 1 includes a plurality of semiconductor elements such as a resistance element, a MOS transistor, and a capacitor element constituting a semiconductor integrated circuit. FIG. 2 is a diagram showing a layout of resistance elements 5A, 5B, 5C, and 5D among the plurality of semiconductor elements. 3 is a schematic cross-sectional view taken along line III-III of the semiconductor device 1 of FIG. 2, FIG. 4 is a schematic cross-sectional view taken along line IV-IV of the semiconductor device 1 of FIG. 2, and FIG. FIG. 6 is a schematic cross-sectional view taken along line VV of the semiconductor device 1 of FIG. 2, and FIG. 6 is a schematic cross-sectional view taken along line VI-VI of the semiconductor device 1 of FIG. 3 to 6 show the insulating films 20, 21, 22, and 23. In FIG. 2, the insulating films 20, 21, 22, and 23 are not shown.

  As shown in FIG. 2, the semiconductor device 1 includes well regions 11A, 11B, 11C, and 11D that are p-type impurity diffusion regions arranged in parallel, and directly above the well regions 11A, 11B, 11C, and 11D, respectively. The resistor layers 32A, 32B, 32C, and 32D are formed, and the conductive wiring layer 33 is formed so as to surround each of the well regions 11A, 11B, 11C, and 11D in a top view. The conductive wiring layer 33 is fixed to a predetermined power supply voltage Vcc. The resistance layers 32A and 32C are electrically connected to each other via the first connection wiring layer 38, and the resistance layers 32B and 32D are electrically connected to each other via the second connection wiring layer 39. Yes. These resistance layers 32A, 32B, 32C, and 32D can be made of, for example, a polycrystalline silicon material. Further, each of the conductive wiring layer 33, the first connection wiring layer 38, and the second connection wiring layer 39 can be made of a metal material such as aluminum or copper.

  As shown in FIG. 3 to FIG. 6, the semiconductor device 1 has a semiconductor substrate 10 that is an n-type single crystal silicon substrate. Well regions 11A, 11B, 11C, and 11D extending in a predetermined direction parallel to are arranged. In these well regions 11A to 11D, for example, a resist pattern (not shown) is formed on the upper surface of the semiconductor substrate 10, and p-type impurities such as boron ions and boron fluoride ions are selectively implanted using this resist pattern as a mask. And can be formed by activation by heat treatment.

  In this embodiment, an n-type single crystal silicon substrate is used as the semiconductor substrate 10, but the present invention is not limited to this. Instead of the n-type single crystal silicon substrate, for example, a semiconductor substrate having an n-type epitaxial growth layer or an SOI (Semiconductor-On-Insulator or Silicon-On-Insulator) substrate may be used. The SOI substrate includes a support substrate, a semiconductor layer forming a surface layer portion, and a buried insulating film interposed between the support substrate and the semiconductor layer. The buried insulating film has a function of electrically separating the semiconductor layer from the supporting substrate.

  The upper surface of the semiconductor substrate 10 is covered with an element isolation insulating film 20. The element isolation insulating film 20 has a function of electrically isolating a plurality of semiconductor elements in the lateral direction. The element isolation insulating film 20 can be, for example, a field insulating film formed with a thickness of 0.1 μm to several μm by the LOCOS method. Instead of the LOCOS method, the element isolation insulating film 20 may be formed using a trench isolation technique such as a known STI (Shallow Trench Isolation). The thickness of the element isolation insulating film 20 of the present embodiment is larger than the thickness of a surface oxide film such as a general gate oxide film formed on the upper surface of the semiconductor substrate. Since the resistance layers 32A to 32D constituting the resistance elements 5A to 5D are formed above the element isolation insulating film 20, the potential of the semiconductor substrate 10 exerts on the resistance layers 32A to 32D having a high specific resistance. The influence can be reduced.

  A lower insulating film 21 such as a silicon oxide film is formed on the element isolation insulating film 20. The element isolation insulating film 20 and the lower insulating film 21 can constitute the intermediate insulating film of the present invention. On the lower insulating film 21, resistance layers 32A, 32B, 32C, and 32D extending in the extending direction of the well regions 11A, 11B, 11C, and 11D are formed. The resistance layers 32A to 32D are formed by depositing a polycrystalline silicon layer doped with impurities such as phosphorus on the lower insulating film 21 by, for example, a low pressure CVD method after the lower insulating film 21 is deposited. It is formed by patterning this polycrystalline silicon layer by anisotropic etching.

As shown in FIG. 6, in the well region 11A immediately below the resistance layer 32A, a p ⁺ type well contact region 12A which is a p-type impurity diffusion region having a higher concentration than the well region 11A is formed. The resistance layer 32A is electrically connected to the well region 11A through the contact plug 31A embedded in the lower insulating film 21 and the well contact region 12A. Similarly, a p ⁺ -type well contact region 12B having a higher concentration than the well region 11B is formed in the well region 11B immediately below the resistance layer 32B. The resistance layer 32B is embedded in the lower insulating film 21. The well region 11B is electrically connected through the contact plug 31B and the well contact region 12B.

On the other hand, as shown in FIG. 4, a p ⁺ -type well contact region 12C, which is a p-type impurity diffusion region having a concentration higher than that of the well region 11C, is formed in the well region 11C immediately below the resistance layer 32C. The resistance layer 32C is electrically connected to the well region 11C through the contact plug 31C embedded in the lower insulating film 21 and the well contact region 12C. Similarly, a p ⁺ type well contact region 12D having a concentration higher than that of the well region 11D is formed in the well region 11D immediately below the resistance layer 32D. The resistance layer 32D is embedded in the lower insulating film 21. The well region 11D is electrically connected through the contact plug 31D and the well contact region 12D.

  For the contact plugs 31A, 31B, 31C, 31D, for example, contact holes that expose the upper surface of the semiconductor substrate 10 are formed in the lower insulating film 21 by using a photolithography technique and an etching technique, and these contact holes are formed by a CVD method. It can be formed by embedding a conductive material inside.

  As shown in FIGS. 3 to 6, a first interlayer insulating film 22 covering the resistance layers 32 </ b> A to 32 </ b> D is formed on the lower insulating film 21. A second interlayer insulating film 23 is further formed on the first interlayer insulating film 22. The first interlayer insulating film 22 and the second interlayer insulating film 23 can also be formed by depositing an insulating material with a thickness of about 0.1 μm to several tens of μm by the CVD method similarly to the lower layer insulating film 21.

  As shown in FIGS. 4 to 6, on the first interlayer insulating film 22, the conductive layers 33A, 33B, 33C, 33D, and 33E constituting the conductive wiring layer 33 are extended from the well regions 11A to 11D. Extends along the direction. Conductive layer 33B is disposed immediately above the n-type region between well regions 11A and 11B adjacent to each other. This structure includes a p-channel parasitic transistor having the conductive layer 33B as a gate electrode, the insulating film immediately below the conductive layer 33B as a gate insulating film, and the p-type well regions 11A and 11B facing each other as sources and drains. Although it has a structure, the power supply voltage Vcc applied to the conductive layer 33B is a voltage value that does not invert the conductivity type (n-type) of the region between the well regions 11A and 11B to the p-type (ie, does not turn on the parasitic transistor). Voltage value). Thereby, it is possible to prevent a leak current from being generated in the region between the well regions 11A and 11B when the semiconductor device 1 is driven. Similarly, the conductive layer 33C is disposed immediately above the n-type region between the well regions 11B and 11C facing each other, and the conductive layer 33D is disposed immediately above the n-type region between the well regions 11C and 11D facing each other. ing.

  The well regions 11A, 11B, 11C, and 11D have a function of protecting the resistance layers 32A, 32B, 32C, and 32D from fluctuations in the substrate potential. From the viewpoint of stabilizing the potentials of the well regions 11A, 11B, 11C, and 11D, the lateral dimensions of the well regions 11A, 11B, 11C, and 11D are set in the lateral direction of the resistance layers 32A, 32B, 32C, and 32D, respectively. Desirably larger than the dimensions. However, if the dimensions of each of the well regions 11A, 11B, 11C, and 11D are increased, the interval L (FIG. 5) between the well regions 11A, 11B, 11C, and 11D is shortened. In the present embodiment, since a thick insulating layer including the element isolation insulating film 20, the lower insulating film 21, and the first interlayer insulating film 22 is interposed between the semiconductor substrate 10 and the conductive layers 33B, 33C, and 33D. Even if the interval L (FIG. 5) is short, the parasitic transistor does not transition to the ON state, and leakage current can be reliably prevented.

  As shown in FIGS. 2 and 3, a first connection wiring layer 38 that electrically connects the resistance layers 32 </ b> A and 32 </ b> C to each other is formed on the second interlayer insulating film 23. Also, upper contact plugs 36A and 36C electrically connected to the upper ends of the resistance layers 32A and 32C are embedded in the first interlayer insulating film 22 and the second interlayer insulating film 23. The first connection wiring layer 38 electrically connects the resistance layers 32A and 32C to each other through the upper layer contact plugs 36A and 36C. On the other hand, as shown in FIGS. 2 and 4, a second connection wiring layer 39 that electrically connects the resistance layers 32 </ b> B and 32 </ b> D to each other is formed on the second interlayer insulating film 23. Further, upper contact plugs 36B and 36D electrically connected to the upper ends of the resistance layers 32B and 32D are embedded in the first interlayer insulating film 22 and the second interlayer insulating film 23. The second connection wiring layer 39 electrically connects the resistance layers 32B and 32D to each other through the upper contact plugs 36B and 36D.

  The upper contact plugs 36A, 36B, 36C, and 36D are contact holes that expose the upper surfaces of the resistance layers 32A to 32D using, for example, a photolithography technique and an etching technique, and the first interlayer insulating film 22 and the second interlayer insulating film. It can be formed by forming the film 23 and embedding a conductive material in these contact holes by the CVD method.

  As shown in FIG. 6, the resistance layers 32A, 32B, 32C, and 32D are electrically connected to the upper wiring layers 35A, 35B, 35C, and 35D through the upper contact plugs 34A, 34B, 34C, and 34D, respectively. The upper layer contact plugs 34A to 34D are simultaneously formed in the same process as the upper layer contact plugs 36A, 36B, 36C, 36D. In FIG. 2, the upper wiring layers 35A, 35B, 35C, and 35D are not shown.

  The semiconductor device 1 has four resistance elements 5A, 5B, 5C, and 5D as components of a semiconductor integrated circuit. FIG. 7 is a diagram showing an equivalent circuit including these four resistance elements 5A, 5B, 5C, and 5D. The first resistance element 5A includes a resistance layer 32A, a well region 11A, and a contact plug 31A. The second resistance element 5B includes a resistance layer 32B, a well region 11B, and a contact plug 31B. The third resistance element 5C includes a resistance layer 32C, a well region 11C, and a contact plug 31C. The fourth resistance element 5D includes a resistance layer 32D, a well region 11D, and a contact plug 31D.

  The resistance elements 5A and 5C are connected in series with each other via the first connection wiring layer 38 to constitute one resistor, and the resistance elements 5B and 5D are connected in series with each other via the second connection wiring layer 39. To constitute another resistor. In this way, by connecting the resistor elements in series so that the geometric center of gravity between the resistors is close, it is possible to suppress variations in characteristics between resistors due to in-plane variations in process conditions during manufacturing. can do.

  As described above, in the semiconductor device 1 according to the first embodiment, the conductive layer 33B is located immediately above the region between the well regions 11A and 11B facing each other, and directly above the region between the well regions 11B and 11C facing each other. The conductive layer 33C is formed immediately above the region between the well regions 11C and 11D facing each other. The power supply voltage Vcc that does not turn on the parasitic transistor is provided in the conductive layers 33B, 33C, and 33D. Is applied. For this reason, even if an electric field is formed in the region between the well regions 11A, 11B, 11C, and 11D during the operation of the semiconductor device 1, it is possible to suppress generation of a leakage current due to the transition to the on state of the parasitic transistor. it can.

  In addition, since a thick insulating layer composed of the element isolation insulating film 20, the lower insulating film 21, and the first interlayer insulating film 22 is interposed between the conductive layers 33B, 33C, and 33D and the semiconductor substrate 10, the parasitic transistor Can be reliably prevented from transitioning to the ON state. Accordingly, it is possible to stabilize the potentials of the well regions 11A, 11B, 11C, and 11D by expanding the lateral dimensions of the well regions 11A, 11B, 11C, and 11D. For this reason, even if the power supply voltage Vcc fluctuates, it is possible to suppress the characteristic fluctuation of the resistance elements 5A to 5C while preventing the generation of a leakage current.

  Therefore, the semiconductor device 1 according to the present embodiment can realize the suppression of the leakage current and the stabilization of the resistance characteristics. For example, even when the resistance elements 5A to 5D are used for high voltage control (such as voltage division or step-down) of about several tens of volts, it is possible to achieve both suppression of leakage current and stabilization of resistance characteristics. It is.

  Further, as shown in FIGS. 2 and 7, the resistance elements 5A and 5C arranged every other one among the plurality of resistance elements 5A to 5D arranged in parallel constitute a first resistor. Since the resistive elements 5B and 5D arranged every other time constitute the second resistor, it is possible to suppress the variation in characteristics between the first and second resistors. Further, when a voltage is applied to the second connection wiring layer 39 shown in FIG. 4, a region between the well regions 11C and 11D and a region between the well regions 11C and 11B below the second connection wiring layer 39 are respectively provided. An electric field resulting from the applied voltage is formed. Even in such a situation, since there are conductive layers 33C and 33D fixed to the power supply voltage Vcc, it is possible to avoid the formation of inversion layers between the well regions 11C and 11D and between the well regions 11C and 11B. it can. Therefore, generation of a leak current between the first and second resistors can be suppressed.

  As mentioned above, although embodiment concerning this invention was described with reference to drawings, these are the illustrations of this invention and various forms other than the above are also employable. For example, as described above, the element isolation insulating film 20 is formed using a known LOCOS method or trench isolation technique, but is not limited thereto.

  As a modification of the above embodiment, there may be a semiconductor device structure in which the conductivity type of impurity diffusion regions such as well regions 11A to 11D formed in the semiconductor device 1 is reversed.

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 5A-5D resistive element, 10 Semiconductor substrate, 11A-11D well area | region, 12A-12D well contact area | region, 20 Element isolation insulation film, 21 Lower-layer insulation film, 22 1st interlayer insulation film, 23 2nd interlayer insulation Film, 31A to 31D contact plug, 32A to 32D resistance layer, 33 conductive wiring layer, 33A to 33E conductive layer, 34A to 34D, 36A to 36D upper layer contact plug, 35A to 35D upper layer wiring layer, 38 first connection wiring layer 39 Second connection wiring layer.

Claims (5)

A plurality of well regions formed in a semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A first resistance layer formed on the first insulating film;
A second resistance layer formed on the first insulating film and spaced apart from the first resistance layer;
A conductive layer formed above the semiconductor substrate between the first resistance layer and the second resistance layer;
A first well contact formed in any of the plurality of well regions and electrically connected to the first resistance layer;
A second well contact formed in any of the plurality of well regions spaced apart from the first well contact and electrically connected to the second resistance layer;
Have
The plurality of well regions are impurity diffusion regions of a first conductivity type formed in the semiconductor substrate,
The conductive layer, the plurality of the semi-conductor device you characterized in that it is fixed to the potential which does not form an inversion layer of the first conductivity type semiconductor region of the semiconductor substrate between the well region. A plurality of well regions formed in a semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A first resistance layer formed on the first insulating film;
A second resistance layer formed on the first insulating film and spaced apart from the first resistance layer;
A conductive layer formed above the semiconductor substrate between the first resistance layer and the second resistance layer;
A first well contact formed in any of the plurality of well regions and electrically connected to the first resistance layer;
A second well contact formed in any of the plurality of well regions spaced apart from the first well contact and electrically connected to the second resistance layer;
An interlayer insulating film interposed between the first insulating film and the conductive layer ;
Semi conductor arrangement you, comprising a. An interval in the lateral direction between the plurality of well regions parallel to the main surface of the semiconductor substrate is shorter than an interval in the lateral direction between the first resistance layer and the second resistance layer. The semiconductor device according to claim 1 or 2 . A third resistance layer formed on the first insulating film;
A third well contact formed in any one of the plurality of well regions spaced apart from the first well contact and the second well contact and electrically connected to the third resistance layer;
The semiconductor according to any one of claims 1 to 3, wherein a first further comprising a and the upper wiring layer electrically connecting the third resistor layer and the first resistive layer apparatus. A fourth resistance layer formed on the first insulating film;
The first well contact, the second well contact, and the third well contact are spaced apart from the plurality of well regions, and are electrically connected to the fourth resistance layer. A fourth well contact;
The semiconductor device according to claim 4 , further comprising: a second upper wiring layer that electrically connects the second resistance layer and the fourth resistance layer.

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