JP2008108799A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can reduce parasitic capacity of a resistor without adding new steps. <P>SOLUTION: The semiconductor device is provided with an insulation film 12, a resistor 13, an insulation film 14, a conductor 15, and an insulation film 16 on the surface of a p-type semiconductor substrate 10 in sequence from the side thereof. The resistor 13 and the conductor 15 are electrically connected with each other by a contact part 17 penetrating the insulation film 14. Thus, an RC circuit is comprised of parasitic capacity C<SB>10</SB>that is generated due to MOS structure formed of the conductor 15, the insulation film 14 and the resistor 13, resistance R of the resistor 13, and parasitic capacity C<SB>1</SB>that is generated due to MOS structure formed of the resistor 13, the insulation film 12 and the p-type semiconductor substrate 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a resistor that generates resistance on or in an insulating film formed on a semiconductor substrate.

  In a semiconductor device having a high-frequency circuit, resistance is generally generated in a wiring that supplies a predetermined voltage (for example, power supply voltage (Vcc) or ground (GND)) to high-frequency components included in the high-frequency circuit. A resistor is inserted. This resistor is normally formed on an insulating film for element isolation formed on a semiconductor substrate, and constitutes a MOS (Metal Oxide Semiconductor) structure together with the insulating film and the semiconductor substrate. For this reason, a parasitic capacitance is generated in the resistor due to the MOS structure. If the parasitic capacitance is large, the high frequency characteristics may be deteriorated. Therefore, conventionally, the insulating film is thickened to, for example, about 500 nm or more so that the influence of the parasitic capacitance does not reach the high frequency circuit.

Patent Document 1 below proposes a measure for reducing parasitic capacitance generated in an inductor by forming an n-type diffusion layer in a region facing the inductor in a p-type semiconductor substrate and providing a pn junction. Yes.
JP 2002-94009 A

  However, with the miniaturization and high performance of semiconductor devices, the thickness of the insulating film for element isolation has become very thin, and the parasitic capacitance tends to increase. For this reason, many measures for reducing the parasitic capacitance have been proposed. For example, the parasitic capacitance can be reduced by making the insulating film thicker by making the insulating film have a trench structure, or by configuring the resistor with metal instead of the conventionally used polysilicon. However, these measures have a problem that the manufacturing cost increases because an additional process is required.

  The present invention has been made in view of such problems, and an object thereof is to provide a semiconductor device capable of reducing the parasitic capacitance of a resistor without adding a new process.

  The first semiconductor device of the present invention includes a second conductive semiconductor layer, a first insulating film, and a resistor in this order from the first conductive semiconductor substrate side on the surface of the first conductive semiconductor substrate.

  In the first semiconductor device of the present invention, the second conductivity type semiconductor layer is formed in a region of the surface of the first conductivity type semiconductor substrate facing the resistor through the first insulating film. As a result, the parasitic capacitance generated due to the pn junction formed at the interface between the second conductive type semiconductor layer and the first conductive type semiconductor substrate becomes the MOS formed by the resistor, the first insulating film, and the semiconductor substrate. It is connected in series with the parasitic capacitance generated due to the structure.

  A second semiconductor device of the present invention includes a multilayer semiconductor layer formed by alternately stacking two or more semiconductor layers having different conductivity types on the surface of a first conductivity type semiconductor substrate, a first insulating film, and a resistor. In order from the side of the first conductivity type semiconductor substrate.

  In the second semiconductor device of the present invention, two or more semiconductor layers having different conductivity types are alternately stacked in a region of the surface of the first conductivity type semiconductor substrate facing the resistor via the first insulating film. A multilayer semiconductor layer is formed. As a result, a plurality of parasitic capacitances generated due to pn junctions formed at the interfaces of the semiconductor layers constituting the multilayer semiconductor layer are formed in the MOS structure formed by the resistor, the first insulating film, and the semiconductor substrate. It is connected in series with the parasitic capacitance generated.

  The third semiconductor device according to the present invention includes a first insulating film, a resistor, a second insulating film, and a conductor in this order from the first conductive semiconductor substrate side on the surface of the first conductive semiconductor substrate. Here, the resistor and the conductor are electrically connected by a contact portion that penetrates the second insulating film.

  In the third semiconductor device of the present invention, the conductor is disposed opposite to the resistor via the second insulating film and is electrically connected to the resistor via the contact portion. As a result, the parasitic capacitance (first parasitic capacitance) generated due to the MOS structure formed by the conductor, the second insulating film, and the resistor, the resistance of the resistor, the resistor, the first insulating film, and the semiconductor An RC circuit is constituted by the parasitic capacitance (second parasitic capacitance) generated due to the MOS structure formed by the substrate.

  According to the first semiconductor device of the present invention, the second conductivity type semiconductor layer is formed in the region of the surface of the first conductivity type semiconductor substrate facing the resistor via the first insulating film. The parasitic capacitance generated due to the pn junction formed at the interface between the second conductive type semiconductor layer and the first conductive type semiconductor substrate is caused by the MOS structure formed by the resistor, the first insulating film, and the semiconductor substrate. Can be connected in series to the parasitic capacitance generated. As a result, the parasitic capacitance of the resistor can be reduced without adding a new process. Here, the second conductivity type semiconductor layer can be formed at the same time when the source layer, drain layer, and well layer of the MOS transistor are formed in the first semiconductor device, for example, so that a new process is not added. The parasitic capacitance of the resistor can be reduced.

  According to the second semiconductor device of the present invention, two or more semiconductor layers having different conductivity types are alternately stacked in a region of the surface of the first conductivity type semiconductor substrate facing the resistor via the first insulating film. Since the multi-layer semiconductor layer is formed, a plurality of parasitic capacitances generated due to pn junctions formed at the interfaces of the semiconductor layers constituting the multi-layer semiconductor layer are formed in the resistor, the first The parasitic capacitance generated due to the MOS structure formed by the insulating film and the semiconductor substrate can be connected in series. As a result, the parasitic capacitance of the resistor can be significantly reduced as compared with the first semiconductor device. Here, since the multilayer semiconductor layer can be formed simultaneously with the formation of the source layer, drain layer, and well layer of the MOS transistor in the second semiconductor device, for example, the resistor without adding a new process Can be significantly reduced as compared with the first semiconductor device.

  According to the third semiconductor device of the present invention, the conductor is disposed opposite to the resistor via the second insulating film and is electrically connected to the resistor via the contact portion. An RC circuit can be configured by one parasitic capacitance, the resistance of the resistor, and the second parasitic capacitance. Here, since the value of the first parasitic capacitance can be changed by changing the size of the conductor, the size of the resistor can be set by appropriately setting the size of the conductor in consideration of the size of the second parasitic capacitance. Parasitic capacitance can be reduced. Here, the conductor can be formed simultaneously with the formation of a wiring layer for supplying a predetermined voltage to circuit components included in the third semiconductor device, for example. Further, the contact portion can be formed simultaneously with the formation of a via for electrically connecting the resistor and the wiring layer, for example. Therefore, the parasitic capacitance of the resistor can be reduced without adding a new process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
1A shows a partial cross-sectional configuration of the semiconductor device 1 according to the first embodiment of the present invention (cross-sectional configuration in the direction of arrows AA in FIG. 2), and FIG. Each of the configurations of parasitic capacitances that can be generated by the cross-sectional configuration of A) is shown. FIG. 2 illustrates the top surface configuration of the semiconductor device 1 with the insulating film 14 (described later) as the uppermost layer omitted.

  The semiconductor device 1 includes, for example, a circuit component (not shown) such as a MOS transistor, a wiring layer (not shown) for supplying a predetermined voltage (eg, Vcc, GND) to the circuit component, This is an IC (Integrated Circuit) chip formed with vias (not shown) for electrically connecting wiring layers to each other.

  The semiconductor device 1 includes an n-type semiconductor layer 11, an insulating film 12 (first insulating film), a resistor 13 and an insulating film 14 in this order from the p-type semiconductor substrate 10 side on the surface of a p-type semiconductor substrate 10. It is.

  The p-type semiconductor substrate 10 is composed of, for example, a silicon substrate doped with high-concentration p-type impurities, or a silicon substrate having an embedded layer (not shown) doped with high-concentration p-type impurities at the top. Has been.

  The n-type semiconductor layer 11 is made of, for example, silicon doped with an n-type impurity shallowly, and is formed by performing ion implantation on the surface of the p-type semiconductor substrate 10. Thereby, the n-type semiconductor layer 11 can be formed by the same process as the source layer and drain layer (not shown) of the n-type MOS transistor.

  The n-type semiconductor layer 11 is disposed to face the resistor 13. 1 and 2, the area of the surface of the n-type semiconductor layer 11 facing the resistor 13 is the area of the surface of the resistor 13 facing the n-type semiconductor layer 11 (hereinafter simply referred to as “the area of the resistor 13”). However, it may be equal to the area of the resistor 13 or may be smaller than the area of the resistor 13 in some cases.

  The insulating films 12 and 14 are made of, for example, silicon oxide, and the resistor 13 is made of, for example, polysilicon. For example, as illustrated in FIG. 2, the resistor 13 has a shape in which the wiring is folded into a rectangular shape. Although not shown, the resistor 13 is electrically connected to a circuit component such as a MOS transistor or a wiring layer. It is connected.

In the semiconductor device 1 having such a configuration, for example, a predetermined voltage is applied to a circuit component such as a MOS transistor via the resistor 13 to enable the circuit component to operate, and then an input terminal (not shown) of the semiconductor device 1 is shown. ), A signal corresponding to the input high-frequency signal propagates through the resistor 13. At this time, a parasitic capacitance C ₁ (see FIG. 1B) is generated due to the MOS structure formed by the resistor 13, the insulating film 12, and the n-type semiconductor layer 11. However, in the present embodiment, a parasitic capacitance C ₂ (see FIG. 1B) is generated due to a pn junction formed at the interface between the n-type semiconductor layer 11 and the p-type semiconductor substrate 10, and this parasitic capacitance is generated. since the capacitance C ₂ is connected in series with the parasitic capacitance C _1, it is possible to reduce the parasitic capacitance of the resistor 13. Thereby, deterioration of high frequency characteristics can be reduced.

  In the present embodiment, the n-type semiconductor layer 11 can be formed at the same time as the source layer and drain layer of the n-type MOS transistor. Therefore, in the manufacturing process of a conventional semiconductor device that does not include the n-type semiconductor layer 11. The parasitic capacitance of the resistor can be reduced without adding a new process.

[Modification of First Embodiment]
In the above embodiment, the case where the n-type semiconductor layer 11 is formed simultaneously with the source layer and the drain layer of the n-type MOS transistor has been exemplified. However, as shown in FIG. 3A, the n-type semiconductor layer 11 is formed. Instead of this, the n-type semiconductor layer 21 formed in a region deeper than the n-type semiconductor layer 11 may be formed simultaneously with an n-well layer (not shown) of a p-type MOS transistor, for example. Even in this case, the parasitic capacitance C ₃ (see FIG. 3B) is generated due to the pn junction formed at the interface between the n-type semiconductor layer 21 and the p-type semiconductor substrate 10, and the parasitic capacitance C ₃ is because it is connected in series with the parasitic capacitance C _1, it is possible to further reduce the parasitic capacitance of the resistor 13 without adding a new step.

Further, as shown in FIG. 4A, a p-type semiconductor layer 22 is provided on the surface layer of the n-type semiconductor layer 21, and the n-type semiconductor layer 21 is formed at the same time as an n-well layer of a p-type MOS transistor, for example. For example, the type semiconductor layer 22 may be formed simultaneously with a p-well layer (not shown) of an n-type MOS transistor. In this case, in addition to the parasitic capacitances C ₁ and C ₃ , the parasitic capacitance C ₄ due to the pn junction formed at the interface between the p-type semiconductor layer 22 and the n-type semiconductor layer 21 (FIG. 4B). And the parasitic capacitances C ₃ and C ₄ are connected in series to the parasitic capacitance C ₁ , so that the parasitic capacitance of the resistor 13 can be further reduced without adding a new process.

5A, an n-type semiconductor layer 23 is provided on the surface layer of the p-type semiconductor layer 22, and the n-type semiconductor layer 21 is formed simultaneously with the n-well layer of the p-type MOS transistor, for example. For example, the n-type semiconductor layer 22 may be formed simultaneously with the p-well layer of the n-type MOS transistor, and the n-type semiconductor layer 23 may be formed simultaneously with the source layer and the drain layer of the p-type MOS transistor, for example. In this case, in addition to the parasitic capacitances C ₁ , C ₃ , and C ₄ , the parasitic capacitance C ₅ (FIG. 5) is caused by the pn junction formed at the interface between the n-type semiconductor layer 23 and the p-type semiconductor layer 22. (See (B)), and these parasitic capacitances C ₃ , C ₄ , C ₅ are connected in series to the parasitic capacitance C ₁ , so that the parasitic capacitance of the resistor 13 can be further increased without adding a new process. Can be reduced.

[Second Embodiment]
6A shows a partial cross-sectional configuration of the semiconductor device 5 according to the second embodiment of the present invention (cross-sectional configuration in the direction of arrows BB in FIG. 8), and FIG. 6B shows FIG. Each of the configurations of parasitic capacitances that can be generated by the cross-sectional configuration of A) is shown. FIG. 7 shows a cross-sectional configuration in the direction of arrows CC in FIG. FIG. 8 shows the top surface configuration of the semiconductor device 5 with insulating films 14 and 16 (described later) omitted.

  The semiconductor device 5 is, for example, an IC chip on which circuit components, wiring layers, and vias are formed, as in the first embodiment.

  The semiconductor device 5 includes an n-type semiconductor layer 11, an insulating film 12 (first insulating film), a resistor 13, an insulating film 14 (second insulating film), a conductor 15, and an insulating film on the surface of a p-type semiconductor substrate 10. 16 are sequentially provided from the p-type semiconductor substrate 10 side, and the resistor 13 and the conductor 15 are electrically connected by a contact portion 17 penetrating the insulating film 14. Accordingly, the semiconductor device 5 is different from the configuration of the above embodiment in that the semiconductor device 5 further includes a conductor 15, an insulating film 16, and a contact portion 17. Therefore, in the following, description of the configuration, operation, and effect common to the above embodiment will be omitted as appropriate, and differences from the above embodiment will be mainly described.

  The conductor 15 is made of the same material as the wiring layer, for example, aluminum. Thereby, the conductor 15 can be formed by the same process as the wiring layer.

For example, as illustrated in FIG. 8, the conductor 15 has an L shape formed so as to substantially follow the pattern of the resistor 13. Each conductor 15, resistor 13 is intended for generating a parasitic capacitance _{C 10} due to the MOS structure formed by the insulating film 14 and conductive 15, such as a MOS transistor through each conductor 15 It does not have a function of supplying voltage to the circuit components. Accordingly, each conductor 15 can be formed by the same process as the wiring layer, but has a completely different function from the wiring layer.

The area of the surface of the conductor 15 facing the resistor 13 (hereinafter simply referred to as “the area of the conductor 15”) is generated between the resistor 13 and the p-type semiconductor substrate 10 as will be described later. The parasitic capacitance C _x is determined in consideration of the size of the parasitic capacitance C _x (see the equivalent circuit of the semiconductor device 5 shown in FIG. 9). For example, the parasitic capacitance C ₁₀ is as large as the parasitic capacitance C _x. It is decided to become. In this embodiment, the parasitic capacitance C _x corresponds to the parasitic capacitance C _1. Therefore, for example, the area of the conductor 15 becomes large when the parasitic capacitance C ₁ is large, the area of the conductor 15 when the parasitic capacitance C ₁ is small becomes small. Therefore, the area of the conductor 15 is larger than the area of the surface of the resistor 13 facing the conductor 15 (hereinafter, simply referred to as “the area of the resistor 13”), or equal to the area of the resistor 13. In some cases, the area of the resistor 13 may be smaller. The area of the conductor 15 can be adjusted by changing the width and the length in the extending direction.

  The insulating film 16 is made of, for example, silicon oxide like the insulating films 12 and 14, and can be formed by the same process as the interlayer insulating film formed between the wiring layers.

  The contact portion 17 is for electrically connecting the resistor 13 and each conductor 15, and is made of the same material as the via for electrically connecting the circuit component and the wiring layer to each other, for example, tungsten. . Thereby, the contact portion 17 can be formed by the same process as the via.

In the semiconductor device 5 having such a configuration, for example, a predetermined voltage is applied to a circuit component such as a MOS transistor via the resistor 13 to enable the circuit component to operate, and then an input terminal (not shown) of the semiconductor device 5 is shown. ), A signal corresponding to the input high-frequency signal propagates through the resistor 13. At this time, a parasitic capacitance C ₁ (see FIG. 6B) is generated due to the MOS structure formed by the resistor 13, the insulating film 12, and the n-type semiconductor layer 11. However, in the present embodiment, a parasitic capacitance C ₁₀ (see FIG. 6B) is generated due to the MOS structure formed by the resistor 13, the insulating film 14, and the conductor 15, and this parasitic capacitance C ₁₀ Is connected to the parasitic capacitance C ₁ and in parallel with the resistor R of the resistor 13, the parasitic capacitance C ₁ , the resistance R of the resistor 13, and the parasitic capacitance C ₁₀ are shown in FIG. An RC equivalent circuit is configured. Here, in the present embodiment, in FIG. 9, C _x corresponds to C ₁ , and C _y corresponds to C ₁₀ .

Here, it is possible to change the value of the parasitic capacitance C ₁₀ by changing the size of the conductor 15 (area), in consideration of the size conductor size and parasitic capacitance C ₁₀ of the resistance R of the resistor 13 By appropriately setting the size (area) of 15, the parasitic capacitance of the resistor 13 can be reduced. Thereby, deterioration of high frequency characteristics can be reduced.

  Further, in the present embodiment, the conductor 15 can be formed at the same time when the wiring layer is formed, for example. The insulating film 16 can be formed simultaneously with the formation of an interlayer insulating film formed between wiring layers, for example. Further, the contact portion 17 can be formed at the same time when, for example, a via for electrically connecting the resistor 13 and the wiring layer is formed. Thereby, the parasitic capacitance of the resistor 13 can be reduced without adding a new process to the manufacturing process of the conventional semiconductor device that does not include the conductor 15, the insulating film 16, and the contact portion 17.

[Modification of Second Embodiment]
In the above embodiment, the resistor 13, the insulating film 14 and conductive 15 is provided, the parasitic capacitance C ₁₀ utilizes to reduce the parasitic capacitance of the resistor 13 caused by the MOS structure formed by these However, as shown in FIG. 10A, the n-type semiconductor layer 11 is further formed in a region facing the resistor 13 on the surface of the p-type semiconductor substrate 10, for example, the source layer of the n-type MOS transistor. Further, parasitic capacitance C ₂ (see FIG. 10B) generated simultaneously with the drain layer and formed due to the pn junction formed at the interface between the n-type semiconductor layer 11 and the p-type semiconductor substrate 10 is also used. The parasitic capacitance of the resistor 13 may be reduced without adding a new process. In this case, since the parasitic capacitance C ₂ is connected in series with the parasitic capacitance C ₁ and the parasitic capacitance C _x (1 / C _x = 1 / C ₁ + 1 / C ₂ ) is reduced, the parasitic capacitance C ₁ Is large, the parasitic capacitance of the resistor 13 can be reduced by adjusting the size (area) of the conductor 15.

As shown in FIG. 11A, an n-type semiconductor layer 21 formed in a region deeper than the n-type semiconductor layer 11 is provided instead of the n-type semiconductor layer 11, and the n-type semiconductor layer 21 is formed. For example, it may be formed simultaneously with the n-well layer of the p-type MOS transistor. Thereby, the parasitic capacitance of the resistor 13 can be reduced without adding a new process. Even in this case, the parasitic capacitance C ₃ (see FIG. 11B) is generated due to the pn junction formed at the interface between the n-type semiconductor layer 21 and the p-type semiconductor substrate 10, and the parasitic capacitance C ₃ is connected in series with the parasitic capacitance C ₁ , and the parasitic capacitance C _x (1 / C _x = 1 / C ₁ + 1 / C ₃ ) is reduced. Therefore, even when the parasitic capacitance C ₁ is large, the conductive By adjusting the size (area) of the body 15, the parasitic capacitance of the resistor 13 can be reduced.

Also, as shown in FIG. 12A, a p-type semiconductor layer 22 is provided on the surface layer of the n-type semiconductor layer 21, and the n-type semiconductor layer 21 is formed at the same time as an n-well layer of a p-type MOS transistor, for example. For example, the type semiconductor layer 22 may be formed simultaneously with a p-well layer (not shown) of an n-type MOS transistor. Thereby, the parasitic capacitance of the resistor 13 can be reduced without adding a new process. Even in this case, pn formed between the resistor 13 and the p-type semiconductor substrate 10 at the interface between the p-type semiconductor layer 22 and the n-type semiconductor layer 21 in addition to the parasitic capacitances C ₁ and C _3. A parasitic capacitance C ₄ (see FIG. 12B) is generated due to the junction, and these parasitic capacitances C ₃ and C ₄ are connected in series to the parasitic capacitance C ₁ , and the parasitic capacitance C _x (1 / C _x = 1 / C ₁ + 1 / C ₃ + 1 / C ₄ ) is reduced, so that the parasitic capacitance of the resistor 13 is reduced by adjusting the size (area) of the conductor 15 even when the parasitic capacitance C ₁ is large. can do.

As shown in FIG. 13A, an n-type semiconductor layer 23 is provided on the surface layer of the p-type semiconductor layer 22, and the n-type semiconductor layer 21 is formed at the same time as an n-well layer of a p-type MOS transistor, for example. For example, the n-type semiconductor layer 22 may be formed simultaneously with the p-well layer of the n-type MOS transistor, and the n-type semiconductor layer 23 may be formed simultaneously with the source layer and the drain layer of the p-type MOS transistor, for example. Thereby, the parasitic capacitance of the resistor 13 can be reduced without adding a new process. Even in this case, in addition to the parasitic capacitances C ₁ , C ₃ , and C ₄ , the parasitic capacitance C ₅ (FIG. 13 (B)), and these parasitic capacitances C ₃ , C ₄ , C ₅ are connected in series to the parasitic capacitance C ₁ , and the parasitic capacitance C _x (1 / C _x = 1 / C ₁ + 1 / C). ₃ + 1 / C ₄ + 1 / C ₅ ) is small, and therefore the parasitic capacitance of the resistor 13 can be reduced by adjusting the size (area) of the conductor 15 even when the parasitic capacitance C ₁ is large. .

  Although the present invention has been described with reference to the embodiment and the modification, the present invention is not limited to the above-described embodiment and the like, and various modifications can be made.

  For example, in the above-described embodiment and the like, the case where the p-type semiconductor substrate 10 is used as the common substrate has been described, but the present invention can also be applied to the case where an n-type semiconductor substrate is used as the common substrate. However, in that case, the conductivity types described in the above embodiments and the like may be replaced from p-type to n-type and from n-type to p-type, respectively.

It is a section lineblock diagram of a semiconductor device concerning a 1st embodiment of the present invention. FIG. 2 is a top view of the semiconductor device of FIG. 1 (the insulating film 14 is omitted). It is a section lineblock diagram of a semiconductor device concerning one modification. It is a section lineblock diagram of a semiconductor device concerning other modifications. It is a section lineblock diagram of a semiconductor device concerning other modifications. It is a section lineblock diagram of one part of a semiconductor device concerning a 2nd embodiment of the present invention. It is a cross-sectional block diagram of the other part of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 7 is a top view of the semiconductor device of FIG. 6 (insulating films 14 and 16 are omitted). FIG. 7 is an equivalent circuit diagram of the semiconductor device of FIG. 6. It is a section lineblock diagram of a semiconductor device concerning one modification. It is a section lineblock diagram of a semiconductor device concerning other modifications. It is a section lineblock diagram of a semiconductor device concerning other modifications. It is a section lineblock diagram of a semiconductor device concerning other modifications.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-9 ... Semiconductor device, 10 ... p-type semiconductor substrate, 11, 21, 23 ... n-type semiconductor layer, 12, 14, 16 ... Insulating film, 13 ... Resistor, 15 ... Conductor, 17 ... Contact part, 22 ... p-type semiconductor layer.

Claims (9)

A semiconductor device comprising a surface of a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer, a first insulating film, and a resistor provided in that order from the first conductivity type semiconductor substrate side. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor layer is formed by performing ion implantation on a surface of the first conductivity type semiconductor substrate. A second insulating film and a conductor are provided in order from the side of the resistor on the surface of the resistor opposite to the first insulating film,
The semiconductor device according to claim 1, wherein the resistor and the conductor are electrically connected by a contact portion that penetrates the second insulating film. A multilayer semiconductor layer formed by alternately laminating two or more semiconductor layers having different conductivity types, a first insulating film, and a resistor are formed on the surface of the first conductivity type semiconductor substrate. A semiconductor device comprising: a semiconductor device in order from the side. 5. The semiconductor device according to claim 4, wherein each semiconductor layer constituting the multilayer semiconductor layer is formed by performing ion implantation on a surface of the first conductivity type semiconductor substrate. A second insulating film and a conductor are provided in order from the side of the resistor on the surface of the resistor opposite to the first insulating film,
The semiconductor device according to claim 4, wherein the resistor and the conductor are electrically connected by a contact portion that penetrates the second insulating film. On the surface of the first conductivity type semiconductor substrate, a first insulating film, a resistor, a second insulating film, and a conductor are sequentially provided from the first conductivity type semiconductor substrate side,
The semiconductor device, wherein the resistor and the conductor are electrically connected by a contact portion penetrating the second insulating film. The semiconductor device according to claim 7, further comprising a second conductivity type semiconductor layer in a region of the surface of the first conductivity type semiconductor substrate facing the resistor. The multilayer semiconductor layer formed by alternately laminating two or more semiconductor layers having different conductivity types in a region of the surface of the first conductivity type semiconductor substrate facing the resistor is provided. A semiconductor device according to 1.

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