JP2002118174A - Method for fabricating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate a semiconductor device satisfying the demand of reduction in size and weight with high reliability while eliminating generation of leakage current or variations in the resistance or characteristics without causing any increase in the fabrication process. SOLUTION: An oxide film 2b is formed on a semiconductor substrate 1, a first conductive film is deposited on the oxide film 2b and patterned to form a first electrode 5 and a second electrode 6, a first insulation film 8 is formed to cover the first and second electrodes 5 and 6, a second conductive film is deposited on the first insulation film 8 and patterned to form a third electrode 9 on the first electrode 5 and a fourth electrode 10 on the oxide film 2b, a second insulation film 11 is formed on the substrate 1 thus obtained, the second and first insulation film 11 and 8 are sequentially etched back to form a side wall spacer 12 on the side wall of the second and third electrodes 6 and 9 thus fabricating a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a capacitance and a resistance element are incorporated.

[0002]

2. Description of the Related Art In an electronic device equipped with a semiconductor device such as a semiconductor integrated circuit,
2. Description of the Related Art Capacitors and resistors used for oscillation circuits, boosting circuits, and the like have been manufactured separately from semiconductor devices and incorporated into electronic devices. This is because it is easier to obtain a desired circuit constant such as an oscillation frequency if each element such as a capacitance element and a resistance element is formed separately.

[0003] In recent years, with the spread of small and light electronic devices such as portable information terminals, there has been a further need for miniaturization and weight reduction of semiconductor devices, capacitance elements, resistance elements, and the like incorporated in these electronic devices. However, mounting a separately manufactured capacitive element or the like on a semiconductor device requires a predetermined area, which is contrary to the demand for miniaturization of electronic devices. Therefore, there is a demand for the development of a technique for manufacturing a capacitor element, a resistor element, and the like which have been separately formed on the same substrate on which a semiconductor device such as a transistor is formed. For example, as shown in FIGS. 2A to 2H, a method of manufacturing a capacitor and a resistor on the same silicon substrate at the same time as forming a transistor has been proposed.

First, as shown in FIG. 2A, a LOCOS oxide film 2a, a gate oxide film 2b, an element isolation region 2c,
A polysilicon layer is deposited and patterned on the silicon substrate 1 on which the well 3 and the P well 4 are formed, and the first electrode 5 is formed on the LOCOS oxide film 2a, and the N well 3 and the P well 4 are formed.
A second electrode 6 is formed on the upper gate oxide film 2b. Further, LDD regions 7a and 7b are formed in the P well 4 and the N well 3, respectively, using a resist pattern (not shown) formed using photolithography and an etching technique and the second electrode 6 as a mask.

Next, as shown in FIG. 2B, a first insulating film 17a is formed on the entire surface of the silicon substrate 1 and etched back to form sidewalls on the side walls of the first electrode 5 and the second electrode 6. The spacer 17 is formed (FIG. 2C). Then
As shown in FIG. 2D, the N
Using a resist pattern 18 having an opening in the MOS transistor region as a mask, phosphorus or arsenic is ion-implanted to form an N ⁺ diffusion region 15a, thereby forming an NMOS transistor. Similarly, as shown in FIG.
Ion implantation using a resist pattern 19 having an opening in the PMOS transistor region provided in the well 3;
A P ⁺ diffusion region 15b is formed, and a PMOS transistor is formed.

Subsequently, as shown in FIG. 2F, an insulating film 20 for setting a capacitance is formed on the entire surface, a polysilicon layer is formed thereon, and phosphorus is doped by ion implantation. The polysilicon layer is patterned to form a third electrode 9 on the first electrode 5 and a fourth electrode 1 on the LOCOS oxide film 2a.
0 (FIG. 2 (g)). Then, FIG.
As shown in (h), using the resist pattern 21 having a predetermined shape, phosphorus is ion-implanted into the third electrode 9 to lower the resistance of the third electrode 9. At this time, by covering the fourth electrode 10 with the resist pattern 21 so that phosphorus is not ion-implanted, the fourth electrode 10 can maintain the low efficiency at the time of forming the polysilicon layer as it is, and a desired high resistance element can be formed. Constitute.

By the above steps, the first electrode 5 and the third electrode 9 are capacitive elements, the second electrode 6 is a gate electrode of an NMOS or PMOS transistor having a sidewall spacer on a side wall, and the fourth electrode 10 is a resistive element. Are completed, respectively. As another method, a method shown in FIGS. 3A to 3D has been proposed (Japanese Patent Laid-Open No. 2-142177).

According to this method, first, FIG.
Similarly to (b), the first electrode 5 and the second electrode 6 are formed on the silicon substrate 1, and the insulating film 17a is formed thereon. Thereafter, as shown in FIG. 3A, the third electrode 9 and the LOCOS oxide film 2a are formed on the first electrode 5 in the same manner as described above.
The fourth electrode 10 is formed thereon. Subsequently, as shown in FIG. 3B, the insulating film 17a is etched back, and the side wall spacers 1 are formed on the side walls of the first electrode 5 and the second electrode 6.
7 is formed.

Next, as shown in FIG. 3C, the arsenic is formed using a resist pattern 22 having an opening in the NMOS transistor region provided in the P well 4 and the region where the first electrode 5 is formed as a mask. By implanting ions, the N ⁺ diffusion region 15a is formed to form an NMOS transistor, and at the same time, the entire surface of the third electrode 9 and a part of the first electrode 5 are doped with arsenic ions. Next, as shown in FIG. 3D, the PM provided in the N well 3
By implanting boron ions using the resist pattern 23 having an opening in the OS transistor region as a mask, a P ⁺ diffusion region 15b is formed to form a PMOS transistor, thereby completing a composite integrated circuit device.

[0010]

In the method shown in FIG. 2, the insulating film 17a for forming the sidewall spacer 17 and the insulating film 20 for setting the capacitance are separately formed. There is an advantage that the insulating film 20 can be made thinner. On the other hand, there is a problem that the manufacturing process becomes complicated. For example, since the steps of FIG. 2D and FIG. 2H perform the same ion implantation, FIG.
2 (h) may also serve as the ion implantation shown in FIG. 2 (h). However, in this case, the following problem newly arises, and it is difficult to simplify the manufacturing process.

That is, when both steps are performed, as shown in FIG. 4, when the ions are implanted into the third electrode 9, the insulating film 20 is formed on the NMOS transistor. Will be injected through
The sheet resistance of the N ⁺ diffusion region 15a will vary widely.

On the other hand, as shown in FIG. 5A, a method of ion implantation after etching back the insulating film 20 can be considered. Side wall spacer 17 of two electrodes 6
Is etched, the width of the sidewall spacer fluctuates, and the characteristics of the transistor fluctuate. Moreover, since the etching back of the insulating film 20 is performed using the third electrode 9 as a mask, the end surfaces of the third electrode 9 and the insulating film 20 become the same (see FIG. 5B), and the first electrode 5 and the 3 electrodes 9
The leakage current from the interface of the insulating film 20 becomes large, and the reliability as a capacitive insulating film is impaired.

In order to prevent a leakage current, FIG.
As shown in FIG. 6B, it is conceivable to leave the insulating film 20 on the outer periphery of the third electrode. For this purpose, a photolithography process for forming a resist pattern 31 as shown in FIG. Is required, and the manufacturing process cannot be simplified. In the method shown in FIG. 3, the insulating film 17a for forming the sidewall spacer 17 is shared with the insulating film for setting the capacitance, and the resistance of the third electrode 9 is reduced and the ion implantation for the N ⁺ diffusion region 15a is performed. Are performed simultaneously, so that the manufacturing process can be simplified.

However, since the width of the sidewall spacer generally depends on the thickness of the insulating film to be etched back, the insulating film needs to have a thickness of about 100 nm or more in order to form a necessary sidewall spacer. become. On the other hand, as the capacitance C is given by εS / d (S: area, d: thickness of the insulating film, ε: dielectric constant of the insulating film), the smaller the thickness of the insulating film, the larger the area. Can be larger. Therefore, when the insulating film for forming the sidewall spacer also serves as the capacitor insulating film, the electrode for forming the capacitor must be enlarged in order to obtain a large capacitance, which is against the demand for miniaturization of the semiconductor device. Becomes Moreover, in this manufacturing method,
Similarly to the above method, a leak current is generated from the end face of the insulating film forming the capacitor, and the reliability as the capacitor insulating film is impaired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to manufacture a semiconductor device meeting the demand for miniaturization and weight reduction with high reliability without generation of leakage current, variation in resistance value and characteristics. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured without increasing the number of steps.

[0016]

According to the present invention, (a)
Forming an oxide film on the semiconductor substrate; (b) depositing a first conductive film on the oxide film; patterning the first conductive film to form a first electrode and a second electrode separated from each other; Forming a first insulating film so as to cover the electrode and the second electrode; (d) depositing a second conductive film on the first insulating film, patterning the same, and forming a third electrode on the first electrode; Forming a fourth electrode on the oxide film, (e) forming a second insulating film on the obtained semiconductor substrate, and sequentially etching back the second insulating film and the first insulating film to form at least a fourth electrode; There is provided a method of manufacturing a semiconductor device in which side wall spacers are formed on side walls of a second electrode and a third electrode.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of manufacturing a semiconductor device according to the present invention, in step (a), first, an oxide film is formed on a semiconductor substrate. The semiconductor substrate used here is not particularly limited as long as it is generally used for a semiconductor device. For example, silicon, germanium or another element semiconductor, or GaAs, InGaAs or ZnSe or another compound semiconductor may be used. Various substrates such as a substrate, an SOI substrate, and a multilayer SOI substrate can be used. Among them, a silicon substrate is preferable. On this semiconductor substrate, LOCO
An element isolation region such as an S film, a trench oxide film, and an STI film, an element such as a transistor, a capacitor, and a resistor, a circuit formed by these elements, an interlayer insulating film, a wiring layer, and the like are combined to form a single or multi-layer structure. Is also good.
Further, one or more N-type or P-type impurity diffusion layers (wells) set to a predetermined impurity concentration may be formed.

The oxide film formed on the semiconductor substrate is preferably a silicon oxide film. The thickness is not particularly limited, and examples thereof include a film thickness functioning as a gate insulating film, a film thickness functioning as an element isolation film, a film thickness functioning as an interlayer insulating film, and the like. Specifically, 2
About 100 to 500 nm is appropriate. The oxide film is formed, for example, by a normal pressure CVD method, a low pressure CVD method, a plasma CVD method,
It can be formed by selecting from various methods such as a sputtering method.

In the step (b), a first conductive film is deposited on the oxide film and patterned to form a first electrode and a second electrode separated from each other. The first conductive film is not particularly limited as long as it is generally used as an electrode. For example, silicon such as polysilicon, monosilicon, and amorphous silicon; platinum, aluminum, copper,
Metals such as nickel; refractory metals such as tantalum, titanium, cobalt, and tungsten; and single-layer films or laminated films of silicide with these high-melting metals. Above all, a single-layer film of polysilicon, a film made of silicide with a high melting point metal, and a film made of polycide are preferable. When using polysilicon, it is preferable to set a predetermined resistance value by doping with an N-type or P-type impurity when or after forming the polysilicon film. The thickness of the first conductive film is, for example, about 100 to 300 nm. The first conductive film is formed by a sputtering method, a CVD method, a vacuum evaporation method, an EB method.
It can be formed by selecting from various methods such as a method.

The first conductive film can be patterned by forming a mask pattern having a predetermined shape by a known method, for example, a photolithography and etching process, and performing wet or dry etching using the mask pattern. By patterning the first conductive film, the first electrode and the second electrode can be formed separately from each other. These electrodes need only be formed at least one by one, and two or more electrodes may be formed. The shape and size of these first and second electrodes are not limited as long as the first electrode can function as a lower electrode of a capacitor and the second electrode can function as a gate electrode of an NMOS or PMOS transistor. There is no particular limitation. In addition, the degree of separation may be such that each electrode can independently perform a desired function.

In the step (c), a first insulating film is formed so as to cover the first electrode and the second electrode. Here, the first insulating film may be any as long as it can function as an insulating film of a capacitor. For example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film, etc., high-temperature oxide film: HTO)
Film), silicon nitride film, SOG film, PSG film, BSG
A single-layer film or a laminated film such as a film, a BPSG film, PZT, PLZT, a ferroelectric film or an anti-ferroelectric film. Further, the film thickness can be set according to its function, and for example, about 10 to 40 nm. These insulating films can be selected from various methods such as a sputtering method, a CVD method, an evaporation method, an EB method, a spin coating method, an MOCVD method, and a sol-gel method. Note that the first insulating film only needs to cover at least the first electrode and the second electrode. However, considering the simplicity of the manufacturing method, it is appropriate to form the first insulating film over the entire surface of the substrate.

In the step (d), a second insulating film is formed on the first insulating film.
A conductive film is deposited and patterned to form a third electrode on the first electrode and a fourth electrode on the oxide film. The second conductive film is selected from the materials listed above as the first conductive film.
The first conductive film can be appropriately selected and used so as to be the same as or different from the first conductive film. Among them, as the combination of the first conductive film and the second conductive film, polysilicon and polysilicon, high melting point silicide or polycide and polycide are preferable. The thickness of the second conductive film is, for example, 100 to 20.
About 0 nm. The patterning of the second conductive film can be performed in the same manner as the patterning of the first conductive film.

By patterning the second conductive film, a third electrode can be formed on the first electrode and a fourth electrode can be formed on the oxide film. These electrodes need only be formed at least one by one, and two or more electrodes may be formed. For example, two or more third electrodes may be formed on the first electrode, or one third electrode may be formed on two or more first electrodes. In addition, the fourth electrode is preferably formed in a state of being electrically separated from the semiconductor substrate. For example, when an element isolation film or the like is formed on the semiconductor substrate, the fourth electrode is formed on the semiconductor substrate. It is preferable to form a fourth electrode on the film. The shape and size of these third and fourth electrodes are not particularly limited, for example, as long as the third electrode can function as an upper electrode of the capacitor and the fourth electrode can function as a resistor.

In the step (e), a second insulating film is formed on the obtained semiconductor substrate, and the second insulating film and the first insulating film are sequentially etched back to form at least a side wall of the second electrode and the third electrode. A sidewall spacer is formed. The second insulating film can be appropriately selected from the above-described materials for the first insulating film so as to be the same as or different from the first insulating film. Among them, combinations of the first insulating film and the second insulating film include HTO film and HTO film, STO film and STO film.
Preferred are an iN film and an HTO film, and an LTO film and an HTO film.
The thickness of the second insulating film is, for example, 50 to 200 n in consideration of the characteristics and the like of the transistor in the obtained semiconductor device.
m.

The etch back is suitably performed by anisotropic dry etching, specifically, RIE.
At the time of this etchback, unless a mask is used, sidewall spacers are formed on the side walls of the first and fourth electrodes as well as the side walls of the second and third electrodes.

In the above manufacturing process, the NMOS
Alternatively, in order to form a PMOS transistor, before and after forming a sidewall spacer on the second electrode, ions are implanted using the second electrode as a mask by using an appropriate mask pattern, thereby forming a low-concentration impurity diffusion region (LDD).
Regions) and source / drain regions (high-concentration impurity diffusion regions). Specifically, it is preferable to form each before the step (c) and after the step (e). In addition, it is preferable that the ion implantation at the time of forming the source / drain regions is used for doping for reducing the resistance of the third electrode. At the time of this ion implantation, it is preferable to prevent the ion implantation into the fourth electrode by using a mask covering the fourth electrode.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, a LOCOS oxide film 2a, a gate oxide film 2b, an element isolation region 2c, an N well 3 and a P well 4 are formed on a silicon substrate 1 formed by a known method. A polysilicon layer having a thickness of about 100 to 300 nm is deposited as a first conductive film, and the polysilicon layer is patterned to form a first electrode 5 having a width of several μm to several hundred μm on the LOCOS oxide film 2a. To form Further, each of the gate oxide films 2b on the N well 3 and the P well 4 has a width of 0.18 to 0.5 μm.
The second electrode 6 of about m is formed.

Further, a resist pattern (not shown) having a predetermined shape is formed using photolithography and etching techniques, and 10 ¹³ to 10 ¹³ are formed in the NMOS transistor region using the resist pattern and the second electrode 6 as a mask.
The LDD region 7a is formed by implanting phosphorus ions at a dose of about 10 ¹⁴ cm ^{-2 and} an implantation energy of about 20 to 40 keV.
To form Similarly, a resist pattern (not shown) having a predetermined shape is formed, and using this resist pattern and the second electrode 6 as a mask, 1
0 ¹³ ~10 ¹⁴ cm ^-2 order of dose, an implantation energy of about 10～15KeV, LDD by implanting boron ions
The region 7b is formed.

Next, as shown in FIG. 1B, an HTO film having a thickness of about 10 to 40 nm is formed as a first insulating film 8 on the entire surface of the obtained silicon substrate 1 by a CVD method.
The first insulating film 8 functions as a capacitance setting insulating film. Subsequently, as shown in FIG. 1C, the first insulating film 8
On the entire upper surface, as a second conductive film, a film thickness of 100 to 200 nm
A polysilicon layer is deposited, phosphorus ions are implanted into the polysilicon layer at a dose of about 10 ¹⁵ to 10 ¹⁶ cm ⁻² , and the polysilicon layer is patterned to form a polysilicon layer on the first electrode 5. Then, a third electrode 9 having a width of several μm to several hundred μm is formed, and a third electrode 9 is formed on the LOCOS oxide film 2b.
The fourth electrode 10 having a width of about 1 to 3 μm is formed.

Further, as shown in FIG. 1D, a second insulating film 11 is formed on the entire surface of the obtained silicon substrate 1.
An HTO film having a thickness of about 100 to 200 nm is formed by a CVD method. Next, as shown in FIG. 1E, the first insulating film 8 and the second insulating film 11 are sequentially etched back to form sidewalls on the side walls of the first to fourth electrodes 5, 6, 9, and 10. The spacers 12 are respectively formed.

Thereafter, a resist is applied to the entire surface of the obtained silicon substrate 1 and, as shown in FIG. 1F, the NMOS transistor region provided in the P well 4 and the first An opening is formed in a region where the electrode 5 is formed, and arsenic ions are implanted by using the resist pattern 13 as a mask with a dose of about 10 ¹⁵ to 10 ¹⁶ cm ^{−2 and} an implantation energy of about 40 keV. An N ⁺ diffusion region 15a functioning as a source / drain region is formed to form an NMOS transistor, and at the same time, arsenic ions are doped into the entire surface of the third electrode 9 and a part of the first electrode 5, which are electrodes for determining capacitance. .

Next, a resist is applied to the entire surface of the obtained silicon substrate 1 and, as shown in FIG. 1 (g), an opening is formed in the PMOS transistor region provided in the N well 3 by photolithography and etching. Is formed, and using this resist pattern 14 as a mask, 10 ¹⁵
By implanting boron ions at a dose of about 10 ¹⁶ cm ^{-2 and} an implantation energy of about 10 keV, a P ⁺ diffusion region 15b is formed as a source / drain region to form a PMOS transistor. Through the above-described steps, the first electrode 5 and the third electrode 9 have a capacitance element, and the second electrode 6 has an NMO having a sidewall spacer 12 on a side wall.
Gate electrode of S and PMOS transistor, fourth electrode 1
0 forms a resistive element to complete the composite integrated circuit element.

As described above, according to the above embodiment, since the second insulating film and the first insulating film are sequentially etched back to form the sidewall spacers, the ions in the high concentration diffusion region for the source / drain regions are formed. The ion implantation can be performed without the intervention of the first insulating film at the time of the implantation, and this ion implantation can be combined with the ion implantation for reducing the resistance of the third electrode. Further, since the capacitor insulating film is formed by the first insulating film and the sidewall spacer is formed by the second insulating film, an insulating film having an optimum material and a film thickness corresponding to each function can be formed. That is, as a capacitive insulating film,
For example, by reducing the film thickness to 1/3, the capacity electrode can be reduced to 1/3.

Further, since a sidewall spacer can be formed also on the third electrode, the first insulating film can be etched back using the sidewall spacer as a mask. Leakage current can be prevented without increasing the number of mask steps.

[0035]

According to the present invention, in the step (e),
Since the second insulating film and the first insulating film are sequentially etched back to form the sidewall spacers, it is possible to prevent variations in characteristics due to subsequent ion implantation or the like.
In addition, since the first insulating film and the second insulating film are formed separately, it is possible to select an optimum material and a film thickness according to each function, and it is possible to realize miniaturization and high reliability. Become.
Further, since the first insulating film can be etched back using the side wall spacer of the second insulating film on the side wall of the third electrode as a mask, a leakage current between the first electrode and the third electrode is reduced by a masking process. Can be reliably prevented without increasing the number of semiconductor devices, and a highly reliable semiconductor device can be manufactured.

Before the step (c), low concentration impurity diffusion regions are formed on both sides of the second electrode, and after the step (e),
When the high-concentration impurity diffusion region is formed by ion implantation using the second electrode and the side wall spacer as a mask, and the third electrode is doped for lowering resistance, the first electrode and the third electrode are Since there is no insulating film serving as a mask, variations in resistance value, characteristics, and the like due to ion implantation can be prevented. Furthermore, when the ion implantation after the step (e) is performed using a mask covering the fourth electrode, a change in the resistance value of the fourth electrode can be prevented. In addition, the first conductive film and the second conductive film
In the case where the conductive film is formed of a single-layer film or a laminated film of polysilicon or high-melting-point metal silicide, the resistance value of each conductive film can be easily adjusted by ion implantation.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process diagram for carrying out a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic process sectional view for carrying out a conventional method of manufacturing a semiconductor device.

FIG. 3 is a schematic process sectional view for carrying out another conventional semiconductor device manufacturing method.

FIG. 4 is a schematic cross-sectional view of a main part of the semiconductor device during a process for describing a problem in the manufacturing method of FIG. 2;

FIG. 5 is a schematic cross-sectional view of a main part of a semiconductor device during a process for explaining another problem in the manufacturing method of FIG. 2;

FIG. 6 is a schematic cross-sectional view of a main part of a semiconductor device during a process for explaining still another problem in the manufacturing method of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate (semiconductor substrate) 2a Locos oxide film 2b Gate oxide film 2c Element isolation region 3 N well 4 P well 5 First electrode 6 Second electrode 7a, 7b LDD region 8 First insulating film 9 Third electrode 10 Fourth Electrode 11 Second insulating film 12 Sidewall spacer 13, 14 Resist pattern 15a N ⁺ diffusion region 15b P ⁺ diffusion region

Continued on front page F term (reference) 5F038 AC05 AC17 AR06 EZ13 EZ15 5F048 AA07 AC03 AC10 BA01 BB05 BB08 BB12 BC06 DA09 DA25 DA27 DA30

Claims (4)

[Claims] (A) an oxide film is formed on a semiconductor substrate; (b) a first conductive film is deposited on the oxide film and patterned to form a first electrode and a second electrode separated from each other. (C) a first electrode covering the first electrode and the second electrode;
(D) depositing a second conductive film on the first insulating film and patterning to form a third electrode on the first electrode and a fourth electrode on the oxide film; (E) forming a second insulating film on the obtained semiconductor substrate, sequentially etching back the second insulating film and the first insulating film to form sidewall spacers on at least side walls of the second electrode and the third electrode; A method for manufacturing a semiconductor device, comprising: 2. A low-concentration impurity diffusion region is formed on both sides of the second electrode before the step (c). After the step (e), a high concentration impurity diffusion region is formed by ion implantation using the second electrode and the side wall spacer as a mask. 2. The method according to claim 1, wherein the third electrode is doped for lowering the resistance simultaneously with the formation of the impurity diffusion region. 3. The method according to claim 2, wherein the ion implantation after the step (e) is performed using a mask covering the fourth electrode. 4. The method according to claim 1, wherein the first conductive film and the second conductive film are formed of a single-layer film or a stacked film of polysilicon and refractory metal silicide.