JP4708388B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a capacitive element formed of a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  In an LSI that configures a circuit using a MISFET, a method of forming a capacitive element using a gate oxide film of the MISFET is known. When the gate oxide film capacitance is used, a p-channel MISFET accumulation region or an n-channel MISFET inversion region is used.

  For example, in Japanese Patent Application Laid-Open No. 61-232656 (Patent Document 1), when forming a capacitor insulating film of a MOS capacitor at the same time as a process of forming a gate oxide film of a normal MOSFET, the film thickness of the gate oxide film is disclosed. In view of the problem that the area of the electrode has to be increased in order to obtain a desired capacitance value, the capacitance insulating film is formed in the process of forming a thin gate oxide film constituting the nonvolatile memory element. A technique for reducing the area of a MOS capacitor element by forming them simultaneously is disclosed.

Japanese Patent Application Laid-Open No. 5-235289 (Patent Document 2) shows that when the operating power supply voltage is reduced as the power consumption of the LSI is reduced, the conventional MOS type capacitor using the storage region has a large voltage dependency. In view of the conventional problem of the above, there is disclosed an LSI in which a MOS capacitor element is used in an inversion region over the entire input voltage range by controlling a threshold voltage (Vth).
Japanese Patent Laid-Open No. 61-232656 JP-A-5-235289

  In recent years, with the miniaturization of MISFETs, the gate oxide film thickness has been reduced to 3 nm or less. However, when the gate oxide film thickness is reduced to this level, defects in the gate oxide film and an increase in leakage current due to direct tunnel current become obvious, and it becomes difficult to obtain a stable capacitance when used in a capacitive element. It was.

  An object of the present invention is to provide a technique capable of reducing the leakage current of a capacitive element using a gate oxide film of a MISFET.

  Another object of the present invention is to provide a technique capable of forming a capacitor element having a low leakage current without increasing the number of manufacturing steps.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The present invention is a method for manufacturing a semiconductor integrated circuit device, wherein a first MISFET, a second MISFET formation region, a third MISFET formation region, and a capacitor element formation region of a semiconductor substrate are each provided with a first MISFET, a second MISFET, a third MISFET, and a capacitor element. There,
(A) forming first, third, and fourth wells of second conductivity type on the semiconductor substrate in the first MISFET formation region, the third MISFET formation region, and the capacitive element formation region, respectively;
(B) forming a first conductivity type second well having a conductivity type opposite to the second conductivity type on the semiconductor substrate in the second MISFET formation region;
(C) after the step (a), introducing a first conductivity type impurity into the third well;
(D) forming a second gate insulating film on the first, second, third and fourth wells, and then removing the second gate insulating film on the first well;
(E) after the step (d) , forming a first gate insulating film having a thickness smaller than that of the second gate insulating film on the first well;
(F) forming a polycrystalline silicon film on the first gate insulating film and the second gate insulating film;
(G) After selectively implanting ions into the polycrystalline silicon film, the polycrystalline silicon film is selectively patterned to form a first conductivity type on the first gate insulating film in the first MISFET formation region. A first gate electrode is formed, a second conductivity type second gate electrode is formed on the second gate insulating film in the second MISFET formation region, and a second gate electrode is formed on the second gate insulating film in the capacitor element formation region. Forming a first conductivity type third gate electrode, and forming a first conductivity type fourth gate electrode on the second gate insulating film in the third MISFET formation region;
(H) After the step (g), a step of forming first, third, and fourth semiconductor regions of the first conductivity type by implanting ions into the first, third, and fourth wells, respectively.
(I) a step of forming a second conductivity type second semiconductor region by ion implantation into the second well after the step (g);
(J) After the step (h) and the step (i), a step of forming a sidewall spacer on the side wall of the first, second, third and fourth gate electrodes,
(K) After the step (j), ions are implanted into the first, third, and fourth wells to show the first conductivity type and higher than the first, third, and fourth semiconductor regions. Forming each of fifth, seventh and eighth semiconductor regions having an impurity concentration;
(L) After the step (j), ion implantation is performed on the second well, thereby forming sixth semiconductor regions that exhibit the second conductivity type and have an impurity concentration higher than that of the second semiconductor region. The process of
Have
The third well serves as one of the two electrodes of the capacitive element, and the third gate electrode serves as the other electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A stable operation can be realized by reducing the leakage current of the capacitive element constituted by the MISFET.

  In addition, a capacitor element that operates stably even at a low power supply voltage can be formed without an increase in manufacturing steps.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor integrated circuit device of this embodiment is an example in which the present invention is applied to a complementary metal oxide semiconductor (CMOS) gate array. A semiconductor chip on which this CMOS gate array is formed is shown in FIG.

For example, in the central portion of the main surface of the semiconductor chip 1A made of single crystal silicon, a large number of basic cells 2 constituting the logic portion of the gate array are arranged in a matrix along the X and Y directions in the figure. . Each basic cell 2, the n-channel type MISFET Qn ₁ and p-channel type MISFET Qp _1, not shown in Figure 1 is constituted by combining a predetermined number, MISFET in each basic cell 2 _(Qn 1, Qp ₁₎ and between the base A desired logic function is realized by connecting the cells 2 based on the logic design.

  The connection for realizing the logic function is performed by, for example, an automatic placement and routing system (DA; Design Automation) using CAD (Computer Aided Design). The automatic placement and routing system automatically lays out a logic circuit designed and verified by using a macro cell or the like on the semiconductor chip 1A, and routes wiring to XY lattice coordinates virtually set on the logic circuit. Automatically lay out and connect logic circuits.

  The gate array of the present embodiment is not particularly limited, but has, for example, seven-layer wiring, and Cu (copper) from the first-layer wiring to the sixth-layer wiring (signal wiring and power supply wiring). ) And the seventh layer wiring (power supply wiring) is made of a metal mainly composed of an Al (aluminum) alloy.

An analog PLL (Phase Lock Loop) circuit 3 that converts an external reference clock into a clock having a predetermined frequency and outputs it to an internal circuit is disposed near the periphery of the logic unit. For example, as shown in FIG. 2, the PLL circuit 3 includes a phase comparator PFC, a charge pump circuit C.I. P. , Voltage-current conversion circuits VI _{1 to} VI ₃ , time-current conversion circuit TI, oscillation circuit C.I. C. O. And a frequency divider.

The charge pump circuit C.I. P. For example, as shown in FIG. 3, the n-channel MISFETs Qn ₂ and Qn ₃ , the p-channel MISFETs Qp ₂ and Qp _3, and the capacitive element C ₁ are included. One electrode of the capacitive element C ₁ is applied with GND (0 V), and the other electrode of the capacitive element C ₁ is electrically connected to the drains of the n-channel MISFET Qn ₃ and the p-channel MISFET Qp ₃ . The drains of the n-channel MISFET Qn ₃ and the p-channel MISFET Qp ₃ are electrically connected to the inputs of the voltage-current conversion circuits VI ₁ and VI ₂ . Charge pump circuit C.I. P. Generates a predetermined level of voltage by accumulating the phase difference signal (UP, DN) that is output from the phase comparator PFC charges corresponding to the capacitor C _1, a voltage as the output voltage (CPOUT) - Output to the current conversion circuits VI _{1 to} VI ₂ .

Around the logic unit, a plurality of input / output (I / O) buffer circuits 4 are arranged so as to surround the logic unit. Each output buffer circuit 4 is constituted by combining a predetermined number of n-channel type MISFET Qn ₄ and p-channel type MISFET Qp _4, not shown in Figure 1, the connection pattern between these MISFET _(Qn 4, Qp ₄₎ By changing the circuit function, an input buffer circuit as shown in FIG. 4A, an output buffer circuit as shown in FIG. 4B, or a bidirectional buffer circuit (not shown) is formed. .

  Around the input / output buffer circuit 4, bonding pads (external terminals) BP for electrical connection with an external device are arranged in a line along each side of the semiconductor chip 1A. These bonding pads BP are arranged at positions corresponding to the arrangement of the input / output buffer circuits 4, and each bonding pad BP and the corresponding input / output buffer circuit 4 are electrically connected via a wiring (not shown). Has been.

FIG. 5 is a cross-sectional view of an essential part of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 on which the CMOS gate array is formed. The left part of the figure is a region where the MISFETs (Qn ₁ , Qp ₁ ) constituting the basic cell 2 are formed, and the central part is the charge pump circuit C.I. P. The right side portion of the region where the capacitive element C ₁ is formed shows the region where the MISFETs (Qn ₄ , Qp ₄ ) constituting the input / output buffer circuit 4 are formed.

Of the MISFETs (Qn ₁ , Qp ₁ ) constituting the basic cell 2, the n-channel type MISFET Qn ₁ is formed in the p-type well 7 of the substrate 1 and mainly includes the gate oxide film 9A, the gate electrode 10A, and the n ⁺ -type semiconductor region. (Source, drain) 13. The p-channel type MISFET Qp ₁ is formed in the n-type well 8 of the substrate 1 and is mainly composed of a gate oxide film 9A, a gate electrode 10B, and a p ⁺ type semiconductor region (source, drain) 14 which are gate insulating films. Yes.

The gate oxide film 9A of the MISFET (Qn ₁ , Qp ₁ ) is formed with a thin film thickness (for example, 2.5 nm to 3 nm) in order to promote higher speed and higher performance of logic functions. Further, the gate electrodes 10A and 10B of the MISFETs (Qn ₁ and Qp ₁ ) are formed with their gate length being the minimum processing dimension (for example, 0.14 μm) of the circuit in order to promote the enlargement of the gate, In order to promote a reduction in resistance, a so-called polymetal structure is formed in which a barrier metal such as a WN film and a W (tungsten) film are stacked on a polycrystalline silicon film. Further, the gate electrodes 10A and 10B are formed of a polycrystalline silicon film that constitutes a part of the gate electrode 10A in order to lower the threshold voltage (Vth) and promote lowering of the circuit voltage and lowering of power consumption. The gate electrode 10B is doped with an n-type impurity (for example, As (arsenic)), and a polycrystalline silicon film constituting a part of the gate electrode 10B is doped with a p-type impurity (B (boron)). Yes.

On the other hand, among the MISFETs (Qn ₄ , Qp ₄ ) constituting the input / output buffer circuit 4, the n-channel type MISFET Qn ₄ is formed in the p-type well 7 of the substrate 1, and mainly a gate oxide film 9 B, which is a gate insulating film, The gate electrode 10C and the n ⁺ type semiconductor region (source, drain) 13 are configured. The p-channel MISFET Qp ₄ is formed in the n-type well 8 of the substrate 1 and is mainly composed of the gate oxide film 9B, the gate electrode 10D, and the p ⁺ -type semiconductor region (source, drain) 14.

The MISFET (Qn ₄ , Qp ₄ ) is formed with a looser design rule than the MISFET (Qn ₁ , Qp ₁ ) constituting the basic cell 2. Further, these MISFETs (Qn ₄ , Qp ₄ ) used for the interface with the outside operate at a voltage (for example, 3.3 V) higher than the operating voltage (for example, 1.5 V) of the MISFET constituting the internal circuit. Therefore, from the viewpoint of ensuring a breakdown voltage, the gate oxide films 9B are formed with a thick film thickness (for example, 6.5 nm). That is, the thickness of the gate oxide film 9B is configured to be larger than the thickness of the gate oxide film 9A. The gate electrodes 10C and 10D of these MISFETs (Qn ₄ and Qp ₄ ) are similar to the gate electrodes 10A and 10B of the MISFETs (Qn ₁ and Qp ₁ ) constituting the basic cell 2 and have a dual metal structure. It consists of

Charge pump circuit C.I. P. Capacitive element _{C 1} in is formed in the n-type well 8 of the substrate 1, the ^{n +} -type semiconductor region 13 for application mainly gate oxide film 9B, the gate electrode 10E and the n-type well 8 to the ground voltage (GND) It is configured. That is, the capacitive element _{C 1} is composed of a p-channel type MISFET. Further, n-type well 8 serves as one electrode of the capacitor C _1, the gate electrode 10E acts as the other electrode of the capacitor C _1, a gate oxide film 9B acts as a derivative film of the capacitive element C ₁ . The capacitive element _{C 1,} for example in order to secure the capacitance of about 50pF to 100pF, is composed of a large area of about 1 × ^{10 -4} cm ^2.

A gate oxide film 9B of the capacitive element _{C 1,} in order to reduce the leakage current, the output MISFET constituting the buffer circuit ₄ (Qn 4, Qp 4) The same large thickness as the gate oxide film 9B (for example 6 .5 nm). Further, the gate electrode 10E of the capacitive element _{C 1} is, MISFET (Qn _4, Qp ₄ constituting the gate electrode 10A, and 10B and the input-output buffer circuit 4 of the MISFET (Qn _1, Qp ₁₎ constituting the basic cell 2 ) In the same manner as the gate electrodes 10C and 10D. Furthermore, the capacitive element C ₁ is to operate stably even at a low supply voltage, n-type impurity (e.g., As) is doped to the polycrystalline silicon film constituting a part of the gate electrode 10E.

Figure 6 is a diagram showing the Vg-C characteristic of the capacitive element _{C 1,} which is constituted by p-channel type MISFET.

Since the capacitive element C ₁ uses the gate oxide film 9B having the same thickness as the MISFET (Qn ₄ , Qp ₄ ) constituting the input / output buffer circuit 4, the MISFET (Qn ₁₎ constituting the basic cell 2 is used. , Qp ₁ ), the leakage current is smaller than that of the capacitive element formed using the gate oxide film 9A having the same thin film thickness as that of Qp ₁ ). On the other hand, when the storage region of the p-channel type MISFET is used as a capacitive element, a stable capacitance cannot be obtained in a region where the gate input voltage is low, as indicated by a broken line in FIG. Therefore, in this embodiment, the polycrystalline silicon film constituting a part of the gate electrode 10E is doped with an n-type impurity (for example, As) to increase the threshold voltage of the p-channel MISFET. As a result, as shown by the solid line in FIG. 6, a stable capacitance can be obtained even in a region where the gate input voltage is low. P. Stable capacitance can be obtained both in the region where the output voltage (CPOUT) is high and in the low region.

As shown in FIG. 5, silicon oxide films 17 and 31 which are two-layer interlayer insulating films are formed on the MISFETs (Qn ₁ , Qp ₁ , Qn ₄ , Qp ₄ ) and the capacitive element C _1. Is formed. A plug electrode 23 is formed inside the contact holes 18 to 22 formed in the silicon oxide film 17, and first-layer wirings 24 to 30 are formed above the plug electrode 23. The plug electrode 23 is made of, for example, a barrier metal such as copper and TaN, or a tungsten film and a TiN film. Further, six layers of wirings are formed above these wirings 24 to 30 with an interlayer insulating film interposed therebetween, but their illustration is omitted.

  Next, a method for manufacturing the CMOS gate array of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 7, for example, a silicon oxide film 6 is buried in a groove formed in an element isolation region of the substrate 1 to form an element isolation groove 5. Next, an n-type impurity (for example, P (phosphorus)) is ion-implanted into a part of the substrate 1 using a photoresist film (not shown) as a mask, and a p-type impurity (for example, B) is ion-implanted into the other part. The p-type well 7 and the n-type well 8 are formed by heat-treating the substrate 1 to diffuse the impurities.

  Next, as shown in FIG. 8, after the substrate 1 is thermally oxidized, a thin gate oxide film 9 having a thickness of about 3 nm to 4 nm is formed on the surface of the substrate 1 (p-type well 7 and n-type well 8). As shown in FIG. 9, the upper portion of the substrate 1 in the capacitive element region (center portion in the figure) and the input / output buffer circuit region (right side portion in the figure) is covered with, for example, a photoresist film 41, and the basic cell region (left side in the figure). Part) of the gate oxide film 9 is removed by wet etching.

  Next, after removing the photoresist film 41, as shown in FIG. 10, the substrate 1 is thermally oxidized to form a film thickness on the surface of the substrate 1 (p-type well 7 and n-type well 8) in the basic cell region. A thin gate oxide film 9A having a thickness of about 2.5 nm to 3 nm is formed. At this time, the silicon oxide film 9 formed on the surface of the substrate 1 (p-type well 7 and n-type well 8) in the capacitive element region and the input / output buffer circuit region grows to form a thick gate having a thickness of about 6.5 nm. The oxide film 9B is formed. Thereafter, nitriding treatment may be performed on the gate oxide films 9A and 9B.

  Next, as shown in FIG. 11, after depositing a polycrystalline silicon film 42 having a thickness of about 70 nm on the substrate 1 by the CVD method, as shown in FIG. 12, the upper portion of the p-type well 7 in the basic cell region, The upper part of the substrate 1 (n-type well 8) in the capacitive element region and the upper part of the p-type well 7 in the input / output buffer circuit region are covered with, for example, a photoresist film 43, and polycrystalline silicon on the upper part of the n-type well 8 in the basic cell region. A p-type impurity (B) is ion-implanted into the polycrystalline silicon film 42 above the film 42 and the n-type well 8 in the input / output buffer circuit region.

The ion implantation of the p-type impurity is performed by using the gate electrode 10B of the p-channel type MISFET Qp ₁ constituting a part of the basic cell 2 and the gate electrode 10D of the p-channel type MISFET Qp ₄ constituting a part of the input / output buffer circuit 4 as p. To make a mold.

  Next, after removing the photoresist film 43, as shown in FIG. 13, the upper portion of the n-type well 8 in the basic cell region and the upper portion of the n-type well 8 in the input / output buffer circuit region are covered with a photoresist film 44. The polycrystalline silicon film 42 above the p-type well 7 in the basic cell region, the polycrystalline silicon film 42 above the substrate 1 (n-type well 8) in the capacitive element region, and the upper portion of the p-type well 7 in the input / output buffer circuit region. An n-type impurity (As) is ion-implanted into the polycrystalline silicon film 42.

The ion implantation of the n-type impurity is performed by the gate electrode 10A of the n-channel type MISFET Qn ₁ constituting the other part of the basic cell 2 and the gate of the n-channel type MISFET Qn ₄ constituting the other part of the input / output buffer circuit 4. This is done to make the electrode 10C n-type. Further, since the gate electrode 10E of the capacitor _{C 1} by the ion implantation is n-type, the threshold voltage of the p-channel type MISFET composing the capacitor _{C 1} increases (see FIG. 6).

As described above, in the above manufacturing method, the gate electrode of the capacitive element C ₁ is utilized by using the ion implantation process for making the gate electrode 10A of the n-channel type MISFET Qn ₁ and the gate electrode 10C of the n-channel type MISFET Qn ₄ n-type. An n-type impurity is introduced into 10E. That is, in the above-described manufacturing method, when introducing an n-type impurity into the gate electrode 10E of the capacitor element C _1, or preparing a photomask separately, it is not necessary or by ion implantation, the capacitance without increasing the manufacturing process can be n-type impurities are introduced into the gate electrode 10E of the element C _1.

  Next, after removing the photoresist film 44, as shown in FIG. 14, a WN film 45 having a thickness of about 5 nm and a W film 46 having a thickness of about 100 nm are deposited on the polycrystalline silicon film 42 by sputtering. Further, a silicon nitride film 15 which is a cap insulating film having a film thickness of about 50 nm is deposited thereon by CVD.

  Next, as shown in FIG. 15, the silicon nitride film 15, the W film 46, the WN film 45, and the polycrystalline silicon film 42 are sequentially dry-etched using the photoresist film 47 as a mask to form a gate electrode in the basic cell region. 10A and 10B are formed, gate electrodes 10C and 10D are formed in the input / output buffer circuit, and a gate electrode 10E is formed in the capacitor element region. The gate electrodes 10A to 10E may be formed of a material other than polymetal, for example, a polycrystalline silicon film, or a polycide film in which a tungsten silicide (WSi) film is stacked on the polycrystalline silicon film. .

Next, after removing the photoresist film 47, as shown in FIG. 16, the n-type well 8 in the basic cell region and the n-type well 8 in the input / output buffer circuit region are p-typed using a photoresist film (not shown) as a mask. Impurity ions (for example, B) are ion-implanted to form a p ⁻ type semiconductor region 12. The p type well 7 in the basic cell region, the n type well 8 in the capacitive element region, and the p type well 7 in the input / output buffer circuit region are formed. An n ⁻ type semiconductor region 11 is formed by ion implantation of an n type impurity (for example, P). The n ⁻ type semiconductor region 11 and the p ⁻ type semiconductor region 12 include a MISFET (Qn ₁ , Qp ₁ ) constituting the basic cell 2, a MISFET constituting the capacitive element C ₁ , and a MISFET (Qn constituting the input / output buffer circuit 4). ₄ , Qp ₄ ) to form an LDD (Lightly Doped Drain) structure.

Next, as shown in FIG. 17, a silicon nitride film (not shown) deposited on the substrate 1 by, eg, CVD is anisotropically etched to form sidewall spacers 16 on the sidewalls of the gate electrodes 10A to 10E. after, p ⁺ -type semiconductor region by ion implantation of p-type impurities (e.g., B) to the n-type well 8 of the n-type well 8 and the output buffer circuit area of the basic cell region by using a photoresist film (not shown) as a mask (Source, drain) 14 is formed, and n-type impurities (for example, P) are ion-implanted into the p-type well 7 in the basic cell region, the n-type well 8 in the capacitive element region, and the p-type well 7 in the input / output buffer circuit region. As a result, an n ⁺ type semiconductor region (source, drain) 13 is formed. Through the steps so far, the MISFET (Qn ₁ , Qp ₁ ) constituting the basic cell 2, the MISFET (Qn ₄ , Qp ₄ ) constituting the input / output buffer circuit 4 and the capacitive element C ₁ are completed.

  Next, as shown in FIG. 18, a silicon oxide film 17 is deposited on the substrate 1 by a CVD method, and then contact holes 18 are formed in the silicon oxide film 17 by dry etching using a photoresist film (not shown) as a mask. After forming ˜22, the plug electrode 23 is formed inside the contact holes 18-22. In order to form the plug electrode 23, for example, a TiN film 23a and a W film 23b are deposited by the CVD method in the contact holes 18-22 and on the silicon oxide film 17, and then the W film outside the contact holes 18-22. The 23b and TiN film 23a are removed by a chemical mechanical polishing method.

  Next, as shown in FIG. 19, after depositing a silicon oxide film 31 on the silicon oxide film 17 by a CVD method, wiring is performed on the silicon oxide film 31 by dry etching using a photoresist film (not shown) as a mask. Grooves 48 to 54 are formed.

  Thereafter, the first layer wirings 24 to 30 are formed in the wiring grooves 48 to 54, thereby obtaining the CMOS gate array shown in FIG. In order to form the first layer wirings 24 to 30, for example, a TiN film and a W film are deposited by CVD in the wiring grooves 48 to 54 and on the silicon oxide film 31, and then the wiring grooves 48 to 54 are formed. The external W film and TiN film are removed by a chemical mechanical polishing method. The first-layer wirings 24 to 30 are formed by forming a TaN film inside the wiring grooves 48 to 54 and on the silicon oxide film 31 and forming a Cu seed film on the TaN film. A Cu film is formed, and then the Cu seed film and Cu film are removed by a chemical mechanical polishing method.

According to this embodiment, the gate oxide film 9B constituting a part of a MISFET of the gate oxide film 9B the output buffer circuit 4 constituting a part of the capacitor element _{C 1} in the PLL circuit 3 (Qn _4, Qp ₄₎ the by configuring the same large thickness, it can be miniaturized CMOS gate array to obtain a capacitor element C ₁ low leakage current.

Further, according to this embodiment, without increasing the number and ion implantation process of the photomask, it is possible to form the capacitor element C _1.

(Embodiment 2)
Capacitive element _{C 1} of the PLL circuit 3 described above may be constituted by n-channel type MISFET as shown in FIG. 20. The capacitive element C ₁ is formed in the p-type well 7 of the substrate 1 and is mainly composed of the gate oxide film 9 B, the gate electrode 10 E, and the n ⁺ -type semiconductor region 13.

A gate oxide film 9B of the capacitive element _{C 1,} in order to reduce the leakage current, output the same large thickness as the gate oxide film 9B of MISFET constituting the buffer circuit _{4 (Qn 4, Qp 4)} ( e.g., 6. 5 nm). Further, the capacitive element C ₁ is to operate stably even at a low supply voltage, n-type impurity (e.g., As) is doped to the p-type well 7, the threshold voltage of the n-channel type MISFET, other n-channel It has been lowered than the threshold voltage of the type MISFET Qn _4.

Figure 21 is a diagram showing the Vg-C characteristic of the capacitive element _{C 1,} which is composed of n-channel type MISFET.

Since the capacitor element C ₁ uses the gate oxide film 9B having the same thickness as that of the MISFETs (Qn ₄ , Qp ₄ ) constituting the input / output buffer circuit 4, the gate oxide film 9A having a thin thickness is used. Compared with the case, the leakage current is reduced. On the other hand, when the inversion region of the n-channel type MISFET is used as a capacitive element, the threshold voltage increases as the gate oxide film thickness increases as shown by the broken line in FIG. In this case, a stable capacity cannot be obtained. Therefore, the p-type well 7 is doped with an n-type impurity (for example, As), and the threshold voltage of the n-channel MISFET is lowered to stabilize the gate input voltage even in a low region as shown by the solid line in FIG. Capacity will be obtained.

the capacitive element _{C 1,} which is composed of n-channel type MISFET is formed by the following method.

  First, as shown in FIG. 22, after element isolation trenches 5 are formed in the element isolation region of the substrate 1, an n-type impurity (for example, P) is ion-implanted into a part of the substrate 1 using a photoresist film (not shown) as a mask. Then, after p-type impurities (for example, B) are ion-implanted into other parts, the substrate 1 is heat-treated to diffuse the impurities, thereby forming the p-type well 7 and the n-type well 8. At this time, in this embodiment, the p-type well 7 is formed in the substrate 1 in the capacitive element region.

Next, as shown in FIG. 23, the upper part of the basic cell region and the upper part of the input / output buffer circuit region are covered with a photoresist film 60, and an n-type impurity (As) is added to the p-type well 7 which is the substrate 1 in the capacitive element region. Ion implantation. This ion implantation is performed in order to lower the threshold voltage of the n-channel type MISFET composing the capacitor _{C 1.}

  Next, after removing the photoresist film 60, the substrate 1 is thermally oxidized as shown in FIG. A thin gate oxide film 9A of about 3 nm is formed.

  Next, as shown in FIG. 25, the substrate 1 is covered with an oxidation-resistant insulating film 61 such as silicon nitride covering the upper portion of the substrate 1 (p-type well 7 and n-type well 8) in the basic cell region. Thermal oxidation. At this time, the silicon oxide film 9A formed on the surface of the substrate 1 (p-type well 7 and n-type well 8) in the capacitive element region and the input / output buffer circuit region grows to form a thick gate having a thickness of about 6.5 nm. The oxide film 9B is formed. The two types of gate oxide films 9A and 9B having different thicknesses may be formed by the same method as in the first embodiment.

Thereafter, the insulating film 61 in the basic cell region is removed, and the MISFETs (Qn ₁ , Qp ₁ ) and the input / output buffer circuit 4 that constitute the basic cell 2 according to the steps shown in FIGS. 11 to 17 of the first embodiment. MISFETs (Qn ₄ , Qp ₄ ) and a capacitive element C ₁ are formed.

As described above, even when the capacitive element C ₁ is configured by the n-channel type MISFET, the gate oxide film 9B constituting a part of the capacitive element C ₁ has the same thick gate oxidation as the MISFET (Qn ₄ , Qp ₄ ) of the input / output buffer circuit 4. By using the film 9B, leakage current can be reduced.

In the case of forming a capacitive element C ₁ to the p-type well 7 composed of n-channel type MISFET, and is required separately ion implantation process and the photomask for adjusting the threshold voltage of the n-channel type MISFET (See FIG. 23). However, the capacitor C ₁ of this embodiment uses the inversion region of the n-channel type MISFET, as compared to a capacitive element that uses an accumulation region of p-channel type MISFET, the gate input voltage more stable at low area capacitance There is an advantage that can be obtained.

(Embodiment 3)
In the first and second embodiments, the case where the present invention is applied to a CMOS gate array has been described. For example, as shown in FIG. 26, a macro cell such as a logic block, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or the like. The present invention can also be applied to a standard cell LSI for specific applications having Also in this case, the capacitor element for the analog circuit in the analog PLL circuit is formed using the thick gate oxide film 9B which is the same as the MISFET constituting the input / output buffer circuit 4 or the MISFETs QM and QS constituting the memory cell of DRAM or SRAM. Thus, the same effect as in the first embodiment can be obtained.

  Further, the present invention can be widely applied not only to gate arrays and standard cells but also to LSIs that form circuits using two or more MISFETs having different gate oxide film thicknesses, such as microcomputers. For example, in the case of a microcomputer, the analog gate in the analog PLL circuit is not formed by using the gate oxide film 9B which is the same as the MISFET constituting the input / output buffer circuit and the memory circuit, instead of the thin gate oxide film 9A of the MISFET constituting the microprocessor unit. A circuit capacitor element may be formed.

The capacitive element to which the present invention is applied is not limited to the analog circuit capacitive element in the analog PLL circuit described above. For example, as shown in FIG. Vdd, Vss) power supply and stabilizing capacitive element C _2, which is connected as a noise countermeasure between, as shown in FIG. 28 can also be applied to a filter capacitor element C _3.

  When the capacitive element is formed using the thick gate oxide film 9B, the leakage current can be reduced. On the other hand, the capacitance per unit area is smaller than when the capacitive element is formed using the thin gate oxide film 9A. . Therefore, the thickness of the gate oxide film needs to be properly used according to the purpose of use of the capacitive element.

As shown in FIG. 29 (a), a large chip area, when the circuit power consumption is also large such, for example capacitive element C ₁ and the power supply stabilizing capacitor element C ₂ in the analog PLL circuit are both thick gate oxide film It is formed using 9B. In this case, the capacitor element C ₁ in the analog PLL circuit, so that stable capacitance even at a low voltage is obtained, and constitute a p-channel type MISFET, the power supply stabilizing capacitor element C ₂ is the gate electrode power supply (Vdd) Therefore, a p-channel MISFET or an n-channel MISFET may be used.

Further, as shown in FIG. 29 (b), a small chip area, if such be the circuit power consumption low, for example, the capacitive element C ₁ only thick gate oxide film 9B in the analog PLL circuit leakage current is particularly problematic constituted by p-channel type MISFET using, power supply stabilizing capacitor element C ₂ uses a thin gate oxide film 9A in order to reduce its area. Power supply stabilizing capacitor element _{C 2} In this case, since to secure the gate electrode to a power source (Vdd), may be n-channel type MISFET any p-channel type MISFET.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is a technique useful when applied to the manufacture of a semiconductor integrated circuit device having a capacitive element composed of MISFETs.

It is a top view of the semiconductor chip which shows the CMOS gate array which is Embodiment 1 of this invention. It is a figure which shows the analog PLL circuit of the CMOS gate array which is Embodiment 1 of this invention. FIG. 3 is a diagram showing a charge pump circuit in the analog PLL circuit shown in FIG. 2. (A) is a figure which shows the input buffer circuit of the CMOS gate array which is Embodiment 1 of this invention, (b) is a figure which similarly shows an output buffer circuit. It is principal part sectional drawing of the semiconductor substrate which shows the CMOS gate array which is Embodiment 1 of this invention. It is a figure which shows the Vg-C characteristic of the capacitive element in the charge pump circuit shown in FIG. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the CMOS gate array which is Embodiment 2 of this invention. It is a figure which shows the Vg-C characteristic of the capacitive element comprised by n channel type MISFET. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS gate array which is Embodiment 2 of this invention. It is a top view of the semiconductor chip which shows the standard cell which is Embodiment 3 of this invention. It is a figure which shows the power supply stabilization capacitive element which is other embodiment of this invention. It is a figure which shows the filter capacitive element which is other embodiment of this invention. (A), (b) is a figure which shows the specific example of the usage method of the gate oxide film thickness according to the use purpose of a capacitive element.

Explanation of symbols

1A semiconductor chip 1 semiconductor substrate 2 basic cell 3 analog PLL circuit 4 input / output (I / O) buffer circuit 5 element isolation groove 6 silicon oxide film 7 p-type well 8 n-type well 9 gate oxide film 9A gate oxide film (thin gate) Oxide film)
9B Gate oxide film (thick gate oxide film)
10A to 10E Gate electrode 11 n ⁻ type semiconductor region 12 p ⁻ type semiconductor region 13 n ⁺ type semiconductor region (source, drain)
14 p ⁺ type semiconductor region (source, drain)
15 Silicon nitride film 16 Side wall spacer 17 Silicon oxide film 18 to 22 Contact hole 23 Plug electrodes 24 to 30 Wiring 31 Silicon oxide film 41 Photoresist film 42 Polycrystalline silicon films 43 and 44 Photoresist film 45 WN film 46 W film 47 The photoresist film 48 to 54 wiring groove 60 a photoresist film 61 insulating film BP bonding pad _C 1 -C ₃ capacitive element C. C. O. Oscillator C. P. Charge pump circuit PFC Phase comparator TI Time-current conversion circuit VI _{1 to} VI ₃ Voltage-current conversion circuit

Claims (9)

A method for manufacturing a semiconductor integrated circuit device comprising a first MISFET, a second MISFET, a third MISFET, and a capacitor element in a first MISFET formation region, a second MISFET formation region, a third MISFET formation region, and a capacitor element formation region of a semiconductor substrate, respectively.
(A) forming first, third, and fourth wells of second conductivity type on the semiconductor substrate in the first MISFET formation region, the third MISFET formation region, and the capacitive element formation region, respectively;
(B) forming a first conductivity type second well having a conductivity type opposite to the second conductivity type on the semiconductor substrate in the second MISFET formation region;
(C) after the step (a), introducing a first conductivity type impurity into the third well;
(D) forming a second gate insulating film on the first, second, third and fourth wells, and then removing the second gate insulating film on the first well;
(E) after the step (d) , forming a first gate insulating film having a thickness smaller than that of the second gate insulating film on the first well;
(F) forming a polycrystalline silicon film on the first gate insulating film and the second gate insulating film;
(G) After selectively implanting ions into the polycrystalline silicon film, the polycrystalline silicon film is selectively patterned to form a first conductivity type on the first gate insulating film in the first MISFET formation region. A first gate electrode is formed, a second conductivity type second gate electrode is formed on the second gate insulating film in the second MISFET formation region, and a second gate electrode is formed on the second gate insulating film in the capacitor element formation region. Forming a first conductivity type third gate electrode, and forming a first conductivity type fourth gate electrode on the second gate insulating film in the third MISFET formation region;
(H) After the step (g), a step of forming first, third, and fourth semiconductor regions of the first conductivity type by implanting ions into the first, third, and fourth wells, respectively.
(I) a step of forming a second conductivity type second semiconductor region by ion implantation into the second well after the step (g);
(J) After the step (h) and the step (i), a step of forming a sidewall spacer on the side wall of the first, second, third and fourth gate electrodes,
(K) After the step (j), ions are implanted into the first, third, and fourth wells to show the first conductivity type and higher than the first, third, and fourth semiconductor regions. Forming each of fifth, seventh and eighth semiconductor regions having an impurity concentration;
(L) After the step (j), ion implantation is performed on the second well, thereby forming sixth semiconductor regions that exhibit the second conductivity type and have an impurity concentration higher than that of the second semiconductor region. The process of
Have
The method of manufacturing a semiconductor integrated circuit device, wherein the third well acts as one of the two electrodes of the capacitive element, and the third gate electrode acts as the other electrode. A method for manufacturing a semiconductor integrated circuit device comprising a first MISFET, a second MISFET, a third MISFET, and a capacitor element in a first MISFET formation region, a second MISFET formation region, a third MISFET formation region, and a capacitor element formation region of a semiconductor substrate, respectively.
(A) forming first, second, and third wells of the first conductivity type on the semiconductor substrate in the first MISFET formation region, the second MISFET formation region, and the capacitive element formation region, respectively;
(B) forming a second well of a second conductivity type, which is a conductivity type opposite to the first conductivity type, on the semiconductor substrate in the third MISFET formation region;
(C) forming a second gate insulating film on the first, second, third and fourth wells, and then removing the second gate insulating film on the first well;
(D) after the step (c) , forming a first gate insulating film having a thickness smaller than that of the second gate insulating film on the first well;
(E) forming a polycrystalline silicon film on the first gate insulating film and the second gate insulating film;
(F) After selectively implanting ions into the polycrystalline silicon film, the polycrystalline silicon film is selectively patterned to form a second conductivity type on the first gate insulating film in the first MISFET formation region. A first gate electrode is formed, a second conductivity type second gate electrode is formed on the second gate insulating film in the second MISFET formation region, and a second gate electrode is formed on the second gate insulating film in the capacitor element formation region. Forming a first conductivity type third gate electrode, and forming a first conductivity type fourth gate electrode on the second gate insulating film in the third MISFET formation region;
(G) A step of forming first and second semiconductor regions of the second conductivity type by implanting ions into the first and second wells after the step (f),
(H) After the step (f), a step of forming third and fourth semiconductor regions of the first conductivity type by implanting ions into the third and fourth wells, respectively.
(I) a step of forming sidewall spacers on the side walls of the first, second, third and fourth gate electrodes after the steps (g) and (h);
(J) After the step (i), a fifth conductivity is obtained by implanting ions into the first and second wells, thereby exhibiting a second conductivity type and having a higher impurity concentration than the first and second semiconductor regions. And forming a sixth semiconductor region,
(K) After the step (i), a seventh conductivity is obtained by implanting ions into the third and fourth wells, thereby exhibiting the first conductivity type and having a higher impurity concentration than the third and fourth semiconductor regions. And an eighth semiconductor region, respectively,
Have
The method of manufacturing a semiconductor integrated circuit device, wherein the third well acts as one of the two electrodes of the capacitive element, and the third gate electrode acts as the other electrode. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising:
Forming an insulating film on the capacitive element;
Forming a plug connected to the seventh semiconductor region in the insulating film;
Forming a wiring connected to the plug on the insulating film;
A method for manufacturing a semiconductor integrated circuit device, comprising: In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 3,
The first and fifth semiconductor regions constitute source / drain regions of the first MISFET,
The second and sixth semiconductor regions constitute source / drain regions of the second MISFET,
The method of manufacturing a semiconductor integrated circuit device, wherein the fourth and eighth semiconductor regions constitute source / drain regions of the third MISFET. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 4,
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a silicide film on the polycrystalline silicon film of the first, second, third, and fourth gate electrodes. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 5,
The method of manufacturing a semiconductor integrated circuit device, wherein the first conductivity type is n-type and the second conductivity type is p-type. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 6,
The method of manufacturing a semiconductor integrated circuit device, wherein the second gate insulating film is formed of a silicon oxide film. In the manufacturing method of the semiconductor integrated circuit device according to claim 7,
A method of manufacturing a semiconductor integrated circuit device, wherein nitriding is performed when forming the second gate insulating film. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 8,
A method of manufacturing a semiconductor integrated circuit device, wherein the thickness of the first gate insulating film is 3 nm or less.

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