CN113078159B - Integrated circuit chip with decoupling capacitor and method for manufacturing the same - Google Patents
Integrated circuit chip with decoupling capacitor and method for manufacturing the same Download PDFInfo
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- CN113078159B CN113078159B CN202110305307.2A CN202110305307A CN113078159B CN 113078159 B CN113078159 B CN 113078159B CN 202110305307 A CN202110305307 A CN 202110305307A CN 113078159 B CN113078159 B CN 113078159B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 139
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 72
- 229920005591 polysilicon Polymers 0.000 claims abstract description 67
- 239000010410 layer Substances 0.000 claims description 156
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 120
- 239000004065 semiconductor Substances 0.000 claims description 84
- 239000000758 substrate Substances 0.000 claims description 82
- 230000015654 memory Effects 0.000 claims description 52
- 235000012239 silicon dioxide Nutrition 0.000 claims description 52
- 239000000377 silicon dioxide Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 claims description 3
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 10
- 238000003860 storage Methods 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical group [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Abstract
The invention provides an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof, wherein the decoupling capacitor is formed based on a polysilicon gate and a high-k dielectric layer, the decoupling capacitor can be integrated in a standard CMOS process, and compared with the original standard CMOS process, only one additional mask is added, so that the process is simple, and the manufacturing cost is low. In addition, the reasonable design can be carried out on the material selection and the thickness of the high-k dielectric layer, so that the capacitance density and the leakage performance of the formed decoupling capacitor are similar to those of the MIM capacitor, and the polysilicon depletion of the decoupling capacitor is controllable, so that the higher performance requirement of devices of 28nm and below technical nodes is met.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to an integrated circuit chip with decoupling capacitors and a method for manufacturing the same.
Background
In a CMOS IC (integrated circuit) chip having a logic circuit and a memory, since circuit components such as a power bus resistor and a current switch cause noise, it is generally necessary to connect a large decoupling capacitor to a power supply, decouple a corresponding part of a circuit from another part of the circuit, and shunt the noise through the decoupling capacitor, thereby canceling a power supply voltage drop caused by the noise, and further avoiding the noise from affecting the reliability of the circuit or causing a circuit failure.
The decoupling capacitors currently required for CMOS IC chips for logic and memory applications are typically built based on MOS capacitors, which are formed with the thinnest silicon oxide gate oxide layer on the chip (i.e., with a silicon oxide film formed along with the gate oxide layer of a low voltage MOS transistor), which have high capacitance density, low leakage current, and low cost compared to metal-insulator-metal decoupling capacitors (MIMs). However, when the integrated circuit chip technology enters a technology node of 28nm or below, the silicon dioxide gate oxide layer is too thin and is easy to tunnel, so that leakage current occurs, and the use of the MOS capacitor as a decoupling capacitor is limited.
Disclosure of Invention
The invention aims to provide an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof, which not only can make a MOS capacitor used as the decoupling capacitor compatible with a CMOS process, but also can avoid the problem that the conventional MOS capacitor cannot be used for the decoupling capacitor of an integrated circuit chip with a 28nm or below technology node due to the leakage current problem.
In order to achieve the above object, the present invention provides a method for manufacturing an integrated circuit chip having decoupling capacitors, comprising the steps of:
providing a semiconductor substrate with a logic region and a capacitance region, and depositing a high-k dielectric layer with dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
patterning the high-k dielectric layer to remove the high-k dielectric layer of the logic region and form a capacitance medium of at least one decoupling capacitor in the capacitance region;
forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic region;
depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region and a polysilicon plate stacked on the capacitance dielectric in the capacitance region;
performing source-drain ion implantation on the semiconductor substrate by taking the polysilicon gate and the polysilicon polar plate as masks to form corresponding logic transistors in the logic region and corresponding decoupling capacitors in the capacitor region, wherein each decoupling capacitor is a MOS capacitor with the corresponding polysilicon polar plate;
and forming a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure is used for electrically connecting at least one logic transistor and at least one polysilicon pole plate to the power line, and the other part is used for electrically connecting at least one logic transistor and the semiconductor substrate to the ground line.
Optionally, shallow trench isolation structures are formed in the semiconductor substrate to electrically isolate each logic transistor from each decoupling capacitor.
Optionally, a silicon dioxide interfacial layer is formed on the surface of the semiconductor substrate prior to depositing a high-k dielectric layer having a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate.
Optionally, when the high-k dielectric layer of the logic region is removed and the corresponding high-k dielectric layer in the capacitor region is reserved, the silicon dioxide interface layer of the logic region is also removed and the corresponding silicon dioxide interface layer in the capacitor region is reserved, so that the finally formed capacitor dielectric of the decoupling capacitor comprises the silicon dioxide interface layer and the high-k dielectric layer which are sequentially stacked.
Optionally, the high-k dielectric layer is a structure formed by single-layer high-k dielectric materials or a composite structure formed by stacking multiple layers of high-k dielectric materials, and the high-k dielectric materials comprise at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide and aluminum oxide.
Optionally, the logic area is provided with at least a first area and a second area with different working voltages; the step of forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic region comprises the following steps: and forming silicon dioxide gate oxide layers with different thicknesses on the semiconductor substrate of the first region and the second region.
Optionally, a silicon dioxide gate oxide layer is formed on the semiconductor substrate of the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process.
Optionally, the semiconductor substrate provided further has a storage region, and the manufacturing method further includes forming at least one memory cell in the storage region; and in the metal wiring process, the memory cell is electrically connected with the corresponding logic transistor.
Based on the same inventive concept, the present invention also provides an integrated circuit chip with decoupling capacitor, which is formed by the method for manufacturing the integrated circuit chip with decoupling capacitor, the integrated circuit chip comprises: the semiconductor device comprises a semiconductor substrate with a logic region and a capacitance region, at least one logic transistor formed in the logic region of the semiconductor substrate, at least one decoupling capacitor formed in the capacitance region of the semiconductor substrate, a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line, wherein one part of the metal interconnection structure is used for electrically connecting at least one logic transistor and the polycrystalline silicon polar plate of the decoupling capacitor to the power line, and the other part is used for electrically connecting at least one logic transistor and the semiconductor substrate to the ground line.
Optionally, the semiconductor substrate further has a memory region, a memory having at least one memory cell is formed in the memory region of the semiconductor substrate, and a further portion of the metal interconnect structure electrically connects the memory cell with at least one of the logic transistors.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. in the invention, at least a high-k dielectric layer is used as a capacitance medium of the MOS capacitor (namely, decoupling capacitor), and when the MOS capacitor (namely, decoupling capacitor) has the same thickness as the capacitance medium layer of the MOS capacitor in the prior art, the characteristics of the high-k dielectric material which is different from silicon dioxide can be utilized, so that the leakage current is reduced, and the capacitance density is improved, thereby the MOS capacitor can be used as the decoupling capacitor of an integrated circuit chip with the technical node of 28nm or below.
2. In the invention, the high-k dielectric layer is used as the capacitance medium of the MOS capacitor, so compared with the scheme of directly using the silicon dioxide gate oxide layer as the capacitance medium of the MOS capacitor in the existing CMOS process, the invention has the advantages of only one more accessory mask for patterning the high-k dielectric layer, compatibility with the original CMOS process, simple process and low cost.
Drawings
Fig. 1 is a flow chart of a method of fabricating an integrated circuit chip with decoupling capacitors according to an embodiment of the present invention.
Fig. 2 to 8 are schematic cross-sectional views of devices in a method for manufacturing an integrated circuit chip with decoupling capacitors according to an embodiment of the present invention.
Fig. 9 to 10 are schematic cross-sectional views of devices in a method for manufacturing an integrated circuit chip with decoupling capacitors according to another embodiment of the present invention.
Fig. 11 to 14 are cross-sectional structure examples of decoupling capacitors formed in an embodiment of the present invention.
Detailed Description
The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1, an embodiment of the invention provides a method for manufacturing an integrated circuit chip with decoupling capacitors, which includes the following steps:
s1, providing a semiconductor substrate with a logic region and a capacitance region, and depositing a high-k dielectric layer with dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
s2, patterning the high-k dielectric layer through photoetching and etching processes to remove the high-k dielectric layer of the logic region and form a capacitance medium of at least one decoupling capacitor in the capacitance region;
s3, forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic region;
s4, depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region and form at least one polysilicon plate of decoupling capacitor stacked on the capacitor dielectric in the capacitor region;
s5, performing source-drain ion implantation on the semiconductor substrate by taking the polycrystalline silicon grid electrode and the polycrystalline silicon polar plate as masks to form corresponding logic transistors in the logic region and corresponding decoupling capacitors in the capacitor region, wherein each decoupling capacitor is a MOS capacitor with the corresponding polycrystalline silicon polar plate;
and S6, forming a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure is used for electrically connecting at least one logic transistor and at least one polysilicon pole plate to the power line, and the other part is used for electrically connecting at least one logic transistor and the semiconductor substrate to the ground line.
Referring to fig. 2, in step S1, first, a semiconductor substrate 100 is provided, the semiconductor substrate 100 may be any suitable substrate material known to those skilled in the art for manufacturing PMOS transistors and NMOS transistors, such as silicon, germanium, silicon-on-insulator, silicon-germanium-on-insulator, etc., and a silicon dioxide interface layer 103 is formed on the surface of the semiconductor substrate 100 by a thermal oxidation process, and the thickness of the silicon dioxide interface layer 103 may beFor example +.>Then, the well ion implantation may be performed on the multiple regions of the semiconductor substrate 100, and then the shallow trench isolation Structure (STI) 101 may be formed in the semiconductor substrate 100, or the shallow trench isolation Structure (STI) 101 may be formed in the semiconductor substrate 100, and then the well ion implantation may be performed on the multiple regions of the semiconductor substrate 100, so as to define the logic region I, each transistor region in the logic region I, and the capacitor region II. In the present embodiment, a high voltage transistor region (HV), i.e., a first region, and a low voltage transistor region (LV, i.e., a second region) with different operating voltages are defined in the logic region I, and a deep well 102a of a first conductivity type is formed in the semiconductor substrate 100 of the high voltage transistor region (HV), a high voltage well 102b of a second conductivity type is formed in the deep well 102a of the first conductivity type, a low voltage well 102c is formed in the semiconductor substrate 100 of the low voltage transistor region (LV), a low voltage well 102d is formed in the semiconductor substrate 100 of the capacitor region II, wherein the low voltage wells 102c and 102d are formedThe low-voltage well 102d may be formed using a same well ion implantation process and has a smaller implantation depth than the high-voltage well 102b. As an example, when it is desired to fabricate a high-voltage NMOS transistor in a high-voltage transistor region (HV), fabricate a low-voltage NMOS transistor in a low-voltage transistor region (LV), fabricate an N-type MOS capacitor (i.e., decoupling capacitor) in a capacitor region II, the deep well 102a of the first conductivity type is a deep N-well (DNW), the high-voltage well 102b of the second conductivity type is a high-voltage P-well (HV-PW), the low-voltage well 102c is a low-voltage N-well (LV-NW), and the low-voltage well 102d may be a low-voltage N-well (LV-NW) or a low-voltage P-well (LV-PW). Shallow trench isolation Structures (STI) 101 may enable electrical isolation between each of the logic transistors and each of the decoupling capacitors that are finally formed. Thereafter, a high-k dielectric layer 104 having a dielectric constant k higher than that of silicon dioxide, for example, a dielectric constant k higher than 3.9 or not lower than 7, is deposited on the surfaces of the shallow trench isolation Structure (STI) 101 and the silicon dioxide interface layer 103. The high-k dielectric layer 104 may be a single-layer high-k dielectric material or a composite structure formed by stacking multiple layers of high-k dielectric materials, wherein the materials of the high-k dielectric materials are determined according to the leakage current performance requirement and capacitance density requirement of the required MOS capacitor, and the materials may include silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), zirconium oxide (ZrO) and aluminum oxide (Al) 2 O 3 ) At least one of them. As an example, the high-k dielectric layer 104 is Al 2 O3 layer, hfO layer, al 2 O 3 Composite structure with layers stacked in sequence or Al 2 O3 layer, zrO layer, al 2 O 3 A composite structure of layers stacked in sequence.
In the above example, the silicon dioxide interface layer 103 is formed on the semiconductor substrate 100 before the well ion implantation and the STI formation, and the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 by a thermal oxidation process before the well ion implantation and the STI formation, the pad oxide layer may be removed after the well ion implantation and the STI formation, and the silicon dioxide interface layer 103 may be formed on the surfaces of the semiconductor substrate 100 and the STI 101 by a thermal oxidation process again to avoid the performance influence of the well ion implantation process on the silicon dioxide interface layer 103 used as a capacitor medium subsequently. In another embodiment of the present invention, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 by a thermal oxidation process prior to the well ion implantation and STI formation, and removed after the well ion implantation and STI formation, and the formation of the silicon dioxide interface layer 103 may be omitted, depositing the high-k dielectric layer 104 directly on the surfaces of the semiconductor substrate 100 and STI 101.
Referring to fig. 2, in step S2, a patterned photoresist layer is formed by a series of photolithography processes such as photoresist coating, exposure, and development, so as to define a region of a capacitor medium in the capacitor region II for forming a MOS capacitor (i.e., a decoupling capacitor); then, the high-k dielectric layer 104 is etched by using the patterned photoresist layer as a mask through a dry etching process or a wet etching process, so as to remove the high-k dielectric layer 104 in the logic region I, and pattern the corresponding high-k dielectric layer 104 in the capacitor region II, where the etching is stopped on the surface of the semiconductor substrate 100 (i.e., the surface of the low-voltage well 102d of the capacitor region II), so as to form a capacitor medium of at least one decoupling capacitor in the capacitor region II. In this embodiment, the capacitance medium of each decoupling capacitor includes a high-k dielectric layer 104 and a silicon dioxide interfacial layer 103 below the high-k dielectric layer, and the lower plate of each decoupling capacitor is the semiconductor substrate 100 (i.e., the low-voltage well 102d of the capacitor region II).
Referring to fig. 4, in step S3, a silicon dioxide gate oxide layer is formed on the semiconductor substrate 100 of the logic region I by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process. In this embodiment, since the thicknesses of the silicon oxide gate oxide layers required for the low-voltage transistor and the high-voltage transistor are different, it is necessary to form the silicon oxide gate oxide layers required for the low-voltage transistor and the high-voltage transistor in multiple steps. As one example, first, a silicon oxide layer 105 is formed on a surface of a semiconductor substrate 100 through a thermal oxidation process, an atomic layer deposition process, or a chemical vapor deposition process; then, the silicon oxide layer 105 on the surface of the semiconductor substrate 100 of the low voltage transistor region LV and the capacitor region II is removed by a photolithography combined with etching method, and the silicon oxide layer 105 on the surface of the semiconductor substrate 100 of the high voltage transistor region HV is remained; next, a silicon dioxide layer 106 is formed on the surfaces of the semiconductor substrate 100 and the silicon dioxide layer 105 through a thermal oxidation process, an atomic layer deposition process or a chemical vapor deposition process, and the thickness of the silicon dioxide layer 106 meets the thickness requirement of the gate oxide layer of the low voltage transistor. Thus, in the high-voltage transistor region HV, the oxide layer structure in which the silicon oxide layer 105 and the silicon oxide layer 106 are stacked serves as a thicker silicon oxide gate oxide layer required for the high-voltage MOS transistor, and in the low-voltage transistor region LV, the silicon oxide layer 106 serves as a thinner silicon oxide gate oxide layer required for the low-voltage MOS transistor.
Referring to fig. 4 and 5, in step S4, firstly, a polysilicon layer 107 is deposited on the silicon dioxide layer 106 and the high-k dielectric layer 104 by a chemical vapor deposition process, and the polysilicon layer 107 is planarized by a chemical mechanical polishing process; thereafter, the polysilicon layer 107, the silicon dioxide layer 106 and the silicon dioxide layer 105 are patterned by a photolithography process in combination with etching, the etching stopping at the surface of the semiconductor substrate 100 (i.e., stopping at the surface of each well), the remaining polysilicon layers 107 in the logic region I are separated from each other and serve as polysilicon gates in the high voltage transistor region HV and the low voltage transistor region LV, respectively, and the remaining polysilicon layers 107 in the capacitor region II are separated from each other and serve as polysilicon plates stacked on the high k dielectric layer 104, i.e., as upper plates of decoupling capacitors.
Referring to fig. 5 and 6, in step S5, first, a first sidewall 108a is formed on the sidewalls of each polysilicon gate and polysilicon plate by a sidewall process (including dielectric layer deposition and etching), and the material of the first sidewall 108a may be silicon dioxide. Then, with the first sidewall 108a and each of the polysilicon gate and the polysilicon plate as masks, a Lightly Doped Drain (LDD) region ion implantation is performed on the semiconductor substrate 100 to form a lightly doped (LDD) region 109 in the well around each of the polysilicon gate and the polysilicon plate, which may be implemented by a multi-step process of photolithography masking before LDD implantation, so that the depths and the concentrations of the lightly doped (LDD) regions 109 formed in the high voltage transistor region HV and the low voltage transistor region LV in the logic region I and in the capacitor region II are not identical. Then, a second side wall 108b and a third side wall 108c are sequentially formed on the outer side of the first side wall 108a by adopting a side wall process, wherein the material of the second side wall 108b can be silicon nitride, the material of the third side wall 108c can be silicon oxide, and the third side wall 108c, the second side wall 108b and the first side wall 108a are jointly used as the grid side wall 108. Next, a first dielectric layer 110 is deposited, and the first dielectric layer 110 is subjected to photolithography and etching to define the regions of the logic region I and the capacitor region II where the source and the drain are to be formed, in this embodiment, the first dielectric layer 110 in the low voltage transistor region LV and the capacitor region II is removed entirely, the first dielectric layer 110 in the high voltage transistor region HV has an opening 110a formed outside the third sidewall 108c, and the opening 110a is used to define the forming regions of the source and the drain of the high voltage transistor. Then, the first dielectric layer 110, the third sidewall 108c, the second sidewall 108b, the first sidewall 108a, and each polysilicon gate and polysilicon plate are used as masks, and source-drain ion implantation is performed on the semiconductor substrate 100 to form source-drain regions 111 in wells around each polysilicon gate and polysilicon plate, wherein the source-drain region 111 located at one side of the polysilicon gate is used as a source S, and the source-drain region 111 located at the other side of the polysilicon gate is used as a drain D. Thus, a high voltage transistor (i.e., a high voltage logic transistor) is formed in the high voltage transistor region HV of the logic region I, a low voltage transistor (i.e., a low voltage logic transistor) is formed in the low voltage transistor region LV, and corresponding decoupling capacitors, each of which is a MOS capacitor, are formed in the capacitor region II, and include a semiconductor substrate 100, a silicon dioxide interface layer 103, a high-k dielectric layer 104, and a polysilicon layer 107, which are stacked in this order.
Referring to fig. 7 and 8, in step S6, a source S, a drain D, a polysilicon gate and a polysilicon plate for the external connection region may be defined by depositing, photo-etching and etching the second dielectric layer 112; then forming metal silicide 113 on the exposed electrode S, drain electrode D, polysilicon gate and polysilicon plate of the second dielectric layer 112 by metal silicidation process; thereafter, a power line VDD, a ground line VSS, and a Metal interconnect structure having at least one conductive plug (not shown) and at least one Metal interconnect line (not shown, refer to Metal of fig. 10) are formed on the semiconductor substrate 100 through a Metal wiring process (including interlayer dielectric layer deposition, contact hole etching, contact hole filling, metal interconnect process, etc.), and a portion of the Metal interconnect structure electrically connects the polysilicon plate of at least one logic transistor and at least one decoupling capacitor to the power line VDD, and another portion of the Metal interconnect structure electrically connects at least one logic transistor and the semiconductor substrate 100 to the ground line VSS. In this embodiment, a portion of the metal interconnection structure electrically connects the drain D of a high voltage transistor and the polysilicon plate (i.e., the polysilicon layer 107) of a decoupling capacitor to the power line VDD through corresponding metal silicide, and another portion of the metal interconnection structure electrically connects the source S of a low voltage transistor and the source S of a decoupling capacitor to the ground line VSS through corresponding metal silicide.
In other embodiments of the present invention, corresponding metal interconnection structures may be designed and fabricated as needed to connect a plurality of decoupling capacitors in series or in parallel, and a plurality of logic transistors may be designed to connect a plurality of logic transistors in series or in parallel.
In addition, in the above embodiment, the logic region I has the high-voltage transistor region and the low-voltage transistor region, and each transistor region only shows the formation region of one transistor, but the technical solution of the present invention is not limited thereto, and each transistor region may have the formation regions of a plurality of transistors, and the transistors formed in each transistor region may be of the same type, or different types, for example, may be NMOS transistors or PMOS transistors, or both NMOS transistors and PMOS transistors, may have LDMOS transistors, fin transistors, or may have a common planar MOS transistor, or the like. The high voltage transistor region and the low voltage transistor region in the logic region I may be replaced with other first and second regions having different operating voltages, for example, the standard voltage transistor region and the low voltage transistor region, and the logic region I may further have three or more transistor regions having different operating voltages.
Referring to fig. 9 and 10, in other embodiments of the present invention, the semiconductor substrate 100 provided in step S1 may have other device regions, such as a memory region, a resistive region, and the like. When the semiconductor substrate 100 provided in step S1 has a memory area III, the method of manufacturing an integrated circuit chip of the present invention further includes forming at least one memory cell in the memory area III; and in the Metal wiring process in step S6, corresponding Metal interconnection structures (including at least one layer of conductive plugs and at least one layer of Metal interconnection lines) are formed to electrically connect the corresponding memory cells with the logic transistors.
The storage unit formed by the storage areas can be an SRAM storage unit, a DRAM storage unit, a FLASH storage unit and the like. As an example, when the storage area forms an electrical structure of polysilicon material such as a control gate or a word line of the memory cell, the polysilicon gate in the logic area I and the polysilicon plate of the decoupling capacitor in the capacitor area II may be formed together. As another example, a memory cell is formed in the memory region, and then a logic transistor and a decoupling capacitor are fabricated in the logic region along with the capacitor region.
Referring to fig. 9 and 10, as an example, the memory cell formed by the memory region is an SRAM memory cell including a memory control transistor for storing data and a memory selection transistor for selecting stored data. The gate dielectric layer 114 of the memory control transistor is a silicon oxide-silicon nitride-silicon oxide stacked film layer, and the gate oxide layer of the memory selection transistor and the gate oxide layer of the low voltage transistor are the same film. In this case, the method for manufacturing an integrated circuit chip still includes the steps S1 to S6 described above, with the difference that: in step S1, a low-voltage well LV-NW is formed in the storage area III while a low-voltage well LV-NW of the low-voltage transistor area LV is formed, and when a shallow trench isolation structure STI is formed, a corresponding STI is also formed in the storage area III to define a storage control transistor area III-1 and a storage selection transistor III-2; in step S2, the high-k dielectric layer 104 on the storage area III is removed simultaneously with the removal of the high-k dielectric layer 104 of the logic area I; in step S3, before or after forming the silicon oxide gate oxide layer required for each logic transistor on the logic region I, forming a patterned silicon oxide-silicon nitride-silicon oxide stack film layer on the semiconductor substrate 100 of the memory control transistor region III-1 by film deposition, photolithography and etching to serve as the gate dielectric layer (i.e., memory medium) 114 required in the memory control transistor region III-1, the silicon oxide layer 106 further covering the memory region III when forming the silicon oxide layer 106; in step S4, the deposited polysilicon layer 107 also overlies the memory region III, the polysilicon layer 107 and the silicon dioxide layer 106 are patterned to form at least one polysilicon gate in the logic region I and at least one polysilicon plate stacked on the capacitor dielectric in the capacitor region II, and also to form a polysilicon control gate in the memory region III on the gate dielectric layer of the memory control transistor region III-1 and a polysilicon gate in the silicon dioxide layer 106 (i.e., gate oxide layer) of the memory select transistor region III-2; in step S5, source-drain ion implantation is also performed on the storage region III to form a storage selection transistor and a storage control transistor; in step S6, a portion of a corresponding Metal interconnection structure (including at least one layer of conductive plugs and at least one layer of Metal interconnection lines) is formed, so that the memory select transistor and the memory control transistor can be electrically connected, and the memory select transistor is electrically connected to the corresponding logic transistor, for example, the drain D of the memory control transistor and the source S of the memory select transistor are electrically connected, and the drain D of the memory select transistor and the source S of the high voltage transistor are electrically connected.
It should be noted that, when the semiconductor substrate has the storage area III, the logic area I and the capacitor area II, the process in the logic area I is a standard CMOS process well known to those skilled in the art, and the process in the storage area III may be a manufacturing process compatible with the standard CMOS process in the logic area I well known to those skilled in the art, or may be a manufacturing process of other memories well known to those skilled in the art. Compared with the prior art, the technical scheme of the invention only uses one additional mask for patterning the high-k dielectric layer, namely, a process of depositing, photoetching and etching the high-k dielectric layer is relatively added, and the rest processes can be completed by the existing processes known to the person skilled in the art.
In addition, in the method for manufacturing an integrated circuit chip of the present invention, there may be four types of decoupling capacitors formed: (1) A depletion type NMOS capacitor having an N-doped polysilicon plate, an N-doped source, an N-doped drain, and a P-doped channel, as shown in fig. 11; (2) An accumulation-mode NMOS capacitor having an N-doped polysilicon plate, an N-doped source, an N-doped drain, and an N-doped channel, as shown in fig. 12; (3) A depletion type PMOS capacitor having P-doped polysilicon plates, P-doped source, P-doped drain, and N-doped channel as shown in fig. 13; (4) An accumulation mode PMOS capacitor with P-doped polysilicon plate, P-doped source, P-doped drain and P-doped channel is shown in fig. 14. Among them, since depletion type PMOS capacitors are relatively easy to generate severe polysilicon depletion, increasing the effective dielectric thickness and resulting in lower capacitance values, it is preferable to use any one of depletion type NMOS capacitors, accumulation type NMOS capacitors and accumulation type PMOS capacitors in high performance integrated circuit chips.
The decoupling capacitor formed in the method for manufacturing the integrated circuit chip has smaller leakage current and larger capacitance density when the capacitor dielectric layer (namely the silicon dioxide gate oxide layer) of the MOS capacitor in the prior art has the same thickness, and can be used as the decoupling capacitor required by the integrated circuit chip with the technical node of 28nm or below.
Based on the same inventive concept, please refer to fig. 8, an embodiment of the present invention further provides an integrated circuit chip with decoupling capacitor, which is formed by the method for manufacturing an integrated circuit chip with decoupling capacitor according to the present invention. The integrated circuit chip includes: the semiconductor device comprises a semiconductor substrate 100 having a logic region I and a capacitance region II, at least one logic transistor formed in the logic region I of the semiconductor substrate 100, at least one decoupling capacitor formed in the capacitance region II of the semiconductor substrate 100, a power line VDD, a ground line VSS and a metal interconnection structure (not shown) comprising at least one layer of conductive plugs and at least one layer of metal interconnection lines, wherein one part of the metal interconnection structure electrically connects the polysilicon plates of at least one logic transistor and at least one decoupling capacitor to the power line VDD and the other part electrically connects at least one logic transistor and the semiconductor substrate 100 to the ground line VSS.
Optionally, referring to fig. 10, the semiconductor substrate 100 further has a memory area III, in which a memory having at least one memory cell is formed in the memory area III of the semiconductor substrate 100, and the further portion of the metal interconnection structure electrically connects the memory with at least one of the logic transistors.
It should be noted that, specific device structures and film materials in the logic area I, the capacitor area II and the storage area III of the integrated circuit chip are not described herein, and reference may be made to the above description of the manufacturing method of the integrated circuit chip.
In summary, the integrated circuit chip with decoupling capacitor and the method for manufacturing the same of the present invention form the decoupling capacitor based on the polysilicon gate and the high-k dielectric layer, so that the decoupling capacitor can be integrated in a standard CMOS process, and only one additional mask is added compared with the original standard CMOS process, so that the process is simple and the manufacturing cost is low. In addition, through reasonable design of the material selection and thickness of the high-k dielectric layer, the capacitance density and leakage performance of the formed decoupling capacitor are similar to those of the MIM capacitor, and the polysilicon depletion of the decoupling capacitor is controllable, so that the higher performance requirement of devices of 28nm and below technology nodes is met.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way, and any alterations and modifications made by those skilled in the art in light of the above disclosure shall fall within the scope of the present invention.
Claims (9)
1. A method of manufacturing an integrated circuit chip having decoupling capacitors, comprising:
providing a semiconductor substrate with a logic region and a capacitor region, wherein the logic region is provided with a first region and a second region with working voltage lower than that of the first region, a high-voltage well is formed in the semiconductor substrate of the first region, low-voltage wells are formed in the semiconductor substrate of the second region and the capacitor region, the low-voltage wells of the second region and the capacitor region are formed by adopting the same well ion implantation process, and the implantation depth is smaller than that of the high-voltage well;
depositing a high-k dielectric layer with a dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
patterning the high-k dielectric layer through photoetching and etching processes to remove the high-k dielectric layer of the logic region and form a capacitance medium of at least one decoupling capacitor on a low-voltage well of the capacitance region;
forming silicon dioxide gate oxide layers on the semiconductor substrates of the first region and the second region respectively, wherein the thickness of the silicon dioxide gate oxide layer on the second region is lower than that of the silicon dioxide gate oxide layer on the first region;
depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the first region and the second region respectively, and forming a polysilicon plate stacked on the capacitor dielectric in the capacitor region;
performing source-drain ion implantation on the semiconductor substrate by taking the polysilicon gate and the polysilicon polar plate as masks to form corresponding logic transistors in the logic region and corresponding decoupling capacitors in the capacitor region, wherein each decoupling capacitor is a MOS capacitor with the corresponding polysilicon polar plate;
and forming a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure is used for electrically connecting at least one logic transistor and at least one polysilicon pole plate to the power line, and the other part is used for electrically connecting at least one logic transistor and the semiconductor substrate to the ground line.
2. The method of manufacturing of claim 1, wherein shallow trench isolation structures are formed in the semiconductor substrate to achieve electrical isolation between each of the logic transistors and each of the decoupling capacitors.
3. The method of manufacturing of claim 1, wherein a silicon dioxide interfacial layer is formed on a surface of the semiconductor substrate prior to depositing a high-k dielectric layer having a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate.
4. The method of manufacturing of claim 3, wherein the silicon dioxide interfacial layer of the logic region is also removed and the corresponding silicon dioxide interfacial layer of the capacitor region is retained while the high-k dielectric layer of the logic region is removed and the corresponding high-k dielectric layer of the capacitor region is retained, such that the finally formed capacitance medium of the decoupling capacitor comprises a silicon dioxide interfacial layer and a high-k dielectric layer stacked in sequence.
5. The method of manufacturing of claim 1, wherein the high-k dielectric layer is a structure formed of a single layer of high-k dielectric material or a composite structure of stacked layers of high-k dielectric materials, the high-k dielectric material including at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide, and aluminum oxide.
6. The method of manufacturing of claim 1, wherein a silicon dioxide gate oxide layer is formed on the semiconductor substrate of the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process.
7. The method of manufacturing according to claim 1, wherein the semiconductor substrate provided further has a memory region, the method further comprising forming at least one memory cell in the memory region; and in the metal wiring process, a further portion of the metal interconnect structure electrically connects the memory cell with the corresponding logic transistor.
8. An integrated circuit chip with decoupling capacitance, characterized in that it is formed by the method for manufacturing an integrated circuit chip with decoupling capacitance according to any one of claims 1 to 7, said integrated circuit chip comprising: the semiconductor device comprises a semiconductor substrate with a logic region and a capacitance region, at least one logic transistor formed in the logic region of the semiconductor substrate, at least one decoupling capacitor formed in the capacitance region of the semiconductor substrate, a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line, wherein one part of the metal interconnection structure is used for electrically connecting at least one logic transistor and the polycrystalline silicon polar plate of the decoupling capacitor to the power line, and the other part is used for electrically connecting at least one logic transistor and the semiconductor substrate to the ground line.
9. The integrated circuit chip of claim 8, wherein the semiconductor substrate further has a memory region in which a memory having at least one memory cell is formed, the further portion of the metal interconnect structure electrically connecting the memory cell with at least one of the logic transistors.
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| CN1679124A (en) * | 2002-08-29 | 2005-10-05 | 富士通株式会社 | Thin film capacitor and method for manufacturing same |
| US7465639B1 (en) * | 2005-05-20 | 2008-12-16 | Advanced Micro Devices, Inc. | Method for fabricating an SOI device |
| CN101427373A (en) * | 2006-04-20 | 2009-05-06 | 先进微装置公司 | Method for fabricating a semiconductor component including a high capacitance per unit area capacitor |
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| DE10240423B4 (en) * | 2002-09-02 | 2007-02-22 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor element having a field effect transistor and a passive capacitor with reduced leakage current and an improved capacity per unit area and method for its production |
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| CN1679124A (en) * | 2002-08-29 | 2005-10-05 | 富士通株式会社 | Thin film capacitor and method for manufacturing same |
| US7465639B1 (en) * | 2005-05-20 | 2008-12-16 | Advanced Micro Devices, Inc. | Method for fabricating an SOI device |
| CN101427373A (en) * | 2006-04-20 | 2009-05-06 | 先进微装置公司 | Method for fabricating a semiconductor component including a high capacitance per unit area capacitor |
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