CN113078159B - Integrated circuit chip with decoupling capacitor and method for manufacturing the same - Google Patents

Abstract

The invention provides an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof, wherein the decoupling capacitor is formed based on a polysilicon gate and a high-k dielectric layer, the decoupling capacitor can be integrated in a standard CMOS process, and compared with the original standard CMOS process, only one additional mask is added, so that the process is simple, and the manufacturing cost is low. In addition, the reasonable design can be carried out on the material selection and the thickness of the high-k dielectric layer, so that the capacitance density and the leakage performance of the formed decoupling capacitor are similar to those of the MIM capacitor, and the polysilicon depletion of the decoupling capacitor is controllable, so that the higher performance requirement of devices of 28nm and below technical nodes is met.

Description

Integrated circuit chip with decoupling capacitor and manufacturing method thereof

technical field

The invention relates to the technical field of integrated circuits, in particular to an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof.

Background technique

In a CMOS IC (Integrated Circuit) chip with logic circuits and memory, since circuit components such as power bus resistance and current switches will cause noise, it is usually necessary to connect a large decoupling capacitor to connect to the power supply, and connect a corresponding part of the circuit It is decoupled from another part of the circuit, and the noise is shunted through the decoupling capacitor, thereby offsetting the power supply voltage drop caused by the noise, thereby preventing the noise from affecting the reliability of the circuit or causing circuit failure.

The decoupling capacitors currently required for CMOS IC chips for logic and memory applications are usually built based on MOS capacitors, and the MOS capacitors specifically utilize the thinnest silicon dioxide gate oxide layer on the chip (that is, using the same The gate oxide layer of the low-voltage MOS transistor is formed by forming a silicon dioxide film), which has the characteristics of high capacitance density, low leakage current and low cost compared with metal-insulator-metal decoupling capacitors (MIM). However, when the integrated circuit chip technology enters the technology node of 28nm or below, the gate oxide layer of silicon dioxide is too thin and is easy to be tunneled, which leads to the occurrence of leakage current, thus limiting the use of MOS capacitors as decoupling capacitors.

Contents of the invention

The object of the present invention is to provide a kind of integrated circuit chip with decoupling capacitor and its manufacturing method, not only can the MOS capacitor used as decoupling capacitor be compatible with CMOS process, but also can avoid existing MOS capacitor at the same time because of leakage current problem But it cannot be used for the problem of decoupling capacitors of integrated circuit chips with technology nodes of 28nm or below.

To achieve the above object, the present invention provides a method for manufacturing an integrated circuit chip with a decoupling capacitor, which comprises the following steps:

providing a semiconductor substrate having a logic region and a capacitor region, and depositing a high-k dielectric layer with a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate;

patterning the high-k dielectric layer to remove the high-k dielectric layer in the logic region, and form at least one capacitive medium of a decoupling capacitor in the capacitive region;

forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic region;

Depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region pole, and form a polysilicon plate stacked on the capacitor medium in the capacitor region;

Using the polysilicon gate and the polysilicon plate as a mask, perform source-drain ion implantation on the semiconductor substrate to form corresponding logic transistors in the logic region, and form corresponding logic transistors in the capacitor region. decoupling capacitors, each of which is a MOS capacitor with a corresponding polysilicon plate;

Through a metal wiring process, a power line, a ground line, and a metal interconnection structure including conductive plugs and metal interconnection lines are formed on the semiconductor substrate, and a part of the metal interconnection structure connects at least one logic transistor The at least one polysilicon plate is electrically connected to the power line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line.

Optionally, a shallow trench isolation structure is formed in the semiconductor substrate to realize electrical isolation between each of the logic transistors and each of the decoupling capacitors.

Optionally, before depositing a high-k dielectric layer with a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate, a silicon dioxide interface layer is first formed on the surface of the semiconductor substrate.

Optionally, when removing the high-k dielectric layer in the logic region and retaining the corresponding high-k dielectric layer in the capacitance region, also remove the silicon dioxide interface layer in the logic region and retain the high-k dielectric layer in the capacitance region Corresponding silicon dioxide interface layer, so that the capacitive medium of the decoupling capacitor finally formed includes a silicon dioxide interface layer and a high-k dielectric layer stacked in sequence.

Optionally, the high-k dielectric layer is a structure formed by a single layer of high-k dielectric material or a composite structure formed by stacking multiple layers of high-k dielectric material, and the high-k dielectric material includes silicon nitride, oxygen nitrogen At least one of silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide and aluminum oxide.

Optionally, the logic region has at least a first region and a second region with different operating voltages; the step of forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic region includes: Silicon dioxide gate oxide layers with different thicknesses are formed on the semiconductor substrate in the second region.

Optionally, a silicon dioxide gate oxide layer is formed on the semiconductor substrate in the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process.

Optionally, the provided semiconductor substrate further has a storage area, and the manufacturing method further includes forming at least one storage unit in the storage area; and in the metal wiring process, the storage unit and the corresponding The logic transistor is electrically connected.

Based on the same inventive concept, the present invention also provides an integrated circuit chip with a decoupling capacitor, which is formed by the method for manufacturing an integrated circuit chip with a decoupling capacitor according to the present invention, and the integrated circuit chip includes: a logic area and the semiconductor substrate of the capacitor area, at least one logic transistor formed in the logic area of the semiconductor substrate, at least one decoupling capacitor formed in the capacitor area of the semiconductor substrate, and power lines, ground lines, and conductive plugs a metal interconnection structure plugged with a metal interconnection line, wherein a part of the metal interconnection structure electrically connects at least one logic transistor and the polysilicon plate of at least one decoupling capacitor to the power supply line, Another part electrically connects at least one of the logic transistors and the semiconductor substrate to the ground.

Optionally, the semiconductor substrate further has a storage area, a memory with at least one storage unit is formed in the storage area of the semiconductor substrate, and another part of the metal interconnection structure connects the storage unit with at least one One of the logic transistors is electrically connected.

Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

1. In the present invention, at least the high-k dielectric layer is used as the capacitance medium of the MOS capacitor (ie, the decoupling capacitor), and when the MOS capacitor of the present invention (ie, the decoupling capacitor) has the same capacitance dielectric layer as the MOS capacitor in the prior art When the thickness is high, the characteristics of the high-k dielectric material itself different from silicon dioxide can be used to reduce the leakage current and increase the capacitance density. Therefore, the MOS capacitor of the present invention can be used as the decoupling of the integrated circuit chip of the technology node of 28nm or below capacitance.

2, in the present invention, owing to needing to adopt high-k dielectric layer to be used as the capacitor medium of MOS capacitor, therefore compare with the scheme of directly using silicon dioxide gate oxide layer as the capacitor medium of MOS capacitor in the existing CMOS process, only There is an additional accessory mask for patterning the high-k dielectric layer, so it is compatible with the original CMOS process, the process is simple, and the cost is low.

Description of drawings

FIG. 1 is a flowchart of a method for manufacturing an integrated circuit chip with decoupling capacitors according to an embodiment of the present invention.

FIG. 2 to FIG. 8 are schematic cross-sectional structural diagrams of devices in a method of manufacturing an integrated circuit chip with decoupling capacitors according to an embodiment of the present invention.

9 to 10 are schematic diagrams of cross-sectional structures of devices in a method for manufacturing an integrated circuit chip with decoupling capacitors according to another embodiment of the present invention.

11 to 14 are examples of cross-sectional structures of decoupling capacitors formed in an embodiment of the present invention.

Detailed ways

The technical solutions proposed by the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

Please refer to FIG. 1, an embodiment of the present invention provides a method for manufacturing an integrated circuit chip with a decoupling capacitor, which includes the following steps:

S1, providing a semiconductor substrate having a logic region and a capacitor region, and depositing a high-k dielectric layer with a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate;

S2, patterning the high-k dielectric layer by photolithography and etching process, so as to remove the high-k dielectric layer in the logic area, and form at least one capacitive medium of decoupling capacitor in the capacitive area;

S3, forming a silicon dioxide gate oxide layer on the semiconductor substrate in the logic region;

S4, depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one a polysilicon gate, and forming a polysilicon plate of at least one decoupling capacitor stacked on the capacitor medium in the capacitor region;

S5, using the polysilicon gate and the polysilicon plate as a mask, perform source-drain ion implantation on the semiconductor substrate, so as to form corresponding logic transistors in the logic region, and forming corresponding decoupling capacitors, each of which is a MOS capacitor having a corresponding polysilicon plate;

S6, forming a power line, a ground line, and a metal interconnection structure including conductive plugs and metal interconnection lines on the semiconductor substrate through a metal wiring process, and a part of the metal interconnection structure connects at least one of the The logic transistor and at least one polysilicon plate are electrically connected to the power line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line.

Please refer to Fig. 2, in step S1, at first, provide semiconductor substrate 100, semiconductor substrate 100 can be any suitable substrate material for making PMOS transistor and NMOS transistor known to those skilled in the art, for example silicon, germanium , silicon-on-insulator, silicon-germanium-on-insulator, etc., and form a silicon dioxide interfacial layer 103 on the surface of the semiconductor substrate 100 through a thermal oxidation process, the thickness of the silicon dioxide interfacial layer 103 can be e.g. for /> Then, well ion implantation can be performed on multiple regions of the semiconductor substrate 100 first, and then a shallow trench isolation structure (STI) 101 can be formed in the semiconductor substrate 100, or a shallow trench isolation structure can be formed in the semiconductor substrate 100 first. structure (STI) 101, and then perform well ion implantation on multiple regions of the semiconductor substrate 100 to define a logic region I, each transistor region in the logic region I, and a capacitor region II. In this embodiment, a high-voltage transistor region (HV, i.e. the first region) and a low-voltage transistor region (LV, i.e. the second region) with different operating voltages are defined in the logic region I, and the semiconductor substrate of the high-voltage transistor region (HV) A deep well 102a of the first conductivity type is formed in 100, a high voltage well 102b of the second conductivity type is formed in the deep well 102a of the first conductivity type, and a low voltage well 102c is formed in the semiconductor substrate 100 of the low voltage transistor region (LV). A low-voltage well 102d is formed in the semiconductor substrate 100 in the capacitor region II, wherein the low-voltage well 102c and the low-voltage well 102d can be formed by the same well ion implantation process, and the implantation depth is smaller than the high-voltage well 102b. As an example, when it is necessary to fabricate high-voltage NMOS transistors in the high-voltage transistor area (HV), low-voltage NMOS transistors in the low-voltage transistor area (LV), and N-type MOS capacitors (ie, decoupling capacitors) in the capacitance area II, The deep well 102a of the first conductivity type is a deep N well (DNW), the high voltage well 102b of the second conductivity type is a high voltage P well (HV-PW), and the low voltage well 102c is a low voltage N well (LV-NW). 102d may be a low-voltage N-well (LV-NW) or a low-voltage P-well (LV-PW). The shallow trench isolation structure (STI) 101 can realize electrical isolation between each of the logic transistors and each of the decoupling capacitors that are finally formed. After that, deposit a high-k dielectric layer 104 with a dielectric constant k higher than silicon dioxide on the surface of the shallow trench isolation structure (STI) 101 and the silicon dioxide interface layer 103, for example, the dielectric constant k is greater than 3.9 or not lower than 7. Wherein, the high-k dielectric layer 104 may be a structure formed by a single layer of high-k dielectric material, or may be a composite structure formed by stacking multiple layers of high-k dielectric materials, and the material selection of the high-k dielectric material needs to be based on The leakage current performance requirements and capacitance density requirements of the required MOS capacitors are determined, which can include silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxide At least one of aluminum (HfAlO), hafnium tantalum oxide (HfTaO), zirconium oxide (ZrO), and aluminum oxide (Al ₂ O ₃ ). As an example, the high-k dielectric layer 104 is a composite structure in which Al ₂ O 3 layers, HfO layers, and Al ₂ O ₃ layers are stacked in sequence, or a composite structure in which Al ₂ O 3 layers, ZrO layers, and Al ₂ O ₃ layers are stacked in sequence.

It should be noted that, in the above example, the silicon dioxide interface layer 103 is formed on the semiconductor substrate 100 before well ion implantation and STI formation, the technical solution of the present invention is not limited thereto, and in other aspects of the present invention In one embodiment, before the well ion implantation and STI formation, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 by a thermal oxidation process, and the pad oxide layer is removed after the well ion implantation and STI formation, And the silicon dioxide interfacial layer 103 is formed on the surface of the semiconductor substrate 100 and the STI 101 through a thermal oxidation process again, so as to avoid the effect of the trap ion implantation process on the subsequent performance of the silicon dioxide interfacial layer 103 used as a capacitor medium. In another embodiment of the present invention, before the well ion implantation and STI formation, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 through a thermal oxidation process, and after the well ion implantation and STI formation The pad oxide layer is removed, and the formation of the silicon dioxide interface layer 103 is omitted, and the high-k dielectric layer 104 is directly deposited on the surface of the semiconductor substrate 100 and the STI 101 .

Please refer to FIG. 2, in step S2, first, through a series of photolithography processes such as photoresist coating, exposure, and development, a patterned photoresist layer is formed to define the MOS capacitor ( That is, the region of the capacitor medium of the decoupling capacitor); then, using the patterned photoresist layer as a mask, the high-k dielectric layer 104 is etched by a dry etching process or a wet etching process to remove the high-k dielectric layer 104 in the logic region I, and pattern the corresponding high-k dielectric layer 104 in the capacitance region II, the etching stops on the surface of the semiconductor substrate 100 (that is, the low-voltage well 102d of the capacitance region II surface), thereby forming the capacitive medium of at least one decoupling capacitor in capacitive region II. In this embodiment, the capacitive medium of each decoupling capacitor includes a high-k dielectric layer 104 and the silicon dioxide interface layer 103 below it, and the lower plate of each decoupling capacitor is the semiconductor substrate 100 (that is, the capacitor region II Low pressure well 102d).

Referring to FIG. 4 , in step S3 , a silicon dioxide gate oxide layer is formed on the semiconductor substrate 100 in the logic region I by at least one of thermal oxidation process, atomic layer deposition process, and chemical vapor deposition process. In this embodiment, since the thickness of the gate oxide layer of silicon dioxide required by the low-voltage transistor and the high-voltage transistor is different, it is necessary to form the gate oxide layer of silicon dioxide required by the low-voltage transistor and the high-voltage transistor in multiple steps. As an example, firstly, a silicon dioxide layer 105 is formed on the surface of the semiconductor substrate 100 by thermal oxidation process, atomic layer deposition process or chemical vapor deposition process; The silicon dioxide layer 105 on the semiconductor substrate 100 surface of the transistor region LV and the capacitor region II, and the silicon dioxide layer 105 on the semiconductor substrate 100 surface of the high-voltage transistor region HV is reserved; then, through the thermal oxidation process, the atomic A layer deposition process or a chemical vapor deposition process forms a silicon dioxide layer 106 on the surface of the semiconductor substrate 100 and the silicon dioxide layer 105, and the thickness of the silicon dioxide layer 106 meets the thickness requirement of a gate oxide layer of a low-voltage transistor. Therefore, in the high-voltage transistor region HV, the oxide layer structure formed by stacking the silicon dioxide layer 105 and the silicon dioxide layer 106 is used as a thicker silicon dioxide gate oxide layer required by the high-voltage MOS transistor, and the low-voltage transistor region LV In this case, the silicon dioxide layer 106 is used as a thinner silicon dioxide gate oxide layer required for low voltage MOS transistors.

Please refer to Fig. 4 and Fig. 5, in step S4, first, by chemical vapor deposition process, deposit polysilicon layer 107 on silicon dioxide layer 106 and described high-k dielectric layer 104, and the polysilicon layer is polished by chemical mechanical polishing process 107 to planarize the top surface; afterward, the polysilicon layer 107, the silicon dioxide layer 106 and the silicon dioxide layer 105 are patterned by a process of photolithography combined with etching, and the etching stops on the surface of the semiconductor substrate 100 ( That is, stop at the surface of each well), the remaining polysilicon layer 107 in the logic region I is separated from each other, and is used as the polysilicon gate in the high-voltage transistor region HV and the polysilicon gate in the low-voltage transistor region LV, respectively. The remaining polysilicon layers 107 in the capacitor region II are separated from each other and serve as polysilicon plates stacked on the high-k dielectric layer 104 , that is, as upper plates of decoupling capacitors.

Please refer to FIG. 5 and FIG. 6, in step S5, first, through a sidewall process (including dielectric layer deposition and etching), a first sidewall 108a is formed on the sidewalls of each polysilicon gate and polysilicon plate, and the second The material of the side wall 108a may be silicon dioxide. Then, lightly doped drain region ion implantation (LDD) is performed on the semiconductor substrate 100 by using the first sidewall 108a and each polysilicon gate and polysilicon plate as a mask, so as to form a layer on each polysilicon gate and polysilicon plate A lightly doped (LDD) region 109 is formed in the surrounding wells. This step can be realized by adopting a multi-step photolithography mask first and then LDD implantation process, so that the high-voltage transistor region HV and the low-voltage transistor region LV and the capacitor in the logic region I The depths and concentrations of the lightly doped (LDD) regions 109 formed in the region II are not completely the same. Afterwards, the sidewall process is used to sequentially form the second sidewall 108b and the third sidewall 108c on the outer side of the first sidewall 108a, wherein the material of the second sidewall 108b can be silicon nitride, and the third sidewall 108c The material may be silicon oxide, and the third sidewall 108c, the second sidewall 108b, and the first sidewall 108a collectively serve as the gate spacer 108 . Next, deposit the first dielectric layer 110, and photolithographically and etch the first dielectric layer 110 to define the regions where the source and drain electrodes are to be formed in the logic region I and the capacitor region II. In this embodiment, the low-voltage transistor The first dielectric layer 110 in the region LV and the capacitance region II is completely removed, and the first dielectric layer 110 in the high-voltage transistor region HV has an opening 110a formed outside the third spacer 108c, and the opening 110a is used to define the source of the high-voltage transistor The region where the electrodes and drains are formed. Afterwards, using the first dielectric layer 110, the third sidewall 108c, the second sidewall 108b, the first sidewall 108a, and each polysilicon gate and polysilicon plate as a mask, the semiconductor substrate 100 is source-drained. implanted to form source and drain regions 111 in wells around each polysilicon gate and polysilicon plate, wherein the source and drain region 111 on one side of the polysilicon gate serves as the source S, and the source and drain region 111 on the other side serves as the drain d. Thus, high-voltage transistors (i.e., high-voltage logic transistors) are formed in the high-voltage transistor area HV of the logic area I, low-voltage transistors (i.e., low-voltage logic transistors) are formed in the low-voltage transistor area LV, and corresponding transistors are formed in the capacitance area II. Each of the decoupling capacitors is a MOS capacitor, which includes a semiconductor substrate 100 , a silicon dioxide interface layer 103 , a high-k dielectric layer 104 and a polysilicon layer 107 stacked in sequence.

Please refer to FIG. 7 and FIG. 8. In step S6, the source S, the drain D, the polysilicon gate and the polysilicon plate can be defined for external connection through deposition of the second dielectric layer 112, photolithography and etching. Then through the metal silicide process, a metal silicide 113 is formed on the pole S, drain D, polysilicon gate and polysilicon pole plate exposed by the second dielectric layer 112; after that, through the metal wiring process (including interlayer dielectric layer deposition, contact hole etching, contact hole filling, metal interconnection process, etc.), on the semiconductor substrate 100, a power line VDD, a ground line VSS, and at least one layer of conductive plugs (not marked in the figure) and A metal interconnection structure of at least one layer of metal interconnection lines (not shown, refer to Metal in FIG. 10 ), and a part of the metal interconnection structure connects at least one logic transistor and at least one decoupling capacitor The polysilicon plate is electrically connected to the power line VDD, and another part of the metal interconnection structure electrically connects at least one logic transistor and the semiconductor substrate 100 to the ground line VSS. In this embodiment, a part of the metal interconnection structure electrically connects the drain D of a high-voltage transistor and the polysilicon plate (ie, the polysilicon layer 107 ) of a decoupling capacitor to the power supply line VDD through a corresponding metal silicide, The other part of the metal interconnection structure electrically connects the source S of a low-voltage transistor and the source S of a decoupling capacitor to the ground line VSS through corresponding metal silicides.

In other embodiments of the present invention, it is possible to design and fabricate corresponding metal interconnection structures as required, so that multiple decoupling capacitors can be connected in series or in parallel, and multiple logic transistors can be designed in series or in parallel. The electrical connection relationship is not specifically limited.

In addition, in the above-mentioned embodiment, the logic region I has a high-voltage transistor region and a low-voltage transistor region, and each transistor region only shows the formation region of one transistor, but the technical solution of the present invention is not limited thereto, each There may be multiple transistor formation regions in the transistor region, and the transistors formed in each transistor region may be of the same type or of different types, for example, they may all be NMOS transistors or PMOS transistors, or they may have both NMOS transistors and PMOS transistors Transistors can include LDMOS transistors, fin transistors, or ordinary planar MOS transistors, etc. The high-voltage transistor area and the low-voltage transistor area in the logic area I can be replaced by other first areas and second areas with different operating voltages, such as the standard voltage transistor area and the low-voltage transistor area, and there can be three or even more in the logic area I. Multiple transistor regions with different operating voltages.

Please refer to FIG. 9 and FIG. 10 , in other embodiments of the present invention, the semiconductor substrate 100 provided in step S1 may have other device regions, such as storage regions, resistor regions and so on. When the semiconductor substrate 100 provided in step S1 has a storage area III, the method for manufacturing an integrated circuit chip of the present invention further includes forming at least one storage unit in the storage area III; and in the metal wiring process in step S6, A corresponding metal interconnection structure (including connecting at least one layer of conductive plugs and at least one layer of metal interconnection lines Metal) is formed to electrically connect the corresponding memory cells with the logic transistors.

Wherein, the storage units formed in the storage area may be SRAM storage units, DRAM storage units, FLASH storage units and the like. As an example, when the electrical structure of polysilicon material such as the control gate or word line of the memory cell is formed in the storage area, the polysilicon gate in the logic area I and the polysilicon plate of the decoupling capacitor in the capacitance area II can be formed together . As another example, memory cells are first formed in the storage area, and then logic transistors and decoupling capacitors are fabricated together in the logic area and capacitor area.

Please refer to FIG. 9 and FIG. 10 , as an example, the storage unit formed in the storage area is an SRAM storage unit, which includes a storage control transistor for storing data and a storage selection transistor for selecting and storing data. The gate dielectric layer 114 of the storage control transistor is a silicon oxide-silicon nitride-silicon oxide stacked film layer, and the gate oxide layer of the storage selection transistor and the gate oxide layer of the low-voltage transistor are the same thin film. In this case, the manufacturing method of the integrated circuit chip still includes the above-mentioned steps S1-S6, the difference is that in step S1, while forming the low-voltage well LV-NW of the low-voltage transistor region LV, a well LV-NW is also formed in the storage region III. The low-voltage well cell-NW, and when forming the shallow trench isolation structure STI, also form the corresponding STI in the storage area III, so as to define the storage control transistor area III-1 and the storage selection transistor III-2; in step S2 , while removing the high-k dielectric layer 104 in the logic region I, the high-k dielectric layer 104 on the storage region III is also removed; in step S3, silicon dioxide required by each logic transistor is formed on the logic region I Before or after the gate oxide layer, a patterned silicon oxide-silicon nitride-silicon oxide stacked film layer is formed on the semiconductor substrate 100 in the storage control transistor region III-1 by film deposition, photolithography and etching , as the gate dielectric layer (i.e. storage medium) 114 required in the storage control transistor region III-1, when the silicon dioxide layer 106 is formed, the silicon dioxide layer 106 also covers the storage region III; in step S4 , the deposited polysilicon layer 107 is also covered on the storage area III, and the polysilicon layer 107 and the silicon dioxide layer 106 are patterned to form at least one polysilicon gate in the logic area I, and in the capacitance area II While forming at least one polysilicon plate stacked on the capacitor medium, a polysilicon control gate located on the gate dielectric layer of the storage control transistor area III-1 is also formed in the storage area III, and a polysilicon control gate located in the storage selection transistor area III -2 polysilicon gates on the silicon dioxide layer 106 (i.e. gate oxide layer); in step S5, also carry out source-drain ion implantation to storage region III, to form storage selection transistors and storage control transistors; in step S6 , forming a part of the corresponding metal interconnection structure (including connecting at least one layer of conductive plugs and at least one layer of metal interconnection line Metal), capable of electrically connecting the storage selection transistor and the storage control transistor, and connecting the storage selection transistor and the storage selection transistor Correspondingly, the logic transistor is electrically connected, for example, the drain D of the storage control transistor is electrically connected with the source S of the storage selection transistor, and the drain D of the storage selection transistor is electrically connected with the source S of the high voltage transistor.

It should be noted that when the semiconductor substrate has a storage area III, a logic area I and a capacitance area II, in the technical solution of the present invention, the process in the logic area I is a standard CMOS process well known to those skilled in the art, and the storage area The process of III may be a manufacturing process that is compatible with the standard CMOS process in the logic region I known to those skilled in the art, or may be a manufacturing process of other memories known to those skilled in the art. Compared with the prior art, the technical solution of the present invention only uses an additional mask for patterning the high-k dielectric layer, that is, a relatively high-k dielectric layer deposition, photolithography and etching process is added, and the rest All the processes can be completed by existing processes well known to those skilled in the art.

In addition, it should be noted that in the manufacturing method of the integrated circuit chip of the present invention, there are four types of decoupling capacitors formed: (1) having N-type doped polysilicon plates, N-type doped source electrodes, A depletion NMOS capacitor with N-type doped drain and P-type doped channel, as shown in Figure 11; (2) has an N-type doped polysilicon plate, an N-type doped source, and an N-type doped drain Pole and N-type doped channel accumulation NMOS capacitance, as shown in Figure 12; (3) with P-type doped polysilicon plate, P-type doped source, P-type doped drain and N-type doped The depletion-type PMOS capacitor of the channel, as shown in Figure 13; (4) the accumulation type with P-type doped polysilicon plate, P-type doped source, P-type doped drain and P-type doped channel PMOS capacitor, as shown in Figure 14. Among them, since depletion-type PMOS capacitors are more likely to produce severe polysilicon depletion, increase the effective dielectric thickness, and result in lower capacitance values, so in high-performance integrated circuit chips, it is preferable to use depletion-type NMOS capacitors and accumulation-type NMOS capacitors. Any of the three forms of accumulative PMOS capacitors.

When the decoupling capacitor formed in the manufacturing method of the integrated circuit chip of the present invention has the same thickness as the capacitor dielectric layer (i.e. silicon dioxide gate oxide layer) of the MOS capacitor in the prior art, the leakage current is small and the capacitance density is relatively high. It is large and can be used as a decoupling capacitor for integrated circuit chips with a technology node of 28nm or below.

Based on the same inventive concept, please refer to FIG. 8 , an embodiment of the present invention also provides an integrated circuit chip with decoupling capacitors, which is formed by the method for manufacturing an integrated circuit chip with decoupling capacitors described in the present invention. The integrated circuit chip includes: a semiconductor substrate 100 having a logic region I and a capacitor region II, at least one logic transistor formed in the logic region I of the semiconductor substrate 100, and a capacitor region II formed in the semiconductor substrate 100 At least one decoupling capacitor, power line VDD, ground line VSS, and a metal interconnection structure (not shown) including at least one layer of conductive plugs and at least one layer of metal interconnection lines, wherein the metal interconnection structure One part electrically connects at least one logic transistor and the polysilicon plate of at least one decoupling capacitor to the power supply line VDD, and the other part electrically connects at least one logic transistor and the semiconductor substrate 100 to the The ground wire VSS.

Optionally, please refer to FIG. 10 , the semiconductor substrate 100 further has a storage region III, a memory having at least one storage unit is formed in the storage region III of the semiconductor substrate 100, and the metal interconnection structure Another part electrically connects the memory with at least one of the logic transistors.

It should be noted that the specific device structures and film material selection in the logic area I, capacitance area II, and storage area III of the integrated circuit chip will not be described in detail here. description of.

To sum up, the integrated circuit chip with decoupling capacitor and its manufacturing method of the present invention form a decoupling capacitor based on a polysilicon gate and a high-k dielectric layer, and can integrate a decoupling capacitor in a standard CMOS process, and relatively The original standard CMOS process only adds an additional mask, the process is simple, and the manufacturing cost is low. In addition, through reasonable design of the material selection and thickness of the high-k dielectric layer, the capacitance density and leakage performance of the formed decoupling capacitor can be further similar to that of the MIM capacitor, and the polysilicon depletion of the decoupling capacitor can be controlled to meet the requirements of 28nm Higher performance requirements for devices of technology nodes and below.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures fall within the scope of the technical solutions of the present invention.

Claims (9)

1. A method for manufacturing an integrated circuit chip with a decoupling capacitor, characterized in that, comprising: providing a semiconductor substrate having a logic region and a capacitor region, the logic region having a first region and a second region having an operating voltage lower than that of the first region, a high voltage well is formed in the semiconductor substrate of the first region, Low-voltage wells are formed in the semiconductor substrate of the second region and the capacitance region, and the low-voltage wells of the second region and the capacitance region are formed by the same well ion implantation process, and the implantation depth is less than the High voltage well; Depositing a high-k dielectric layer with a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate; patterning the high-k dielectric layer by photolithography and etching processes to remove the high-k dielectric layer in the logic region, and form at least one capacitive dielectric of a decoupling capacitor on the low-voltage well of the capacitive region; A silicon dioxide gate oxide layer is respectively formed on the semiconductor substrate in the first region and the second region, and the thickness of the silicon dioxide gate oxide layer on the second region is lower than that on the first region silicon dioxide gate oxide layer; A polysilicon layer is deposited on the silicon dioxide gate oxide layer and the high-k dielectric layer, and the polysilicon layer and the silicon dioxide gate oxide layer are patterned, so that the first region and the second At least one polysilicon gate is respectively formed in the region, and a polysilicon plate stacked on the capacitor medium is formed in the capacitor region; Using the polysilicon gate and the polysilicon plate as a mask, perform source-drain ion implantation on the semiconductor substrate to form corresponding logic transistors in the logic region, and form corresponding logic transistors in the capacitor region. decoupling capacitors, each of which is a MOS capacitor with a corresponding polysilicon plate; Through a metal wiring process, a power line, a ground line, and a metal interconnection structure including conductive plugs and metal interconnection lines are formed on the semiconductor substrate, and a part of the metal interconnection structure connects at least one logic transistor The at least one polysilicon plate is electrically connected to the power line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line. 2. The manufacturing method according to claim 1, wherein a shallow trench isolation structure is formed in the semiconductor substrate to realize electrical isolation between each of the logic transistors and each of the decoupling capacitors . 3. The manufacturing method according to claim 1, characterized in that, before depositing a high-k dielectric layer with a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate, first depositing a layer on the surface of the semiconductor substrate A silicon dioxide interfacial layer is formed on it. 4. The manufacturing method according to claim 3, wherein when removing the high-k dielectric layer of the logic region and retaining the corresponding high-k dielectric layer in the capacitance region, the second layer of the logic region is also removed. The silicon interface layer is oxidized, and the corresponding silicon dioxide interface layer in the capacitance region is retained, so that the finally formed capacitance medium of the decoupling capacitor includes a silicon dioxide interface layer and a high-k dielectric layer stacked in sequence. 5. The manufacturing method according to claim 1, wherein the high-k dielectric layer is a structure formed by a single layer of high-k dielectric material or a composite structure formed by stacking multiple layers of high-k dielectric materials, and the The high-k dielectric material includes at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide, and aluminum oxide. 6. The manufacturing method according to claim 1, characterized in that silicon dioxide is formed on the semiconductor substrate in the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process gate oxide layer. 7. The manufacturing method according to claim 1, wherein the provided semiconductor substrate also has a storage area, and the manufacturing method further comprises forming at least one storage unit in the storage area; and in the metal In the wiring process, another part of the metal interconnection structure electrically connects the storage unit with the corresponding logic transistor. 8. An integrated circuit chip with a decoupling capacitor, characterized in that it is formed by the method for manufacturing an integrated circuit chip with a decoupling capacitor according to any one of claims 1-7, and the integrated circuit chip comprises: A semiconductor substrate having a logic region and a capacitance region, at least one logic transistor formed in the logic region of the semiconductor substrate, at least one decoupling capacitor formed in the capacitance region of the semiconductor substrate, and power lines, ground lines and a metal interconnection structure comprising a conductive plug and a metal interconnection line, wherein a part of the metal interconnection structure electrically connects at least one logic transistor and the polysilicon plate of at least one decoupling capacitor to the A power line, another part electrically connects at least one logic transistor and the semiconductor substrate to the ground line. 9. The integrated circuit chip according to claim 8, wherein the semiconductor substrate further has a storage area, and a memory with at least one storage unit is formed in the storage area of the semiconductor substrate, and the metal A further portion of the interconnect structure electrically connects the memory cell to at least one of the logic transistors.