CN113078159A - Integrated circuit chip with decoupling capacitor and method of manufacturing the same - Google Patents
Integrated circuit chip with decoupling capacitor and method of manufacturing the same Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 154
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 69
- 239000010410 layer Substances 0.000 claims description 151
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 130
- 239000004065 semiconductor Substances 0.000 claims description 88
- 239000000758 substrate Substances 0.000 claims description 85
- 235000012239 silicon dioxide Nutrition 0.000 claims description 62
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- 238000000231 atomic layer deposition Methods 0.000 claims description 5
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- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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Abstract
The invention provides an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof, the decoupling capacitor is formed based on a polysilicon grid and a high-k dielectric layer, the decoupling capacitor can be integrated in a standard CMOS process, only one additional mask is added compared with the original standard CMOS process, the process is simple, and the manufacturing cost is low. In addition, through reasonable design of material selection and thickness of the high-k dielectric layer, the capacitance density and leakage performance of the formed decoupling capacitor are further similar to those of an MIM capacitor, and polycrystalline silicon depletion of the decoupling capacitor is controllable, so that the higher performance requirement of devices with technical nodes of 28nm and below is met.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to an integrated circuit chip with a decoupling capacitor and a method for manufacturing the same.
Background
In a CMOS IC (integrated circuit) chip having a logic circuit and a memory, since circuit components such as a power bus resistor and a current switch cause noise, it is generally necessary to connect a large decoupling capacitor to a power supply, decouple a corresponding part of the circuit from another part of the circuit, and shunt the noise through the decoupling capacitor, thereby canceling a power supply voltage drop caused by the noise, and further avoiding the noise from affecting the reliability of the circuit or causing a circuit failure.
The decoupling capacitors currently required for CMOS IC chips for logic and memory applications are typically built on MOS capacitors formed using the thinnest silicon dioxide gate oxide on the chip (i.e., using a silicon dioxide film formed along with the gate oxide of the low voltage MOS transistors), which have the characteristics of high capacitance density, low leakage current, and low cost relative to metal-insulator-metal decoupling capacitors (MIMs). However, when the integrated circuit chip technology enters a technology node of 28nm or below, the silicon dioxide gate oxide layer is too thin and is easy to tunnel, and further, leakage current is caused, so that the use of the MOS capacitor as a decoupling capacitor is limited.
Disclosure of Invention
The invention aims to provide an integrated circuit chip with a decoupling capacitor and a manufacturing method thereof, which not only can make the MOS capacitor used as the decoupling capacitor compatible with a CMOS (complementary metal oxide semiconductor) process, but also can avoid the problem that the existing MOS capacitor cannot be used for the decoupling capacitor of the integrated circuit chip with the technical node of 28nm or below due to the problem of leakage current.
To achieve the above object, the present invention provides a method for manufacturing an integrated circuit chip having a decoupling capacitor, comprising the steps of:
providing a semiconductor substrate with a logic area and a capacitance area, and depositing a high-k dielectric layer with the dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
patterning the high-k dielectric layer to remove the high-k dielectric layer in the logic area and form a capacitor dielectric of at least one decoupling capacitor in the capacitor area;
forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic area;
depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region and a polysilicon plate stacked on the capacitor dielectric in the capacitor region;
performing source-drain ion implantation on the semiconductor substrate by taking the polysilicon gate and the polysilicon pole plate as masks to form a corresponding logic transistor in the logic region and form a corresponding decoupling capacitor in the capacitor region, wherein each decoupling capacitor is an MOS capacitor with the corresponding polysilicon pole plate;
and forming a power supply line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure electrically connects at least one logic transistor and at least one polysilicon plate to the power supply line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line.
Optionally, a shallow trench isolation structure is formed in the semiconductor substrate to achieve electrical isolation between each logic transistor and each decoupling capacitor.
Optionally, before depositing a high-k dielectric layer with a dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate, a silicon dioxide interface layer is formed on the surface of the semiconductor substrate.
Optionally, when the high-k dielectric layer in the logic region is removed and the corresponding high-k dielectric layer in the capacitor region is reserved, the silicon dioxide interface layer in the logic region is also removed and the corresponding silicon dioxide interface layer in the capacitor region is reserved, so that the finally formed capacitor dielectric of the decoupling capacitor comprises the silicon dioxide interface layer and the high-k dielectric layer which are sequentially stacked.
Optionally, the high-k dielectric layer is a structure formed by a single layer of high-k dielectric material or a composite structure formed by stacking multiple layers of high-k dielectric materials, and the high-k dielectric material includes at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide, and aluminum oxide.
Optionally, the logic region has at least a first region and a second region with different operating voltages; the step of forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic area comprises the following steps: and forming silicon dioxide gate oxide layers with different thicknesses on the semiconductor substrate of the first region and the semiconductor substrate of the second region.
Optionally, a silicon dioxide gate oxide layer is formed on the semiconductor substrate of the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process.
Optionally, the semiconductor substrate is further provided with a storage region, and the manufacturing method further comprises forming at least one storage unit in the storage region; and in the metal wiring process, the memory cells are electrically connected with the corresponding logic transistors.
Based on the same inventive concept, the present invention further provides an integrated circuit chip with a decoupling capacitor, which is formed by the manufacturing method of the integrated circuit chip with the decoupling capacitor of the present invention, and the integrated circuit chip comprises: the semiconductor device comprises a semiconductor substrate with a logic area and a capacitance area, at least one logic transistor formed in the logic area of the semiconductor substrate, at least one decoupling capacitor formed in the capacitance area of the semiconductor substrate, a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line, wherein one part of the metal interconnection structure electrically connects the polysilicon plates of the at least one logic transistor and the at least one decoupling capacitor to the power line, and the other part electrically connects the at least one logic transistor and the semiconductor substrate to the ground line.
Optionally, the semiconductor substrate further has a storage region, a memory having at least one memory cell is formed in the storage region of the semiconductor substrate, and a further portion of the metal interconnection structure electrically connects the memory cell with at least one of the logic transistors.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. in the invention, at least the high-k dielectric layer is used as a capacitor dielectric of the MOS capacitor (namely, the decoupling capacitor), and when the MOS capacitor (namely, the decoupling capacitor) has the same thickness as the capacitor dielectric layer of the MOS capacitor in the prior art, the characteristics of the high-k dielectric material which is different from silicon dioxide can be utilized, the leakage current is reduced, and the capacitor density is improved, so that the MOS capacitor can be used as the decoupling capacitor of an integrated circuit chip with a technical node of 28nm or below.
2. In the invention, because the high-k dielectric layer is used as the capacitor dielectric of the MOS capacitor, compared with the scheme that the silicon dioxide gate oxide layer is directly used as the capacitor dielectric of the MOS capacitor in the existing CMOS process, only one additional mask used for patterning the high-k dielectric layer is added, so that the method is compatible with the original CMOS process, simple in process and low in cost.
Drawings
Fig. 1 is a flow chart of a method of manufacturing an integrated circuit chip having decoupling capacitors in accordance with an embodiment of the present invention.
Fig. 2 to 8 are schematic cross-sectional views of devices in a method for manufacturing an integrated circuit chip with a decoupling capacitor according to an embodiment of the present invention.
Fig. 9 to 10 are schematic cross-sectional views of devices in a method for manufacturing an integrated circuit chip with a decoupling capacitor according to another embodiment of the present invention.
Fig. 11 to 14 are sectional structure examples of a decoupling capacitor formed in an embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, an embodiment of the invention provides a method for manufacturing an integrated circuit chip with a decoupling capacitor, which includes the following steps:
s1, providing a semiconductor substrate with a logic area and a capacitance area, and depositing a high-k dielectric layer with a dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
s2, patterning the high-k dielectric layer through photoetching and etching processes to remove the high-k dielectric layer in the logic area and form at least one capacitor dielectric of a decoupling capacitor in the capacitor area;
s3, forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic area;
s4, depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region and at least one polysilicon plate of a decoupling capacitor stacked on the capacitor dielectric in the capacitor region;
s5, using the polysilicon gate and the polysilicon pole plate as masks, performing source-drain ion implantation on the semiconductor substrate to form a corresponding logic transistor in the logic area and form a corresponding decoupling capacitor in the capacitor area, wherein each decoupling capacitor is an MOS capacitor with a corresponding polysilicon pole plate;
and S6, forming a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure electrically connects at least one logic transistor and at least one polysilicon plate to the power line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line.
Referring to fig. 2, in step S1, a semiconductor substrate 100 is first provided, the semiconductor substrate 100 may be any suitable substrate material known to those skilled in the art for fabricating PMOS transistors and NMOS transistors, such as silicon, germanium, silicon-on-insulator, silicon germanium-on-insulator, etc., and a silicon dioxide interface layer 103 is formed on the surface of the semiconductor substrate 100 by a thermal oxidation process, wherein the silicon dioxide interface layer 103 may have a thickness of
For example, is
Then, canThe method includes performing well ion implantation on a plurality of regions of the semiconductor substrate 100, and then fabricating a Shallow Trench Isolation (STI)101 in the semiconductor substrate 100, or performing well ion implantation on a plurality of regions of the semiconductor substrate 100 after fabricating the Shallow Trench Isolation (STI)101 in the semiconductor substrate 100, so as to define a logic region I, each transistor region in the logic region I, and a capacitor region II. In this embodiment, a high voltage transistor region (HV, i.e., a first region) and a low voltage transistor region (LV, i.e., a second region) with different operating voltages are defined in the logic region I, a first conductive type deep well 102a is formed in the semiconductor substrate 100 of the high voltage transistor region (HV), a second conductive type high voltage well 102b is formed in the first conductive type deep well 102a, a low voltage well 102c is formed in the semiconductor substrate 100 of the low voltage transistor region (LV), and a low voltage well 102d is formed in the semiconductor substrate 100 of the capacitor region II, wherein the low voltage well 102c and the low voltage well 102d can be formed by using the same well ion implantation process, and the implantation depth is smaller than that of the high voltage well 102 b. As an example, when it is required to fabricate a high voltage NMOS transistor in a high voltage transistor region (HV), a low voltage NMOS transistor in a low voltage transistor region (LV), and an N-type MOS capacitor (i.e., decoupling capacitor) in a capacitor region II, the first conductivity type deep well 102a is a deep N-well (DNW), the second conductivity type high voltage well 102b is a high voltage P-well (HV-PW), the low voltage well 102c is a low voltage N-well (LV-NW), and the low voltage well 102d may be a low voltage N-well (LV-NW) or a low voltage P-well (LV-PW). A shallow trench isolation Structure (STI)101 may achieve electrical isolation between each of the logic transistors and each of the decoupling capacitors that are finally formed. Then, a high-k dielectric layer 104 with a dielectric constant k higher than that of silicon dioxide, for example, the dielectric constant k is greater than 3.9 or not less than 7, is deposited on the surface of the shallow trench isolation Structure (STI)101 and the silicon dioxide interface layer 103. The high-k dielectric layer 104 may be a structure formed by a single layer of high-k dielectric material, or may be a composite structure formed by stacking multiple layers of high-k dielectric materials, and the material selection of the high-k dielectric material needs to be determined according to the leakage current performance requirement and the capacitance density requirement of the MOS capacitor, which may include silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), zirconium oxide (zr θ)(ZrO) and alumina (Al)2O3) At least one of (1). As an example, the high-k dielectric layer 104 is Al2O3 layer, HfO layer, Al2O3The layers being stacked in series in a composite structure or being Al2O3 layer, ZrO layer, Al2O3A composite structure with layers stacked in sequence.
It should be noted that, in the above example, the silicon dioxide interface layer 103 is formed on the semiconductor substrate 100 before the well ion implantation and the STI formation, the technical solution of the present invention is not limited thereto, and in another embodiment of the present invention, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 by a thermal oxidation process before the well ion implantation and the STI formation, the pad oxide layer is removed after the well ion implantation and the STI formation, and the silicon dioxide interface layer 103 may be formed on the surfaces of the semiconductor substrate 100 and the STI 101 by a thermal oxidation process again, so as to avoid the performance influence of the well ion implantation process on the silicon dioxide interface layer 103 which is subsequently used as the capacitance medium. In another embodiment of the present invention, a pad oxide layer (not shown) may be formed on the semiconductor substrate 100 by a thermal oxidation process before the well ion implantation and the STI formation, the pad oxide layer may be removed after the well ion implantation and the STI formation, and the high-k dielectric layer 104 may be deposited directly on the surface of the semiconductor substrate 100 and the STI 101 by omitting the formation of the silicon dioxide interface layer 103.
Referring to fig. 2, in step S2, a patterned photoresist layer is formed through a series of photolithography processes including photoresist coating, exposure, and development to define a region of a capacitor dielectric for forming a MOS capacitor (i.e., a decoupling capacitor) in the capacitor region II; then, the patterned photoresist layer is used as a mask, the high-k dielectric layer 104 is etched through a dry etching process or a wet etching process to remove the high-k dielectric layer 104 in the logic region I, and the corresponding high-k dielectric layer 104 in the capacitor region II is patterned, and the etching is stopped on the surface of the semiconductor substrate 100 (i.e., the surface of the low-voltage well 102d of the capacitor region II), so that a capacitor dielectric of at least one decoupling capacitor is formed in the capacitor region II. In this embodiment, the capacitor dielectric of each decoupling capacitor includes a high-k dielectric layer 104 and a silicon dioxide interface layer 103 thereunder, and the lower plate of each decoupling capacitor is the semiconductor substrate 100 (i.e., the low-voltage well 102d of the capacitor region II).
Referring to fig. 4, in step S3, a silicon dioxide gate oxide layer is formed on the semiconductor substrate 100 in the logic region I by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process. In this embodiment, since the thicknesses of the silicon dioxide gate oxide layers required for the low-voltage transistor and the high-voltage transistor are different, the silicon dioxide gate oxide layers required for the low-voltage transistor and the high-voltage transistor need to be formed in multiple steps. As an example, first, a silicon dioxide layer 105 is formed on a surface of the semiconductor substrate 100 through a thermal oxidation process, an atomic layer deposition process, or a chemical vapor deposition process; then, removing the silicon dioxide layer 105 on the surface of the semiconductor substrate 100 in the low-voltage transistor area LV and the capacitor area II by a method of photolithography and etching, and remaining the silicon dioxide layer 105 on the surface of the semiconductor substrate 100 in the high-voltage transistor area HV; next, a silicon dioxide layer 106 is formed on the surface of the semiconductor substrate 100 and the silicon dioxide layer 105 by a thermal oxidation process, an atomic layer deposition process or a chemical vapor deposition process, wherein the thickness of the silicon dioxide layer 106 meets the thickness requirement of a gate oxide layer of the low-voltage transistor. Thus, in the high-voltage transistor region HV, the oxide layer structure in which the silicon oxide layer 105 and the silicon oxide layer 106 are stacked functions as a thicker silicon oxide gate oxide layer required for the high-voltage MOS transistor, and in the low-voltage transistor region LV, the silicon oxide layer 106 functions as a thinner silicon oxide gate oxide layer required for the low-voltage MOS transistor.
Referring to fig. 4 and 5, in step S4, firstly, a polysilicon layer 107 is deposited on the silicon dioxide layer 106 and the high-k dielectric layer 104 by a chemical vapor deposition process, and the top surface of the polysilicon layer 107 is planarized by a chemical mechanical polishing process; then, the polysilicon layer 107, the silicon dioxide layer 106 and the silicon dioxide layer 105 are patterned by a process of photolithography and etching, the etching stops on the surface of the semiconductor substrate 100 (i.e. stops on the surface of each well), the polysilicon layers 107 remaining in the logic region I are separated from each other and respectively used as polysilicon gates in the high voltage transistor region HV and the low voltage transistor region LV, and the polysilicon layers 107 remaining in the capacitor region II are separated from each other and used as polysilicon plates stacked on the high-k dielectric layer 104, i.e. as upper plates of decoupling capacitors.
Referring to fig. 5 and 6, in step S5, first, a first sidewall 108a is formed on sidewalls of each of the polysilicon gate and the polysilicon plate by a sidewall process (including dielectric layer deposition and etching), where the first sidewall 108a may be made of silicon dioxide. Then, with the first sidewall 108a and each polysilicon gate and polysilicon plate as masks, Lightly Doped Drain (LDD) ion implantation is performed on the semiconductor substrate 100 to form a lightly doped (LDD) region 109 in the well around each polysilicon gate and polysilicon plate, which may be implemented by a multi-step process of performing mask lithography first and then LDD implantation, so that the depths and concentrations of the lightly doped (LDD) regions 109 formed in the high voltage transistor region HV and the low voltage transistor region LV in the logic region I and the capacitor region II are not completely the same. Then, a sidewall process is adopted to sequentially form a second sidewall 108b and a third sidewall 108c on the outer side of the first sidewall 108a, wherein the second sidewall 108b may be made of silicon nitride, the third sidewall 108c may be made of silicon oxide, and the third sidewall 108c, the second sidewall 108b and the first sidewall 108a are used as the gate sidewall 108 together. Next, a first dielectric layer 110 is deposited, and the first dielectric layer 110 is subjected to photolithography and etching to define regions to be formed with a source and a drain in the logic region I and the capacitor region II, in this embodiment, the first dielectric layer 110 in the low voltage transistor region LV and the capacitor region II is completely removed, the first dielectric layer 110 in the high voltage transistor region HV has an opening 110a formed outside the third sidewall 108c, and the opening 110a is used to define a formation region of the source and the drain of the high voltage transistor. Then, with the first dielectric layer 110, the third side wall 108c, the second side wall 108b, the first side wall 108a, and each polysilicon gate and polysilicon plate as masks, source-drain ion implantation is performed on the semiconductor substrate 100 to form a source-drain region 111 in the well around each polysilicon gate and polysilicon plate, where the source-drain region 111 on one side of the polysilicon gate is used as a source S, and the source-drain region 111 on the other side is used as a drain D. Thus, a high voltage transistor (i.e., a high voltage logic transistor) is formed in the high voltage transistor region HV of the logic region I, a low voltage transistor (i.e., a low voltage logic transistor) is formed in the low voltage transistor region LV, and corresponding decoupling capacitors are formed in the capacitor region II, each of which is a MOS capacitor including a semiconductor substrate 100, a silicon dioxide interface layer 103, a high-k dielectric layer 104, and a polysilicon layer 107, which are sequentially stacked.
Referring to fig. 7 and 8, in step S6, a region for externally connecting the source S, the drain D, the polysilicon gate and the polysilicon plate may be defined by depositing, photolithography and etching the second dielectric layer 112; then, forming a metal silicide 113 on the exposed electrode S, the exposed drain electrode D, the exposed polysilicon gate and the exposed polysilicon polar plate of the second dielectric layer 112 by a metal silicification process; then, a power line VDD, a ground line VSS, and a Metal interconnection structure having at least one layer of conductive plug (not labeled in the figure) and at least one layer of Metal interconnection line (not shown, refer to Metal in fig. 10) are formed on the semiconductor substrate 100 through a Metal wiring process (including interlayer dielectric layer deposition, contact hole etching, contact hole filling, Metal interconnection process, etc.), wherein one portion of the Metal interconnection structure electrically connects the polysilicon plate of at least one logic transistor and at least one decoupling capacitor to the power line VDD, and another portion of the Metal interconnection structure electrically connects at least one logic transistor and the semiconductor substrate 100 to the ground line VSS. In this embodiment, one portion of the metal interconnection structure electrically connects the drain D of one high voltage transistor and the polysilicon plate (i.e., the polysilicon layer 107) of one decoupling capacitor to the power line VDD through the corresponding metal silicide, and the other portion of the metal interconnection structure electrically connects the source S of one low voltage transistor and the source S of one decoupling capacitor to the ground line VSS through the corresponding metal silicide.
In other embodiments of the present invention, a corresponding metal interconnection structure may be designed and manufactured as needed, so as to connect a plurality of decoupling capacitors in series or in parallel, and design a plurality of logic transistors in series or in parallel.
In addition, in the above embodiment, the logic region I has a high-voltage transistor region and a low-voltage transistor region, and each transistor region only shows a formation region of one transistor, but the technical solution of the present invention is not limited thereto, and each transistor region may have formation regions of a plurality of transistors, and the transistors formed in each transistor region may be of the same type or different types, for example, they may be all NMOS transistors or PMOS transistors, or both NMOS transistors and PMOS transistors, LDMOS transistors, fin transistors, or ordinary planar MOS transistors, and so on. The high voltage transistor region and the low voltage transistor region in the logic region I may be replaced by other first and second regions with different operating voltages, such as a standard voltage transistor region and a low voltage transistor region, and the logic region I may further have three or more transistor regions with different operating voltages.
Referring to fig. 9 and 10, in other embodiments of the present invention, the semiconductor substrate 100 provided in step S1 may have other device regions, such as a memory region, a resistance region, and the like. When the semiconductor substrate 100 provided in step S1 has the memory area III, the manufacturing method of an integrated circuit chip of the present invention further includes forming at least one memory cell in the memory area III; and in the Metal wiring process in step S6, a corresponding Metal interconnection structure (including at least one conductive plug and at least one Metal interconnection line Metal) is formed to electrically connect the corresponding memory cell and the logic transistor.
The memory unit formed by the memory area can be an SRAM memory unit, a DRAM memory unit, a FLASH memory unit and the like. As an example, when the storage region forms an electrical structure made of polysilicon, such as a control gate of a memory cell or a word line, the polysilicon gate in the logic region I and the polysilicon plate of the decoupling capacitor in the capacitor region II may be formed together. As another example, a memory cell is formed in the memory region, and then a logic transistor and a decoupling capacitor are formed in the logic region together with the capacitor region.
Referring to fig. 9 and 10, as an example, the memory cell formed by the memory area is an SRAM memory cell, which includes a memory control transistor for storing data and a memory selection transistor for selecting to store data. The gate dielectric layer 114 of the memory control transistor is a silicon oxide-silicon nitride-silicon oxide stacked film layer, and the gate oxide layer of the memory selection transistor and the gate oxide layer of the low-voltage transistor are the same film. In this case, the method of manufacturing the integrated circuit chip still includes the above-described steps S1 to S6, with the difference that: in step S1, a low-voltage well cell-NW is formed in the storage region III at the same time as the low-voltage well LV-NW of the low-voltage transistor region LV is formed, and a corresponding shallow trench isolation structure STI is formed in the storage region III to define a memory control transistor region III-1 and a memory selection transistor III-2; in step S2, the high-k dielectric layer 104 on the storage area III is removed while the high-k dielectric layer 104 on the logic area I is removed; in step S3, before or after forming the silicon dioxide gate oxide layer required by each logic transistor on the logic region I, forming a patterned silicon oxide-silicon nitride-silicon oxide stacked film layer on the semiconductor substrate 100 in the memory control transistor region III-1 by film deposition, photolithography and etching, so as to serve as a gate dielectric layer (i.e. storage medium) 114 required in the memory control transistor region III-1, wherein the silicon dioxide layer 106 also covers the storage region III when forming the silicon dioxide layer 106; in step S4, the deposited polysilicon layer 107 further covers the storage region III, and the polysilicon layer 107 and the silicon dioxide layer 106 are patterned to form at least one polysilicon gate in the logic region I, and to form a polysilicon control gate on the gate dielectric layer of the storage control transistor region III-1 and a polysilicon gate on the silicon dioxide layer 106 (i.e., gate oxide layer) of the storage selection transistor region III-2 in the storage region III while forming at least one polysilicon plate stacked on the capacitor dielectric in the capacitor region II; in step S5, source-drain ion implantation is also performed on the storage region III to form a storage selection transistor and a storage control transistor; in step S6, a portion of the corresponding Metal interconnection structure (including at least one conductive plug and at least one Metal interconnection line Metal) is formed to electrically connect the memory select transistor and the memory control transistor and electrically connect the memory select transistor to the corresponding logic transistor, for example, to electrically connect the drain D of the memory control transistor and the source S of the memory select transistor and to electrically connect the drain D of the memory select transistor and the source S of the high voltage transistor.
It should be noted that, when the semiconductor substrate has a memory region III, a logic region I and a capacitor region II, in the technical solution of the present invention, the process in the logic region I is a standard CMOS process known to those skilled in the art, and the process in the memory region III may be a process compatible with the standard CMOS process in the logic region I, which is known to those skilled in the art, or may be a process of manufacturing other memories known to those skilled in the art. Compared with the prior art, the technical scheme of the invention only uses one additional mask for patterning the high-k dielectric layer, namely, a process of depositing, photoetching and etching the high-k dielectric layer is relatively added, and other processes can be completed by the existing process known by the technical personnel in the field.
In addition, in the manufacturing method of the integrated circuit chip of the present invention, there are four types of decoupling capacitors formed: (1) a depletion NMOS capacitor having an N-doped polysilicon plate, an N-doped source, an N-doped drain, and a P-doped channel, as shown in FIG. 11; (2) an accumulation type NMOS capacitor with N-doped polysilicon plate, N-doped source, N-doped drain, and N-doped channel, as shown in fig. 12; (3) a depletion PMOS capacitor having a P-doped polysilicon plate, a P-doped source, a P-doped drain, and an N-doped channel, as shown in FIG. 13; (4) an accumulation-mode PMOS capacitor with P-doped polysilicon plate, P-doped source, P-doped drain, and P-doped channel is shown in FIG. 14. In the integrated circuit chip with high performance, any one of three forms of depletion type NMOS capacitor, accumulation type NMOS capacitor and accumulation type PMOS capacitor is preferably used, because the depletion type PMOS capacitor is more likely to generate serious polysilicon depletion, and the effective dielectric thickness is increased, resulting in a lower capacitance value.
The decoupling capacitor formed in the manufacturing method of the integrated circuit chip has smaller leakage current and larger capacitor density when the thickness of the decoupling capacitor is the same as that of a capacitor dielectric layer (namely a silicon dioxide gate oxide layer) of an MOS capacitor in the prior art, and can be used as the decoupling capacitor required by the integrated circuit chip with a technical node of 28nm or below.
Based on the same inventive concept, please refer to fig. 8, an embodiment of the present invention further provides an integrated circuit chip with a decoupling capacitor, which is formed by the manufacturing method of the integrated circuit chip with a decoupling capacitor according to the present invention. The integrated circuit chip includes: the semiconductor device comprises a semiconductor substrate 100 having a logic region I and a capacitance region II, at least one logic transistor formed in the logic region I of the semiconductor substrate 100, at least one decoupling capacitor formed in the capacitance region II of the semiconductor substrate 100, a power line VDD, a ground line VSS and a metal interconnection structure (not shown) comprising at least one layer of conductive plug and at least one layer of metal interconnection line, wherein one part of the metal interconnection structure electrically connects the polysilicon plates of the at least one logic transistor and the at least one decoupling capacitor to the power line VDD, and the other part electrically connects the at least one logic transistor and the semiconductor substrate 100 to the ground line VSS.
Optionally, referring to fig. 10, the semiconductor substrate 100 further has a storage region III, a memory having at least one memory cell is formed in the storage region III of the semiconductor substrate 100, and a further portion of the metal interconnection structure electrically connects the memory with at least one of the logic transistors.
It should be noted that specific device structures, film materials, and the like in the logic region I, the capacitor region II, and the storage region III of the integrated circuit chip are not described herein again, and reference may be made to the description of the manufacturing method of the integrated circuit chip above.
In summary, the integrated circuit chip with the decoupling capacitor and the manufacturing method thereof of the present invention form the decoupling capacitor based on the polysilicon gate and the high-k dielectric layer, can integrate the decoupling capacitor in the standard CMOS process, and only adds one additional mask compared with the original standard CMOS process, and has the advantages of simple process and low manufacturing cost. In addition, through reasonable design of material selection and thickness of the high-k dielectric layer, the capacitance density and leakage performance of the formed decoupling capacitor are further similar to those of an MIM capacitor, and polycrystalline silicon depletion of the decoupling capacitor is controllable, so that the higher performance requirement of devices with technical nodes of 28nm and below is met.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A method of fabricating an integrated circuit chip having a decoupling capacitor, comprising:
providing a semiconductor substrate with a logic area and a capacitance area, and depositing a high-k dielectric layer with the dielectric constant higher than that of silicon dioxide on the surface of the semiconductor substrate;
patterning the high-k dielectric layer through photoetching and etching processes to remove the high-k dielectric layer in the logic area and form at least one capacitor dielectric of a decoupling capacitor in the capacitor area;
forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic area;
depositing a polysilicon layer on the silicon dioxide gate oxide layer and the high-k dielectric layer, and patterning the polysilicon layer and the silicon dioxide gate oxide layer to form at least one polysilicon gate in the logic region and a polysilicon plate stacked on the capacitor dielectric in the capacitor region;
performing source-drain ion implantation on the semiconductor substrate by taking the polysilicon gate and the polysilicon pole plate as masks to form a corresponding logic transistor in the logic region and form a corresponding decoupling capacitor in the capacitor region, wherein each decoupling capacitor is an MOS capacitor with the corresponding polysilicon pole plate;
and forming a power supply line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line on the semiconductor substrate through a metal wiring process, wherein one part of the metal interconnection structure electrically connects at least one logic transistor and at least one polysilicon plate to the power supply line, and the other part electrically connects at least one logic transistor and the semiconductor substrate to the ground line.
2. The manufacturing method according to claim 1, wherein a shallow trench isolation structure is formed in the semiconductor substrate to achieve electrical isolation between each of the logic transistors and each of the decoupling capacitors.
3. The method of manufacturing of claim 1, wherein a silicon dioxide interfacial layer is formed on the surface of the semiconductor substrate prior to depositing a high-k dielectric layer having a dielectric constant higher than silicon dioxide on the surface of the semiconductor substrate.
4. The method of claim 3, wherein when removing the high-k dielectric layer in the logic region and retaining the corresponding high-k dielectric layer in the capacitor region, the silicon dioxide interface layer in the logic region is also removed and the corresponding silicon dioxide interface layer in the capacitor region is retained, so that the finally formed capacitor dielectric of the decoupling capacitor comprises the silicon dioxide interface layer and the high-k dielectric layer which are sequentially stacked.
5. The method according to claim 1, wherein the high-k dielectric layer is a single-layer high-k dielectric material or a composite structure formed by stacking multiple layers of high-k dielectric materials, and the high-k dielectric material comprises at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium oxide, and aluminum oxide.
6. The manufacturing method according to claim 1, wherein the logic region has at least a first region and a second region which are different in operating voltage; the step of forming a silicon dioxide gate oxide layer on the semiconductor substrate of the logic area comprises the following steps: and forming silicon dioxide gate oxide layers with different thicknesses on the semiconductor substrate of the first region and the semiconductor substrate of the second region.
7. The manufacturing method according to claim 6, wherein a silicon dioxide gate oxide layer is formed on the semiconductor substrate of the logic region by at least one of a thermal oxidation process, an atomic layer deposition process, and a chemical vapor deposition process.
8. The manufacturing method according to claim 1, wherein the semiconductor substrate is further provided with a storage region, the manufacturing method further comprising forming at least one memory cell in the storage region; and in the metal wiring process, the memory cell is electrically connected with the corresponding logic transistor by the other part of the metal interconnection structure.
9. An integrated circuit chip having a decoupling capacitor formed by the method of manufacturing an integrated circuit chip having a decoupling capacitor of any one of claims 1 to 8, the integrated circuit chip comprising: the semiconductor device comprises a semiconductor substrate with a logic area and a capacitance area, at least one logic transistor formed in the logic area of the semiconductor substrate, at least one decoupling capacitor formed in the capacitance area of the semiconductor substrate, a power line, a ground line and a metal interconnection structure comprising a conductive plug and a metal interconnection line, wherein one part of the metal interconnection structure electrically connects the polysilicon plates of the at least one logic transistor and the at least one decoupling capacitor to the power line, and the other part electrically connects the at least one logic transistor and the semiconductor substrate to the ground line.
10. The integrated circuit chip of claim 9, wherein the semiconductor substrate further has a storage region, a memory having at least one memory cell is formed in the storage region of the semiconductor substrate, and a further portion of the metal interconnect structure electrically connects the memory cell with at least one of the logic transistors.
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