CN113793851B - Method for forming nonvolatile memory - Google Patents
Method for forming nonvolatile memory Download PDFInfo
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- CN113793851B CN113793851B CN202111344598.2A CN202111344598A CN113793851B CN 113793851 B CN113793851 B CN 113793851B CN 202111344598 A CN202111344598 A CN 202111344598A CN 113793851 B CN113793851 B CN 113793851B
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a method for forming a nonvolatile memory, which comprises the following steps: sequentially forming a low-voltage well region, a high-voltage well region and a cell region in a substrate; forming a patterned first polysilicon layer on the substrate of the high-voltage well region and the cell region; forming an ONO layer on the patterned first polysilicon layer; forming a second polysilicon layer on the substrate of the low-voltage well region and the ONO layer; sequentially etching a second polysilicon layer, an ONO layer and a patterned first polysilicon layer on the high-voltage well region and the cell region to form a second grid, an inter-grid dielectric layer and a first grid, wherein the second grid, the inter-grid dielectric layer and the first grid are all in columnar structures and are aligned, and the cross-sectional areas are the same; etching the second polysilicon layer on the substrate of the low-voltage well region to form a third grid, removing the second grid on the high-voltage well region and the inter-grid dielectric layer to expose the first grid; contact holes are formed on the surface of the third grid electrode, the surface of the first grid electrode and the surface of the second grid electrode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a nonvolatile memory.
Background
The semiconductor memory is one of the key components in the modern electronic technology, and promotes the digitalization and informatization development of the modern society. They can be broadly divided into volatile memories and non-volatile memories according to the length of time they hold data. The nonvolatile memory has the characteristics of long data retention time, no loss in power failure and low power consumption. Non-volatile charge trap memory is a popular solid-state memory technology because of its excellent data storage performance and device scalability. In modern electronics, nonvolatile charge trap type memories play a very important role, from portable electronic systems to large data centers.
In a manufacturing process of a 1T cell NVM (non-volatile memory) semiconductor chip, the non-volatile memory is divided into a low-voltage well region, a high-voltage well region and a cell region, and the cell region is used in a Dual-POLY (POLY-ONO-POLY) structure. Since the structure determines the formation of various semiconductor devices, the process complexity is very high, the requirement for process integration is also very high, and it is not easy to find a suitable process flow for manufacturing Dual-POLY.
In the prior art, the method for forming Dual-POLY (POLY-ONO-POLY) structure in the cell area generally comprises the following steps: growing P1 film, namely forming a lower polysilicon layer POLY 1; etching to remove the P1 film of the low-voltage well region, and forming a grid electrode in the high-voltage well region and a first grid electrode in the Cell region; growing an ONO insulator (inter-gate dielectric layer); etching to remove the ONO in the low-voltage well region; growing P2 film, namely an upper polysilicon layer POLY 2; etching to remove the upper polysilicon layer of the high-voltage well region and forming a second grid, namely a Dual-POLY structure; finally, etching an upper polysilicon layer POLY of the low-voltage well region to form a third grid; and connecting corresponding contact holes on the polycrystalline silicon exposed in all the areas. However, this method has the following disadvantages: the second grid etching requires that the second grid development of the previous process has high alignment precision; the area of the upper polysilicon layer in the Cell area is larger than that of the lower polysilicon layer POLY1, which is not favorable for reducing the area of a single Cell area, and thus, the Cell area needs to be larger, which is not favorable for miniaturization of the nonvolatile memory. The other method is as follows: growing P1 film, namely forming a lower polysilicon layer POLY 1; forming insulation isolation between adjacent second gates of the same Word Line by etching the P1 film; growing an ONO insulator (inter-gate dielectric layer); removing ONO film of the low-voltage well region and the high-voltage well region by ONO etching, and then further removing P1 film of the low-voltage well region and the high-voltage well region; growing P2 film, namely an upper polysilicon layer POLY 2; etching P2, ONO film and P1 to form a Dual-POLY structure (from top to bottom: P2/ONO/P1, and the edges are cut off); finally, etching the P2 of the low-voltage well region and the high-voltage well region to form a third grid and a grid of the high-voltage well region; and connecting corresponding connecting holes on the polycrystalline silicon exposed in all the areas. However, this method has the following disadvantages: removing the P1 film of the low-voltage well region and the high-voltage well region after the ONO etching is an unnecessary step, and the process is relatively complex; the P1 film is used only to form the first gate of the Cell area, and does not fully function.
Disclosure of Invention
The invention aims to provide a method for forming a nonvolatile memory, which can realize a double-gate stack structure of a second gate, an inter-gate dielectric layer and a first gate in a cell region, and meanwhile, the forming steps are simple, and the occupied area of the formed stack structure is small.
In order to achieve the above object, the present invention provides a method for forming a nonvolatile memory, including:
providing a substrate;
sequentially forming a low-voltage well region, a high-voltage well region and a cell region in the substrate, wherein the low-voltage well region, the high-voltage well region and the cell region are all separated by using shallow trench isolation structures;
forming a patterned first polysilicon layer on the substrate of the high-voltage well region and the cell region, wherein the patterned first polysilicon layer exposes a shallow trench isolation structure between the high-voltage well region and the cell region;
forming an ONO layer on the patterned first polysilicon layer, wherein the ONO layer also covers the shallow trench isolation structure between the high-voltage well region and the cell region;
forming a second polysilicon layer on the substrate of the low-voltage well region and the ONO layer;
sequentially etching the second polysilicon layer, the ONO layer and the first polysilicon layer to form a second grid, an inter-grid dielectric layer and a first grid on the substrate of the high-voltage well region and the cell region, wherein the second grid, the inter-grid dielectric layer and the first grid are all in a columnar structure and are aligned, and the cross sectional areas of the second grid, the inter-grid dielectric layer and the first grid are all the same;
etching the second polysilicon layer of the low-voltage well region to form a third grid, and removing the second grid and the inter-grid dielectric layer on the high-voltage well region to expose the first grid;
and forming contact holes on the third grid, the first grid and the second grid.
Optionally, in the method for forming a non-volatile memory, after providing a substrate, a gate oxide layer is further formed on the substrate.
Optionally, in the method for forming a nonvolatile memory, the method for forming the shallow trench isolation structure includes: and etching the gate oxide layer and the substrate to form a groove, and filling the groove to form a shallow groove isolation structure.
Optionally, in the method for forming a nonvolatile memory, the method for forming a patterned first polysilicon layer includes:
and forming a first polysilicon layer on the gate oxide layer, and etching to remove the first polysilicon layer of the low-voltage well region so as to expose the substrate of the low-voltage well region.
Optionally, in the method for forming the nonvolatile memory, the first polysilicon layer is doped polysilicon, and the second polysilicon layer is undoped polysilicon.
Optionally, in the method for forming a nonvolatile memory, the method for forming the ONO layer of the hvw region and the cell region includes:
forming an ONO layer on the surface of the substrate of the low-voltage well region and the patterned first polycrystalline silicon layer;
and etching and removing the ONO layer on the surface of the substrate of the low-voltage well region to expose the substrate of the low-voltage well region.
Optionally, in the method for forming the nonvolatile memory, the low-voltage well region includes a low-voltage P-type well region and a low-voltage N-type well region, and the low-voltage P-type well region and the low-voltage N-type well region are separated by using a shallow trench isolation structure.
Optionally, in the method for forming the nonvolatile memory, the substrate of the low-voltage P-type well region and the substrate of the low-voltage N-type well region both have a third gate.
Optionally, in the method for forming the nonvolatile memory, the high-voltage well region includes a high-voltage P-type well region and a high-voltage N-type well region, and the high-voltage P-type well region and the high-voltage N-type well region are separated by using a shallow trench isolation structure.
Optionally, in the method for forming the nonvolatile memory, the substrate of the high-voltage P-type well region and the substrate of the high-voltage N-type well region both have a first gate.
In the forming method of the nonvolatile memory provided by the invention, a double-gate stack structure of a second gate, an inter-gate dielectric layer and a first gate in a cell region can be realized, the cross sections of the second gate and the first gate have the same area, the area occupied by the first gate can be reduced, and the volume of the nonvolatile memory is further reduced.
Drawings
FIG. 1 is a flow chart of a method of forming a non-volatile memory according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a non-volatile memory after well formation according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a non-volatile memory after forming a first polysilicon layer in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a non-volatile memory after forming an ONO layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a non-volatile memory after etching a portion of the ONO layer in accordance with one embodiment of the present invention;
FIG. 6 is a schematic diagram of a non-volatile memory after forming a second polysilicon layer in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a non-volatile memory after forming a second gate in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram of a nonvolatile memory after forming a third gate in accordance with an embodiment of the present invention;
FIG. 9 is a schematic diagram of a non-volatile memory after forming a contact hole according to an embodiment of the invention;
in the figure: 110-substrate, 141-low-voltage P-type well region, 142-low-voltage N-type well region, 143-high-voltage P-type well region, 144-high-voltage N-type well region, 145-cell region, 120-gate oxide layer, 130-shallow trench isolation structure, 151-first polysilicon layer, 152-patterned first polysilicon layer, 153-first gate, 161-ONO layer, 162-inter-gate dielectric layer, 171-second polysilicon layer, 172-second gate, 173-third gate and 180-contact hole.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present invention provides a method for forming a non-volatile memory, including:
s1: providing a substrate;
s2: sequentially forming a low-voltage well region, a high-voltage well region and a cell region in the substrate, wherein the low-voltage well region, the high-voltage well region and the cell region are all separated by using shallow trench isolation structures;
s3: forming a patterned first polysilicon layer on the substrate of the high-voltage well region and the cell region, wherein the patterned first polysilicon layer exposes a shallow trench isolation structure between the high-voltage well region and the cell region;
s4: forming an ONO layer on the patterned first polysilicon layer, wherein the ONO layer also covers the shallow trench isolation structure between the high-voltage well region and the cell region;
s5: forming a second polysilicon layer on the substrate of the low-voltage well region and the ONO layer;
s6: sequentially etching the second polysilicon layer, the ONO layer and the first polysilicon layer to form a second grid, an inter-grid dielectric layer and a first grid on the substrate of the high-voltage well region and the cell region, wherein the second grid, the inter-grid dielectric layer and the first grid are all in a columnar structure and are aligned, and the cross sectional areas of the second grid, the inter-grid dielectric layer and the first grid are all the same;
s7: etching the second polysilicon layer of the low-voltage well region to form a third grid, and removing the second grid and the inter-grid dielectric layer on the high-voltage well region to expose the first grid;
s8: and forming contact holes on the third grid, the first grid and the second grid.
Referring to fig. 2, a substrate 110 is provided, the substrate 110 may be a wafer, a gate oxide layer 120, which may be silicon dioxide, is formed on the substrate 110, and the gate oxide layer 120 and the substrate 110 are etched and filled with oxide to form a plurality of spaced shallow trench isolation structures 130. Implanting ions into the substrate 110 between the shallow trench isolation structures 130 to form a plurality of regions, for example, a low-voltage well region, a high-voltage well region and a cell region 145, wherein the low-voltage well region is adjacent to the high-voltage well region, the high-voltage well region is adjacent to the cell region 145, the low-voltage well region is further divided into a low-voltage P-type well region 141 and a low-voltage N-type well region 142, the high-voltage well region is further divided into a high-voltage P-type well region 143 and a high-voltage N-type well region 144, the regions formed in the substrate are sequentially divided into a low-voltage P-type well region 141, a low-voltage N-type well region 142, a high-voltage P-type well region 143, a high-voltage N-type well region 144 and a cell region 145, the shallow trench isolation structures 130 are disposed between the regions close to the substrate 110 for isolation, each shallow trench isolation structure 130 is divided into two parts, respectively disposed in the two adjacent regions, for example, the shallow trench isolation structure 130 between the low-voltage P-type well region 141 and the low-voltage N-type well region 142, half of which is disposed in the low-voltage P-type well region 141, the other half is in the low voltage N-well region 142, and besides, the cell region 145 has a shallow trench isolation structure 130 to divide the cell region 145 into two regions. The implanted ions are conventional and will not be described herein.
Next, referring to fig. 3 and fig. 4, a first polysilicon layer 151 is formed on the surface of the gate oxide layer 120 and the shallow trench isolation structure 130, the first polysilicon layer 151 is doped polysilicon, the first polysilicon layer 151 on the gate oxide layer 120 of the low-voltage well region and the shallow trench isolation structure 130 of the low-voltage well region is etched to remove the gate oxide layer 120 of the low-voltage well region and the shallow trench isolation structure 130 of the low-voltage well region, and the gate oxide layer 120 of the low-voltage well region and the shallow trench isolation structure 130 of the low-voltage well region are exposed. Meanwhile, a portion of the first polysilicon layer 151 on the shallow trench isolation structure 130 between the hvw region and the cell region 145 is etched away, i.e., a patterned first polysilicon layer 152 is formed on the gate oxide layer 120 of the hvw region and the shallow trench isolation structure 130, and a patterned first polysilicon layer 152 is formed on the cell region 145.
Next, with reference to fig. 4, and with reference to fig. 5, an ONO layer 161 is formed on the gate oxide layer 120 and the shallow trench isolation structure 130 of the low-voltage well region, on the patterned first polysilicon layer 152, and on the shallow trench isolation structure 130 between the patterned first polysilicon layer 152, and then the ONO layer 161 on the gate oxide layer 120 and the shallow trench isolation structure 130 of the low-voltage well region is etched away to expose the gate oxide layer 120 and the shallow trench isolation structure 130 of the low-voltage well region.
Next, referring to fig. 6 and 7, a second polysilicon layer 171 is formed on the gate oxide layer 120 and the shallow trench isolation structure 130 of the low-voltage well region and the remaining ONO layer 161, wherein the second polysilicon layer 171 is undoped polysilicon. The second polysilicon layer 171, the ONO layer 161 and the patterned first polysilicon layer 152 of the hvw region and the cell region 145 are etched to form the second gate 172, the inter-gate dielectric layer 162 and the first gate 153, respectively, and the etching is a one-step etching. The first gate 153 is respectively located on the gate oxide layer 120 of the high-voltage P-type well region 143, the gate oxide layer 120 of the high-voltage N-type well 144 and the gate oxide layer 120 of the cell region 145, the inter-gate dielectric layer 162 is located on the first gate 153, and the second gate 172 is located on the inter-gate dielectric layer 162. The second gate 172, the inter-gate dielectric layer 162 and the first gate 153 are all in a columnar structure, the cross sections (parallel to the substrate surface) of the second gate 172, the inter-gate dielectric layer 162 and the first gate 153 are the same in size, and the second gate 172, the inter-gate dielectric layer 162 and the first gate 153 are all aligned.
Next, referring to fig. 7 and 8, the second polysilicon layer 171 of the low-voltage well region is etched to form a third gate 173 on the gate oxide layer 120 of the low-voltage P-type well region 141 and a third gate 120 on the gate oxide layer of the low-voltage N-type well region 142. Meanwhile, the second gate 172 and the inter-gate dielectric layer 162 of the high-voltage P-well region 143 are removed to expose the first gate 172, and the second gate 172 and the inter-gate dielectric layer 162 of the high-voltage N-well region 144 are removed to expose the first gate 172.
Next, referring to fig. 9, contact holes 180 are formed on the third gate 173, the first gate 172 and the second gate 172.
In summary, in the method for forming a nonvolatile memory according to the embodiments of the present invention, a dual-gate stack structure including a second gate, an inter-gate dielectric layer, and a first gate in a cell region may be implemented, and cross-sectional areas of the second gate and the first gate are the same, so that an area occupied by the first gate may be reduced, and a volume of the nonvolatile memory may be reduced.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for forming a non-volatile memory, comprising:
providing a substrate;
sequentially forming a low-voltage well region, a high-voltage well region and a cell region in the substrate, wherein the low-voltage well region, the high-voltage well region and the cell region are all separated by using shallow trench isolation structures;
forming a patterned first polysilicon layer on the substrate of the high-voltage well region and the cell region, wherein the patterned first polysilicon layer exposes a shallow trench isolation structure between the high-voltage well region and the cell region;
forming an ONO layer on the patterned first polysilicon layer, wherein the ONO layer also covers the shallow trench isolation structure between the high-voltage well region and the cell region;
forming a second polysilicon layer on the substrate of the low-voltage well region and the ONO layer;
sequentially etching the second polysilicon layer, the ONO layer and the first polysilicon layer to form a second grid, an inter-grid dielectric layer and a first grid on the substrate of the high-voltage well region and the cell region, wherein the second grid, the inter-grid dielectric layer and the first grid are all in a columnar structure and are aligned, and the cross sectional areas of the second grid, the inter-grid dielectric layer and the first grid are all the same;
etching the second polysilicon layer of the low-voltage well region to form a third grid, and removing the second grid and the inter-grid dielectric layer on the high-voltage well region to expose the first grid;
and forming contact holes on the third grid, the first grid and the second grid.
2. The method of forming a non-volatile memory as claimed in claim 1, further comprising forming a gate oxide layer on said substrate after providing said substrate.
3. The method of forming a non-volatile memory as claimed in claim 2, wherein the method of forming the shallow trench isolation structure comprises: and etching the gate oxide layer and the substrate to form a groove, and filling the groove to form a shallow groove isolation structure.
4. The method of forming a non-volatile memory of claim 2, wherein the method of forming the patterned first polysilicon layer comprises:
and forming a first polysilicon layer on the gate oxide layer, and etching to remove the first polysilicon layer of the low-voltage well region so as to expose the substrate of the low-voltage well region.
5. The method of claim 4, wherein the first polysilicon layer is doped polysilicon and the second polysilicon layer is undoped polysilicon.
6. The method of claim 1, wherein the method of forming the ONO layer of the HVW region and the cell region comprises:
forming an ONO layer on the surface of the substrate of the low-voltage well region and the patterned first polycrystalline silicon layer;
and etching and removing the ONO layer on the surface of the substrate of the low-voltage well region to expose the substrate of the low-voltage well region.
7. The method of claim 1, wherein the low-voltage well region comprises a low-voltage P-type well region and a low-voltage N-type well region, and the low-voltage P-type well region and the low-voltage N-type well region are separated by a shallow trench isolation structure.
8. The method of claim 7, wherein the low voltage P-well and N-well regions have a third gate over the substrate.
9. The method of claim 1, wherein the hvw region comprises a hvp region and a hvn region separated by a shallow trench isolation structure.
10. The method of claim 9, wherein the hvpwr and hvnwr have a first gate over the substrate.
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| CN115881524A (en) * | 2023-02-22 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Embedded flash memory, embedded flash memory grid and preparation method |
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| CN102945832A (en) * | 2012-11-20 | 2013-02-27 | 上海宏力半导体制造有限公司 | Process for forming flash memory device |
| CN105336695A (en) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN108074933A (en) * | 2016-11-16 | 2018-05-25 | 无锡华润上华科技有限公司 | Memory and preparation method thereof |
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| KR100648283B1 (en) * | 2005-03-16 | 2006-11-23 | 삼성전자주식회사 | Method of forming non-volatile memory device and the same device so formed |
| US10825522B2 (en) * | 2018-10-29 | 2020-11-03 | United Microelectronics Corp. | Method for fabricating low and high/medium voltage transistors on substrate |
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| CN102945832A (en) * | 2012-11-20 | 2013-02-27 | 上海宏力半导体制造有限公司 | Process for forming flash memory device |
| CN105336695A (en) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN108074933A (en) * | 2016-11-16 | 2018-05-25 | 无锡华润上华科技有限公司 | Memory and preparation method thereof |
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