US20030003660A1 - Structure of an embedded channel write/erase flash memory cell and fabricating method thereof - Google Patents

Structure of an embedded channel write/erase flash memory cell and fabricating method thereof Download PDF

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US20030003660A1
US20030003660A1 US09/865,432 US86543201A US2003003660A1 US 20030003660 A1 US20030003660 A1 US 20030003660A1 US 86543201 A US86543201 A US 86543201A US 2003003660 A1 US2003003660 A1 US 2003003660A1
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well
flash memory
memory cell
layer
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Ching-Hsiang Hsu
Ching-Sung Yang
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Powerchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, which can not only effectively improve the operating efficiency of flash memory cell and CMOS device, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
  • flash memories and CMOS logical circuits are separately designed and fabricated. Although designers can select and match them according to required circuit designs, the volumes after integrated are unsatisfactorily larger for present demands.
  • most products have been standardized, and mutual collocations of most products have specific modes. Therefore, if an IC combining flash memories and CMOS logical circuits is designed according to most of the specifications, the occupied space can be effectively reduced.
  • the present invention aims to propose a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, which can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
  • the primary object of the present invention is to provide a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, wherein flash memory cell structures and CMOS logical devices are simultaneously fabricated on a substrate so that the flash memory cell structures and the CMOS logical devices can be combined and the whole occupied space can be reduced.
  • FIG. 1 is a cross-sectional view showing the process flow according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit diagram according to a preferred embodiment of the present invention.
  • FIGS. 1A to 1 Z show the process flow according to a preferred embodiment of the present invention.
  • the process flow comprises the following steps:
  • Step A A deep P-well 12 of the flash memory cell, a first deep P-well 12 a of the CMOS device, and a second deep P-well 12 b of the CMOS device are implanted in proper positions of an N-substrate 10 , as shown in FIG. 1A;
  • Step B An N-well 14 is implanted in the deep P-well 12 of flash memory cell, a first N-well 14 a is implanted in the first deep P-well 12 a of the CMOS device, and a second N-well 14 b is implanted in the second deep P-well 12 b of the CMOS device, as shown in FIG. 1B;
  • Step C A first P-well 13 a and a second P-well 13 b are implanted between the first deep P-well 12 a and the second deep P-well 12 b of the CMOS device in the N-substrate 10 , as shown in FIG. 1C;
  • Step D A shallow p-type region 15 is implanted on the surface of the N-well 14 in the deep P-well of the flash memory cell, as shown in FIG. 1D;
  • Step E A tunnel oxide layer 20 is grown on the substrate 10 , and a first polysilicon layer 22 is deposited, as shown in FIG. 1E;
  • Step G An oxide-nitride-oxide (ONO) film 24 is deposited on the first polysilicon layer 22 , and the ONO film 24 on the CMOS device is etched, as shown in FIG. 1G;
  • ONO oxide-nitride-oxide
  • Step H A thick oxide layer 25 is grown on the CMOS device, and the thick oxide layer 25 on the second N-well 14 b and the second P-well 13 b are locally etched, as shown in FIG. 1H;
  • Step I A thin oxide layer 26 is grown on the second N-well 14 b and the second P-well 13 b of the CMOS device, as shown in FIG. 11;
  • Step J A second polysilicon layer 27 and a tungsten silicide 28 are deposited, as shown in FIG. 1J;
  • Step K The tunnel oxide layer 20 and all grown and deposited layers on the flash memory cell are etched to form a rectangular stacked layer 30 , whose two sides being exposed region of the tunnel oxide layer, and oxidation is performed to form a smiling effect oxide 21 between the rectangular stacked layer 30 and the N-well 14 , as shown in FIG. 1K;
  • Step L A deep p-type region 16 is implanted at one side of the rectangular stacked layer 30 in the flash memory cell and in the N-well 14 , as shown in FIG. 1L;
  • Step M N-type regions 17 and 18 are implanted at two sides of the rectangular stacked layer 30 in the flash memory cell, respectively, and in the N-well 14 , as shown in FIG. 1M;
  • Step N All grown and deposited layers on the CMOS device are etched to respectively form stacked layers 30 a , 30 b , 30 c , and 30 d , as shown in FIG. 1N;
  • Step O A first lightly doped n-type region 130 b is implanted at two sides of the stacked layer 30 c on the second P-well 13 b of the CMOS device, as shown in FIG. 1O;
  • Step P A first lightly doped p-type region 140 b is implanted at two sides of the stacked layer 30 d on the second N-well 14 b of the CMOS device, as shown in FIG. 1P;
  • Step Q A second lightly doped n-type region 130 a is implanted at two sides of the stacked layer 30 b on the second P-well 13 a of the CMOS device, as shown in FIG. 1Q;
  • Step R A second lightly doped p-type region 140 a is implanted at two sides of the stacked layer 30 a on the second N-well 14 a of the CMOS device, as shown in FIG. 1R;
  • Step S An insulating layer is deposited, and side wall spacers 120 a and 120 b are etched out, a higher doped n-type region 131 b is implanted at two sides of the stacked layer 30 b on the first P-well 13 a of the CMOS device, and a higher doped n-type region 131 a is implanted at two sides of the stacked layer 30 c on the second P-well 13 b of the CMOS device, as shown in FIG. 1S;
  • Step T A higher doped p-type region 141 b is implanted at two sides of the stacked layer 30 a on the first N-well 14 a of the CMOS device, and a higher doped p-type region 141 a is implanted at two sides of the stacked layer 30 d on the second N-well 14 b of the CMOS device, as shown in FIG. 1T;
  • Step U An insulating layer 32 is formed to cover the rectangular stacked layer 30 and the stacked layers 30 a , 30 b , 30 c , and 30 d on the substrate 10 , as shown in FIG. 1U;
  • Step V Contact holes 33 are etched out at one side of the rectangular stacked layer 30 and two sides of the stacked layers 30 a , 30 b , 30 c , and 30 d on the substrate 10 to expose part of the implanted regions.
  • Silicide 34 is deposited in the implanted regions below the contact holes 33 .
  • the implanted regions in part of the N-well and P-well are deepened to prevent the deposited silicide 34 from penetrating the junctions, as shown in FIG. 1V;
  • Step W A first metal layer 40 is deposited on the insulating layer 32 and locally etched so that each of the contact holes has a first metal interconnect 401 therein, as shown in FIG. 1W;
  • Step X A first dielectric layer 42 is deposited on the first metal layer 40 , and a plurality of contact vias 422 are etched out, as shown in FIG. 1X;
  • Step Y A second metal layer 44 is formed on the first dielectric layer 42 and locally etched so that each of the contact vias 422 has a second metal interconnect 441 , as shown in FIG. 1Y;
  • Step Z Steps X and Y are repeated till the required level. An encapsulation 50 is finally deposited to cover on the metal layer, as shown in FIG. 1Z.
  • the present invention has low-voltage CMOS devices and high-voltage CMOS devices.
  • the low-voltage CMOS devices are mainly used in logical controllers and encoders, and the high-voltage CMOS devices are mainly used in high-voltage switches, word-line drivers. Therefore, the low-voltage CMOS devices need to meet the requirement of high-speed operation, and the high-voltage CMOS devices need to be capable of bearing a higher breakage voltage.
  • the operating mode of the flash memory cell is shown in Table 1. If the reading operation is performed, the word line voltage is 3.3 V, the bit line voltage is 0V, and the source line voltage is 1 V. TABLE 1 Source line Word line voltage Bit line voltage voltage Program ⁇ 10 V 5 V Floating Erase 10 V Floating ⁇ 8 V Read 3.3 V 0 V 1 V
  • the present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, which can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.

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Abstract

The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, which can not only effectively improve the operating efficiency of flash memory cell and CMOS device, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells. [0001]
    • BACKGROUND OF THE INVENTION
  • Generally, flash memories and CMOS logical circuits are separately designed and fabricated. Although designers can select and match them according to required circuit designs, the volumes after integrated are unsatisfactorily larger for present demands. Nowadays, most products have been standardized, and mutual collocations of most products have specific modes. Therefore, if an IC combining flash memories and CMOS logical circuits is designed according to most of the specifications, the occupied space can be effectively reduced. [0002]
  • Accordingly, the present invention aims to propose a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, which can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells. [0003]
    • SUMMARY OF THE INVENTION
  • The primary object of the present invention is to provide a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, wherein flash memory cell structures and CMOS logical devices are simultaneously fabricated on a substrate so that the flash memory cell structures and the CMOS logical devices can be combined and the whole occupied space can be reduced. [0004]
  • The secondary object of the present invention is to provide a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof, wherein CMOS devices capable of performing high-voltage and low-voltage operations are reserved, hence effectively enhancing the whole operating efficiency. [0005]
  • The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:[0006]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view showing the process flow according to a preferred embodiment of the present invention; and [0007]
  • FIG. 2 is a circuit diagram according to a preferred embodiment of the present invention.[0008]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Please refer to FIGS. 1A to [0009] 1Z, which show the process flow according to a preferred embodiment of the present invention. The process flow comprises the following steps:
  • Step A: A deep P-[0010] well 12 of the flash memory cell, a first deep P-well 12 a of the CMOS device, and a second deep P-well 12 b of the CMOS device are implanted in proper positions of an N-substrate 10, as shown in FIG. 1A;
  • Step B: An N-[0011] well 14 is implanted in the deep P-well 12 of flash memory cell, a first N-well 14 a is implanted in the first deep P-well 12 a of the CMOS device, and a second N-well 14 b is implanted in the second deep P-well 12 b of the CMOS device, as shown in FIG. 1B;
  • Step C: A first P-[0012] well 13 a and a second P-well 13 b are implanted between the first deep P-well 12 a and the second deep P-well 12 b of the CMOS device in the N-substrate 10, as shown in FIG. 1C;
  • Step D: A shallow p-[0013] type region 15 is implanted on the surface of the N-well 14 in the deep P-well of the flash memory cell, as shown in FIG. 1D;
  • Step E: A [0014] tunnel oxide layer 20 is grown on the substrate 10, and a first polysilicon layer 22 is deposited, as shown in FIG. 1E;
  • Step F: The [0015] tunnel oxide layer 20 and the first polysilicon layer 22 on the CMOS device are etched, as shown in FIG. 1F;
  • Step G: An oxide-nitride-oxide (ONO) [0016] film 24 is deposited on the first polysilicon layer 22, and the ONO film 24 on the CMOS device is etched, as shown in FIG. 1G;
  • Step H: A [0017] thick oxide layer 25 is grown on the CMOS device, and the thick oxide layer 25 on the second N-well 14 b and the second P-well 13 b are locally etched, as shown in FIG. 1H;
  • Step I: A [0018] thin oxide layer 26 is grown on the second N-well 14 b and the second P-well 13 b of the CMOS device, as shown in FIG. 11;
  • Step J: A [0019] second polysilicon layer 27 and a tungsten silicide 28 are deposited, as shown in FIG. 1J;
  • Step K: The [0020] tunnel oxide layer 20 and all grown and deposited layers on the flash memory cell are etched to form a rectangular stacked layer 30, whose two sides being exposed region of the tunnel oxide layer, and oxidation is performed to form a smiling effect oxide 21 between the rectangular stacked layer 30 and the N-well 14, as shown in FIG. 1K;
  • Step L: A deep p-[0021] type region 16 is implanted at one side of the rectangular stacked layer 30 in the flash memory cell and in the N-well 14, as shown in FIG. 1L;
  • Step M: N-[0022] type regions 17 and 18 are implanted at two sides of the rectangular stacked layer 30 in the flash memory cell, respectively, and in the N-well 14, as shown in FIG. 1M;
  • Step N: All grown and deposited layers on the CMOS device are etched to respectively form stacked [0023] layers 30 a, 30 b, 30 c, and 30 d, as shown in FIG. 1N;
  • Step O: A first lightly doped n-[0024] type region 130 b is implanted at two sides of the stacked layer 30 c on the second P-well 13 b of the CMOS device, as shown in FIG. 1O;
  • Step P: A first lightly doped p-[0025] type region 140 b is implanted at two sides of the stacked layer 30 d on the second N-well 14 b of the CMOS device, as shown in FIG. 1P;
  • Step Q: A second lightly doped n-[0026] type region 130 a is implanted at two sides of the stacked layer 30 b on the second P-well 13 a of the CMOS device, as shown in FIG. 1Q;
  • Step R: A second lightly doped p-[0027] type region 140 a is implanted at two sides of the stacked layer 30 a on the second N-well 14 a of the CMOS device, as shown in FIG. 1R;
  • Step S: An insulating layer is deposited, and [0028] side wall spacers 120 a and 120 b are etched out, a higher doped n-type region 131 b is implanted at two sides of the stacked layer 30 b on the first P-well 13 a of the CMOS device, and a higher doped n-type region 131 a is implanted at two sides of the stacked layer 30 c on the second P-well 13 b of the CMOS device, as shown in FIG. 1S;
  • Step T: A higher doped p-type region [0029] 141 b is implanted at two sides of the stacked layer 30 a on the first N-well 14 a of the CMOS device, and a higher doped p-type region 141 a is implanted at two sides of the stacked layer 30 d on the second N-well 14 b of the CMOS device, as shown in FIG. 1T;
  • Step U: An [0030] insulating layer 32 is formed to cover the rectangular stacked layer 30 and the stacked layers 30 a, 30 b, 30 c, and 30 d on the substrate 10, as shown in FIG. 1U;
  • Step V: [0031] Contact holes 33 are etched out at one side of the rectangular stacked layer 30 and two sides of the stacked layers 30 a, 30 b, 30 c, and 30 d on the substrate 10 to expose part of the implanted regions. Silicide 34 is deposited in the implanted regions below the contact holes 33. The implanted regions in part of the N-well and P-well are deepened to prevent the deposited silicide 34 from penetrating the junctions, as shown in FIG. 1V;
  • Step W: A [0032] first metal layer 40 is deposited on the insulating layer 32 and locally etched so that each of the contact holes has a first metal interconnect 401 therein, as shown in FIG. 1W;
  • Step X: A [0033] first dielectric layer 42 is deposited on the first metal layer 40, and a plurality of contact vias 422 are etched out, as shown in FIG. 1X;
  • Step Y: A [0034] second metal layer 44 is formed on the first dielectric layer 42 and locally etched so that each of the contact vias 422 has a second metal interconnect 441, as shown in FIG. 1Y; and
  • Step Z: Steps X and Y are repeated till the required level. An [0035] encapsulation 50 is finally deposited to cover on the metal layer, as shown in FIG. 1Z.
  • It is noted that the present invention has low-voltage CMOS devices and high-voltage CMOS devices. The low-voltage CMOS devices are mainly used in logical controllers and encoders, and the high-voltage CMOS devices are mainly used in high-voltage switches, word-line drivers. Therefore, the low-voltage CMOS devices need to meet the requirement of high-speed operation, and the high-voltage CMOS devices need to be capable of bearing a higher breakage voltage. The operating mode of the flash memory cell is shown in Table 1. If the reading operation is performed, the word line voltage is 3.3 V, the bit line voltage is 0V, and the source line voltage is 1 V. [0036]
    TABLE 1
    Source line
    Word line voltage Bit line voltage voltage
    Program −10 V 5 V Floating
    Erase  10 V Floating −8 V
    Read  3.3 V 0 V  1 V
  • To sum up, the present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, which can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells. [0037]
  • Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. P-type semiconductors and n-type semiconductors can interchange each other in the structure of the present invention. For instance, the N-well/deep P-well/N-substrate structure can be replaced with the P-well/deep N-well/P-substrate structure. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims. [0038]

Claims (23)

I claim:
1. A structure of an embedded channel write/erase flash memory cell, comprising mainly:
an N-substrate;
a flash memory cell region comprising mainly:
a deep P-well formed on said substrate;
an N-well formed on said deep P-well, a deep P-type region and
a shallow p-type region being implanted in predetermined positions of said N-well; and
a stacked gate formed on said N-well;
a CMOS device region comprising mainly:
a first deep P-well formed on said substrate;
a first N-well formed on said first deep P-well, a plurality of p-type regions being implanted in predetermined positions of said first N-well;
a second deep P-well formed on said substrate; and
a second N-well formed on said first deep P-well, a plurality of p-type regions being implanted in predetermined positions of said first N-well.
2. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein an oxide layer is further provided between said N-well and said stacked gate of said flash memory cell region.
3. The structure of an embedded channel write/erase flash memory cell as claimed in claim 2, wherein a smiling effect pattern is caused by oxidation between said stacked gate and said oxide layer.
4. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein an n-type region is further implanted in said deep p-type region in said N-well of said flash memory cell region to be used as a drain.
5. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein the implanted depth of said deep p-type region in said N-well of said flash memory cell region is larger than that of said shallow p-type region.
6. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein said deep p-type region in said N-well of said flash memory cell region is connected with one end of said shallow p-type region.
7. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein an n-type region is further implanted at the other side of said shallow p-type region in said N-well of said flash memory cell region to be used as a source.
8. The structure of an embedded channel write/erase flash memory cell as claimed in claim 7, wherein a field oxide layer and an n-type ion channel barrier layer can also be provided between said n-type region and said shallow p-type region in said N-well, said n-type ion channel barrier layer being disposed below said field oxide layer.
9. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein said n-type region implanted in said deep p-type region of said flash memory cell region is connected to said deep p-type region via an electrical short circuit.
10. The structure of an embedded channel write/erase flash memory cell as claimed in claim 9, wherein said electrical short circuit is formed by using a metal contact to penetrate a junction of said n-type region in said deep p-type region and said deep p-type region.
11. The structure of an embedded channel write/erase flash memory cell as claimed in claim 9, wherein said electrical short circuit is formed by using a metal contact to connect said exposed n-type region in said deep p-type region with said deep p-type region.
12. The structure of an embedded channel write/erase flash memory cell as claimed in claim 9, wherein said n-type semiconductors and said p-type semiconductors can interchange each other, e.g., an npn structure can be replaced with a pnp structure.
13. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein said CMOS device region further comprises a first P-well formed on said substrate and at one side of said first deep P-well.
14. The structure of an embedded channel write/erase flash memory cell as claimed in claim 13, wherein said CMOS device region further comprises a second P-well formed on said substrate and at one said of said first P-well.
15. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein said CMOS device region further comprises a first P-well formed on said first deep P-well.
16. The structure of an embedded channel write/erase flash memory cell as claimed in claim 1, wherein said CMOS device region further comprises a second P-well formed on said second deep P-well.
17. A fabricating method of an embedded channel write/erase flash memory cell, comprising the steps of:
implanting a plurality of deep P-wells at predetermined positions in an N-substrate;
implanting an N-well in each of said deep P-wells;
implanting a plurality of P-wells at predetermined positions in said N-substrate;
implanting a shallow p-type region on the surface of one of said N-wells;
growing a tunnel oxide layer on said substrate and depositing a first polysilicon layer;
removing the part of said channel oxide and first polysilicon layer on said N-well of said shallow p-type region by etching;
depositing an oxide-nitride-oxide film on said first polysilicon layer; growing a thick oxide layer on the part of said first polysilicon layer defaulted to be connected to a high voltage;
growing a thin oxide layer on the part of said first polysilicon layer defaulted to be connected to a low voltage;
depositing a second polysilicon layer;
etching said tunnel oxide layer and all grown and deposited layers on said N-well having a shallow p-type region to form a rectangular stacked layer with exposed regions of said channel oxide region at two sides thereof;
performing oxidation to form a smiling effect oxide layer between said rectangular stacked layer and the surface of said N-well;
implanting a deep p-type region at one side of said rectangular stacked layer and in said N-well;
implanting a plurality of n-type regions in said N-well and at two sides of said rectangular stacked layer;
etching all grown and deposited layers on the part of said substrate having another N-well or P-well implanted therein to form a stacked layer;
implanting a first lightly doped n-type region at two sides of said stacked layer on said another P-well;
implanting a first lightly doped p-type region at two sides of said stacked layer on said another N-well;
implanting a second lightly doped n-type region at two sides of said stacked layer on said another P-well;
implanting a second lightly doped p-type region at two sides of said stacked layer on said another N-well;
depositing an insulating layer and etching out side wall spacers;
implanting a higher doped n-type region at two sides of said stacked layer on each of said other P-wells;
implanting a higher doped p-type region at two sides of said stacked layer on each of said other N-wells;
forming an insulating layer to cover said rectangular stacked layer and said stacked layers on said substrate;
etching out a contact hole at one side and above said rectangular stacked layer and at two sides and above each said stacked layer to expose part of said implanted region; and
depositing a first metal layer on said insulating layer and locally etching said metal layer to let each said contact hole have a first metal interconnect.
18. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 17 further comprising, after said step of depositing a first metal layer on said insulating layer and then locally etching said first metal layer, the steps of:
(a). depositing a first dielectric layer on said first metal layer and etching out a plurality of contact vias;
(b). forming a second metal layer on said first dielectric layer and locally etching said second metal layer to let each said contact via have a second metal interconnect;
(c). repeating said Steps (a) and (b) till the required level; and
(d). depositing an encapsulation to cover on the final metal layer.
19. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 17 further comprising, after said step of depositing an oxide-nitride-oxide film on said first polysilicon layer, the step of:
etching part of said oxide-nitride-oxide film.
20. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 17 further comprising, after said step of depositing a second polysilicon layer on said thin oxide layer, the step of: depositing a tungsten silicide on said second polysilicon layer.
21. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 17 further comprising, after said step of etching out a contact hole at one side of said rectangular stacked layer and two sides of each said stacked layer on said substrate, the step of:
depositing silicide in the implanted region below each said contact hole.
22. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 21 further comprising, after said step of depositing silicide in the implanted region below each said contact hole, the step of:
deepening part of implanted regions in said N-wells and P-wells to prevent said deposited silicide from penetrating the junctions.
23. The fabricating method of an embedded channel write/erase flash memory cell as claimed in claim 17, wherein said n-type semiconductors and said p-type semiconductors can interchange each other, e.g., an npn structure can be replaced with a pnp structure.
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