CN116053274B - Semiconductor integrated device and manufacturing method thereof - Google Patents
Semiconductor integrated device and manufacturing method thereof Download PDFInfo
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- CN116053274B CN116053274B CN202310042314.7A CN202310042314A CN116053274B CN 116053274 B CN116053274 B CN 116053274B CN 202310042314 A CN202310042314 A CN 202310042314A CN 116053274 B CN116053274 B CN 116053274B
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
The invention discloses a semiconductor integrated device and a manufacturing method thereof, belonging to the technical field of semiconductors, wherein the semiconductor integrated device comprises: the device comprises a substrate, a first memory area and a second memory area, wherein the substrate comprises a flash memory area, a first area and a second area; a plurality of well regions disposed within the substrate; the grid electrode oxide layer is arranged on the well region; a first gate structure disposed on the flash memory region and the gate oxide layer on the first region, the first gate structure including a first gate layer, an insulating layer, and a second gate layer, the insulating layer being disposed between the first gate layer and the second gate layer; a second gate structure disposed on the gate oxide layer on the second region, the second gate structure including the second gate layer; and the heavily doped region is positioned in the well region at two sides of the first grid structure and the second grid structure. The semiconductor integrated device and the manufacturing method thereof can improve the performance and the manufacturing yield of the semiconductor integrated device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor integrated device and a manufacturing method thereof.
Background
With the increasing integration of semiconductor devices, a general trend of semiconductor devices is miniaturization of semiconductor devices. And multiple types of devices are often required to be integrated together for manufacturing, for example, different types of transistors are prepared on the same substrate, and the different transistors are isolated by a shallow trench isolation structure. However, in the manufacturing process of different transistors, the manufacturing process is different, different areas need to be manufactured respectively, the manufacturing process is complex, and lateral etching and other phenomena are easy to occur at the joints of the different areas, so that the electrical attenuation of the transistors is caused, the performance of the semiconductor device is reduced, and the manufacturing yield is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor integrated device and a manufacturing method thereof, which can improve the interface performance between different areas, simplify the manufacturing process and obtain a high-quality semiconductor integrated device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a semiconductor integrated device including:
the device comprises a substrate, a first memory region and a second memory region, wherein the substrate comprises a flash memory region, a first region and a second region;
a plurality of well regions disposed within the substrate;
the grid electrode oxide layer is arranged on the well region;
a first gate structure disposed on the flash memory region and the gate oxide layer on the first region, the first gate structure including a first gate layer, an insulating layer, and a second gate layer, the insulating layer being disposed between the first gate layer and the second gate layer;
a second gate structure disposed on the gate oxide layer on the second region, the second gate structure including the second gate layer; and
and the heavily doped region is positioned in the well region at two sides of the first grid structure and the second grid structure.
In an embodiment of the present invention, the insulating layer is one of an oxide layer, a nitride layer, and a stack of the oxide layer and the nitride layer.
In an embodiment of the present invention, the gate oxide layer includes a first gate oxide layer, and the first gate oxide layer is disposed on the first region.
In an embodiment of the present invention, the gate oxide layer includes a second gate oxide layer, the second gate oxide layer is disposed on the second region, and the thickness of the first gate oxide layer is 1.5 times to 2.5 times that of the second gate oxide layer.
In an embodiment of the present invention, the well region includes a low-voltage well region, and the low-voltage well region is disposed in the substrate on the second region.
In an embodiment of the present invention, the well region includes a high-voltage well region, the high-voltage well region is disposed in the substrate on the first region, and a doping concentration of the high-voltage well region is 1.2 times to 1.5 times that of the low-voltage well region.
The invention also provides a manufacturing method of the semiconductor integrated device, which at least comprises the following steps:
providing a substrate, wherein the substrate comprises a flash memory area, a first area and a second area;
forming a plurality of well regions within the substrate;
forming a gate oxide layer on the well region;
forming a first gate structure on the flash memory region and the gate oxide layer on the first region, wherein the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer;
forming a second gate structure on the gate oxide layer on the second region, wherein the second gate structure comprises the second gate layer; and
and forming heavy doping regions in the well regions at two sides of the first gate structure and the second gate structure.
In an embodiment of the present invention, the manufacturing method includes:
forming a first gate oxide layer on the well region;
forming a first gate layer on the first gate oxide layer, the first gate layer covering the flash memory region and the well region on the first region;
forming the insulating layer on the first gate layer and the second region;
forming a photoresist layer on the flash memory region and the first region, an
And etching the insulating layer and the first gate oxide layer on the second region by taking the photoresist layer as a mask.
In an embodiment of the present invention, the etching method includes dry etching, and the dry etching includes the steps of:
etching the insulating layer on the second region, wherein etching gas comprises at least one of argon, oxygen, hydrogen and nitrogen;
the first gate oxide layer is etched, and an etching gas includes at least one of octafluorocyclobutane, perfluorobutadiene, and difluoromethane.
In an embodiment of the present invention, the manufacturing method includes:
etching to remove the first gate oxide layer, and forming a second gate oxide layer on the second region; and
and forming a second gate layer on the insulating layer and the second gate oxide layer.
The semiconductor integrated device and the manufacturing method thereof provided by the invention can reduce the phenomenon of drilling and carving at interfaces of different areas and improve the electrical performance of the semiconductor integrated device. When the insulating layer and the first gate oxide layer are removed, damage to the substrate is reduced, interface integrity between different areas is improved, and performance of the semiconductor device is improved. Meanwhile, the etching is carried out through a one-time photomask process, the number of photomasks is not added, the manufacturing process is simplified, and the cost is reduced. And the production efficiency of the semiconductor device can be improved, and the production cost can be reduced. In summary, the present invention provides a semiconductor integrated device and a method for manufacturing the same, which can improve the performance of the semiconductor integrated device and the manufacturing yield.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a substrate distribution in an embodiment.
FIG. 2 is a schematic diagram of a shallow trench isolation structure in an embodiment.
FIG. 3 is a diagram of well sector area in one embodiment.
Fig. 4 is a schematic structural diagram of a first gate oxide layer and a first gate layer in an embodiment.
Fig. 5 is a schematic structural diagram of an insulating layer in an embodiment.
FIG. 6 is a schematic diagram illustrating removing the insulating layer on the second region according to an embodiment.
Fig. 7 is a schematic structural diagram of a second gate oxide layer in an embodiment.
Fig. 8 is a schematic structural diagram of a second gate layer in an embodiment.
FIG. 9 is a schematic diagram illustrating the locations of the gate structures on the flash memory region and the first region in an embodiment.
Fig. 10 is a schematic diagram illustrating a position of a gate structure on a second region in an embodiment.
FIG. 11 is a schematic diagram of a gate structure according to an embodiment.
Fig. 12 is a schematic diagram of a semiconductor integrated device according to an embodiment.
Description of the reference numerals:
100. a substrate; 101. a pad oxide layer; 102. pad nitriding layer; 103. a first photoresist layer; 104. shallow trench isolation structures; 105. a deep well region; 106. a first well region; 107. a second well region; 108. a third well region; 109. a fourth well region; 110. a fifth well region; 111. a first gate oxide layer; 112. a first gate layer; 113. an insulating layer; 114. a second photoresist layer; 115. a second gate oxide layer; 116. a second gate layer; 117. a third photoresist layer; 118. a first high voltage gate; 119. a second high voltage gate; 120. a select gate; 121. a cell gate; 122. a fourth photoresist layer; 123. a first low voltage gate; 124. a second low voltage gate; 130. a doped region; 131. a first high-voltage heavily doped region; 132. a second high-voltage heavily doped region; 133. a first low-voltage heavily doped region; 134. a second low-voltage heavily doped region; 10. a flash memory region; 11. a first region; 12. a second region.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The invention provides a semiconductor integrated device and a manufacturing method thereof, which can prepare semiconductor devices with different functions in different areas of the same substrate, and each semiconductor device has excellent performance. The manufacturing method of the semiconductor integrated device provided by the invention can be widely applied to the manufacturing process of various semiconductor integrated devices.
Referring to fig. 1, in an embodiment of the present invention, a substrate 100 includes, for example, a flash memory region 10, a first region 11 and a second region 12. The flash memory region 10 is provided with a plurality of flash cells, and a plurality of Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) transistors, such as P-type mosfet (PositiveChannel Metal Oxide Semiconductor, PMOS) and N-type mosfet (Negative Channel Metal Oxide Semiconductor, NMOS), may be disposed in the first region 11 and the second region 12, and the PMOS transistors and the NMOS transistors are staggered. The semiconductor devices are prepared in different areas of the same substrate, so that the production efficiency is improved, and the production cost is reduced.
Referring to fig. 1, in one embodiment of the present invention, a substrate 100 is provided first, and the substrate 100 may be any material suitable for forming, such as a silicon wafer, a germanium substrate, silicon germanium, silicon on insulator or silicon on insulator stack, etc. The invention is not limited to the type and thickness of the substrate 100, and in this embodiment, the substrate 100 is, for example, a silicon wafer, and the substrate 100 is, for example, a P-type silicon wafer, and the substrate 100 includes, for example, a flash memory region 10, a first region 11, and a second region 12. The first region 11 is, for example, provided with an edge mosfet, i.e., an IO MOS transistor, generally used for interaction between a chip and an external interface, and the working voltage is higher, and the second region 12 is, for example, provided with a Core MOS used in the device, generally having a lower working voltage. The flash memory area 10 is provided with a non-volatile flash memory structure for storing codes or system management parameters, for example. In this embodiment, the first region 11 includes one PMOS transistor and one NMOS transistor, the second region 12 includes one PMOS transistor and one NMOS transistor, and the flash memory region 10 includes a storage structure as an example, and the PMOS transistors and the NMOS transistors of the first region 11 and the second region 12 are alternately distributed, and the PMOS transistors and the NMOS transistors are isolated by a shallow trench isolation structure.
Referring to fig. 1, in an embodiment of the present invention, a plurality of shallow trench isolation structures are formed on a substrate 100, specifically, a pad oxide layer 101 is formed on the substrate 100, and the pad oxide layer 101 is made of a material such as dense silicon oxide, and the pad oxide layer 101 may be prepared by a thermal oxidation method, an in situ vapor growth method, or a chemical vapor deposition (Chemical Vapor Deposition, CVD) method, for example. A pad nitride layer 102 is formed on the pad oxide layer 101, and the pad nitride layer 102 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and the pad nitride layer 102 may be formed by chemical vapor deposition or the like. In the process of forming the shallow trench isolation structure, the pad oxide layer 101 can improve the stress between the substrate 100 and the pad oxide layer 101, and can protect the substrate 100 from being damaged by high-energy ions when the well region is formed by ion implantation. A first photoresist layer 103 is formed on the pad nitride layer 102, and a plurality of openings are disposed on the first photoresist layer 103, wherein the openings are used for defining the positions of the shallow trench isolation structures, and the openings expose the pad nitride layer 102.
Referring to fig. 1 to 2, in an embodiment of the invention, after forming the first photoresist layer 103, the first photoresist layer 103 is used as a mask, for example, dry etching is used to etch in the direction of the substrate 100 to form a shallow trench, and the etching gas may be, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), etc. A liner oxide layer (not shown) is formed in the shallow trench, for example, by a thermal oxidation method, so as to repair etching damage in the process of forming the shallow trench and reduce the leakage condition of the semiconductor device. An isolation medium, such as an insulating material, for example, silicon oxide, is deposited within the shallow trench, for example, by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High AspectRatio Process CVD, HARP-CVD). After the isolation medium deposition is completed, the isolation medium and the pad nitride layer 102 are planarized, for example, by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process, to form a shallow trench isolation structure 104, and the shallow trench isolation structure 104 is higher than the pad oxide layer 101 on both sides.
Referring to fig. 2 to 3, in an embodiment of the present invention, after the preparation of the shallow trench isolation structure 104 is completed, ion implantation is performed on the substrate 100 to form different well regions. First, a doped region having a higher concentration than the substrate 100 is implanted with a high implantation energy, i.e. a deep well region 105 is formed in the substrate 100, wherein the deep well region 105 is located at the bottom of the flash memory region 10 and the first region 11 is used to form the bottom of the PMOS for further isolating the different semiconductor devices. And then implanting a doped region having a higher concentration than the substrate 100 to form a plurality of well regions. A low-voltage well region is formed in the second region 12, the low-voltage well region includes a first well region 106 and a second well region 107 which are arranged in parallel, and the depths of the first well region 106 and the second well region 107 are the same as those of the shallow trench isolation structure 104. A high-voltage well region is formed in the first region 11, where the high-voltage well region includes a third well region 108 and a fourth well region 109, and the depths of the third well region 108 and the fourth well region 109 are greater than the depth of the shallow trench isolation structure 104, the depths of the third well region 108 and the fourth well region 109 are equal, and the depth of the third well region 108 is, for example, 1.1 times to 1.2 times the depth of the shallow trench isolation structure 104. A fifth well region 110 is formed in the flash memory region 10, the fifth well region 110 is formed on the deep well region 105, and a doped region 130 is formed on the fifth well region 110 as a heavily doped region of the flash memory cell.
Referring to fig. 3, in an embodiment of the present invention, the first well region 106, the third well region 108 and the fifth well region 110 are doped with the same ion type, such As N-type well, and the doped ions are phosphorus (P), arsenic (As) or aluminum (Al). The doping concentration of the third well region 108 is, for example, 1.2 times to 1.5 times that of the first well region 106, and the ion doping concentrations of the third well region 108 and the fifth well region 110 are equal. The second well region 107 and the fourth well region 109 are the same in ion doping type, for example, P-type well is provided, the doping ions are boron (B) or gallium (Ga) and the like, the doping concentration of the fourth well region 109 is, for example, 1.2 times to 1.5 times the doping concentration of the second well region 107, the doping concentrations of the first well region 106 and the second well region 107 are equal, and the doping concentrations of the third well region 108 and the fourth well region 109 are equal. After the well region is formed, a rapid thermal annealing process (RapidThermal Anneal, RTA) is performed on the substrate 100, and in this embodiment, the annealing temperature is, for example, 1000 ℃ to 1400 ℃, the annealing time is, for example, 1h to 3h, and the annealing process is performed under a protective gas atmosphere, for example, under a nitrogen atmosphere. Through the annealing process, ions in the well region are implanted to a proper depth, and the avalanche breakdown resistance of the semiconductor device is improved.
Referring to fig. 3 to 4, in an embodiment of the invention, after the well region is formed, the pad oxide layer 101 is removed. In this embodiment, for example, wet etching is used to remove the pad oxide layer 101, and wet etching liquid is, for example, hydrofluoric acid, and etching is performed at normal temperature. In other embodiments, other etching methods may be used, and the etching method may be selected according to specific manufacturing requirements. After removing the pad oxide layer 101, a first gate oxide layer 111 is formed on the surface of the well region, and the method for forming the first gate oxide layer 111 is not limited in the present invention, for example, chemical vapor deposition or physical vapor deposition is used. In this embodiment, the first gate oxide layer 111 is formed by, for example, a thermal oxidation method, wherein the first gate oxide layer 111 is, for example, a silicon oxide material, and the thickness of the first gate oxide layer 111 is, for example, 5nm to 15nm. In other embodiments, the material and thickness of the first gate oxide layer 111 may be set according to actual needs. In the process of forming the well region, the pad oxide layer 101 inevitably generates a nicking phenomenon, and by resetting the first gate oxide layer 111, the flatness of the first gate oxide layer 111 is ensured, the defect rate is reduced, and the breakdown and leakage phenomena of the MOS transistor are improved. After the first gate oxide layer 111 is formed, part of the first gate oxide layer 111 in the flash memory region 10 is etched and removed, and the first gate oxide layer 111 in the flash memory region 10 is thinned, so that the thickness of the first gate oxide layer 111 in the flash memory region 10 is, for example, 4 nm-10 nm, the control capability of the flash memory unit is improved, and meanwhile, the breakdown resistance of the high-voltage device on the first region 11 is ensured. In this embodiment, for example, a photoresist layer is formed in other regions, and the first gate oxide layer 111 of the flash memory region 10 is wet etched. In other embodiments, portions of the first gate oxide 111 may be removed in other manners.
Referring to fig. 4, in an embodiment of the present invention, a gate material layer, such as a polysilicon layer or a metal layer, is deposited on the first gate oxide layer 111. In this embodiment, the gate material layer is, for example, a polysilicon layer, and the gate material layer is, for example, formed by Low-pressure chemical vapor deposition (LPCVD) and the thickness of the gate material layer is, for example, 80nm to 120nm, where the polysilicon layer may be doped or undoped, and the doping type may be P-type or N-type. After forming the gate material layer, the gate material layer is etched to remove the gate material layer on the second region 12 and the shallow trench isolation structure 104, and a first gate layer 112 is formed on the well region of the flash memory region 10 and the first region 11.
Referring to fig. 4 to 5, in an embodiment of the invention, after forming the first gate layer 112, an insulating layer 113 is formed on the substrate 100, and the insulating layer 113 covers the surface and the side of the first gate layer 112, the surface of the shallow trench isolation structure 104, and the surface of the first gate oxide layer 111 on the second region 12. In this embodiment, the insulating layer 113 is, for example, a silicon oxide, a silicon nitride or a stacked structure, and in this embodiment, the insulating layer 113 is, for example, a stacked structure of silicon oxide-silicon nitride-silicon oxide, i.e., a silicon oxide layer is formed on the substrate 100, a silicon nitride layer is formed on the silicon oxide layer, and finally a silicon oxide layer is formed on the silicon nitride layer, wherein the silicon oxide and the silicon nitride are formed in a common forming manner. The thickness of the insulating layer 113 is, for example, 10nm to 30nm, wherein the thickness of the plurality of stacked layers in the insulating layer 113 is equal.
Referring to fig. 5 to 7, in an embodiment of the invention, after forming the insulating layer 113, a second photoresist layer 114 is formed on the substrate 100, and the second photoresist layer 114 covers the flash memory region 10 and the first region 11 to remove the insulating layer 113 and the first gate oxide layer 111 on the second region 12. In this embodiment, the insulating layer 113 and the first gate oxide layer 111 are removed by, for example, dry etching, and etching is completed by, for example, step etching. In the first etching to remove the insulating layer 113, the etching gas includes, for example, argon (Ar), oxygen (O) 2 ) Hydrogen (H) 2 ) Nitrogen (N) 2 ) At least one of the insulating layer 113 is etched. The etching time is controlled according to the thickness of the insulating layer, and the removal accuracy of the insulating layer 113 is ensured. Then, when the first gate oxide layer 111 is removed by the second etching, the etching gas is replaced to include, for example, octafluorocyclobutane (C 4 F 8 ) Perfluorobutadiene (C) 4 F 6 ) Difluoromethane (CH) 2 F 2 ) And the like, etching the first gate oxide layer 111, and etching the first gate oxide layer 111 and the substrate 100 with an etching gasThe selection ratio is high to prevent damage to the substrate 100 at the bottom of the first gate oxide layer 111. In this embodiment, etching is performed by inductively coupled plasma (Inductive Coupled Plasma Emission Spectrometer, ICP), for example, and the etching gas includes octafluorocyclobutane and perfluorobutadiene, for example, and hydrogen and nitrogen, for example.
Referring to FIGS. 5-7, in an embodiment of the present invention, during etching, the pressure of the etching chamber is controlled to be 10 mT-60 mT, the Source Power (Source Power) is, for example, 50W-500W, the Bias Power (Bias Power) is, for example, 10W-30W, the gas flow rate of octafluorocyclobutane is, for example, 5 sccm-200 sccm, the gas flow rate of perfluorobutadiene is, for example, 5 sccm-200 sccm, the gas flow rate of hydrogen is, for example, 0 sccm-200 sccm, the gas flow rate of nitrogen is, for example, 0 sccm-50 sccm, the pressure of Back Side Helium is, for example, 8 Torr-20 Torr, and the temperature of the electrostatic chuck is, for example, 40 ℃ to 60 ℃. In the etching process, the pressure of the etching chamber is controlled, the concentration of the plasma for forming etching is low, the longitudinal knocking capability is relatively weakened, the transverse etching is reduced, meanwhile, the mode of relatively large etching selection of silicon oxide and silicon is selected for etching, the damage to a substrate is reduced, side etching generated by wet etching is avoided, the interface integrity between different areas is improved, and the performance of a semiconductor device is improved. Meanwhile, when the insulating layer 113 and the first gate oxide layer 111 are removed, the photoresist which needs to be formed again when the first gate oxide layer 111 is removed is saved through the photomask, drilling caused by wet etching is avoided, and the manufacturing yield of the device is improved.
Referring to fig. 7, in an embodiment of the present invention, after the first gate oxide 111 is removed, a second gate oxide 115 is formed on the second region 12. The thickness of the second gate oxide layer 115 is, for example, 2nm to 7nm, and the thickness of the first gate oxide layer 111 is 1.5 times to 2.5 times that of the second gate oxide layer 115, and the second gate oxide layer 115 is formed by, for example, chemical vapor deposition or physical vapor deposition. In this embodiment, the second gate oxide layer 115 is formed, for example, by an In-situ vapor growth method (In-Situ Steam Generation, ISSG), wherein the second gate oxide layer 115 is, for example, a silicon oxide material, and the silicon oxide formed by the ISSG has a higher quality and fewer defects, so as to improve the stability of the transistor on the second region 12. In other embodiments, the material and thickness of the second gate oxide layer 115 may be set according to actual needs.
Referring to fig. 7 to 8, in an embodiment of the present invention, after forming the second gate oxide layer 115, a second gate layer 116 is deposited on the substrate 100, where the second gate layer 116 is, for example, a polysilicon layer or a metal layer. In this embodiment, the second gate layer 116 is, for example, a polysilicon layer, and the thickness of the second gate layer 116 is, for example, 180nm to 220nm, wherein the polysilicon layer may be selectively doped or undoped, and the doping type may be P-type or N-type. And the second gate layer 116 covers the entire upper layer of the substrate, and the second gate layer 116 is formed, for example, by low pressure chemical vapor deposition or the like.
Referring to fig. 8to 10, in an embodiment of the present invention, after the second gate layer 116 is formed, a third photoresist layer 117 is formed on the second gate layer 116, and the third photoresist layer 117 is used to define the gate positions of the flash memory region 10 and the devices on the first region 11. The second gate layer 116, the insulating layer 113 and the first gate layer 112 are etched using the third photoresist layer 117 as a mask, to form a plurality of gate structures. The gate structure includes a first gate structure including a high voltage gate and a flash memory gate disposed on the first region 11 and the flash memory region 10, wherein the high voltage gate includes a first high voltage gate 118 and a second high voltage gate 119 to form gates of different types of devices, and the flash memory gate includes a select gate 120 and a plurality of cell gates 121 to constitute a select transistor and a cell transistor for forming the flash memory structure. In this embodiment, the insulating layer 113 is disposed in the high voltage gate and the flash memory gate to form a split gate, i.e. the first gate layer 112 in the gate is used as a floating gate for storing data, and the second gate layer 116 is used as a control gate, so that the performance of the semiconductor device is improved by adjusting the gate structure.
Referring to fig. 9 to 11, in an embodiment of the invention, after the formation of the gate electrodes on the flash memory region 10 and the first region 11, the third photoresist layer 117 is removed, and a new photoresist layer, i.e., the fourth photoresist layer 122, is formed on the substrate 100. The fourth photoresist layer 122 is used to define the gate position of the device on the second region 12, and the second gate layer 116 is etched with the fourth photoresist layer 122 as a mask to form a plurality of gate structures. The gate structure includes a second gate structure, which is a low voltage gate, wherein the low voltage gate includes a first low voltage gate 123 and a second low voltage gate 124 to form gates of different types of devices. Different gate structures are formed by etching the gate layers in different areas, so that the integrity of the gate structures is ensured, and the over-etching phenomenon is reduced.
Referring to fig. 11 to 12, in an embodiment of the invention, after forming the gate structure, sidewall structures 125 are formed on both sides of the gate structure. For simplicity of the picture, the corresponding sidewall structures 125 are not drawn on both sides of the flash gate on the flash memory region 10. Specifically, after the gate structure is formed, a sidewall dielectric layer is formed on the gate structure, each well region and the shallow trench isolation structure 104, where the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After the sidewall dielectric layer is formed, for example, the gate structure, the shallow trench isolation structure 104 and the sidewall dielectric layer on a part of the well region can be removed by using an etching process such as photolithography, so that the sidewall dielectric layers on two sides of the gate structure are reserved. The side wall dielectric layer is used for defining the side wall structure 125, the height of the side wall structure 125 is consistent with that of the grid structure, the width of the side wall structure 125 is gradually increased from the top to the bottom of the grid structure, and the insulating side wall structure 125 is arranged to prevent the prepared transistor from generating electric leakage. In this embodiment, the shape of the sidewall structure 125 is, for example, arc, and in other embodiments, the shape of the sidewall structure 125 may also be triangular or L-shaped.
Referring to fig. 12, in an embodiment of the present invention, after forming the sidewall structure 125, heavy doping is performed in the first region 11 and the second region 12 to form a source and a drain of the transistor. The first high voltage gate 118 is heavily doped on both sides to form a first high voltage heavily doped region 131 to serve as the source and drain of the first high voltage transistor. The second high voltage gate 119 is heavily doped on both sides to form a second high voltage heavily doped region 132 to serve as the source and drain of the second high voltage transistor. The first low voltage gate electrode 123 is heavily doped on both sides to form a first low voltage heavily doped region 133 serving as the source and drain of the first low voltage transistor. The second low voltage gate 124 is heavily doped on both sides to form a second low voltage heavily doped region 134 which serves as the source and drain of the second low voltage transistor. In this embodiment, the doping types of the first high-voltage heavily doped region 131 and the first low-voltage heavily doped region 133 are the same, for example, P-type doping is performed, the doping ions are boron (B) or gallium (Ga), and the doping concentration of the first high-voltage heavily doped region 131 is, for example, 1.2 times to 1.5 times that of the first low-voltage heavily doped region 133. The doping types of the second high-voltage heavily doped region 132 and the second low-voltage heavily doped region 134 are the same, for example, N-type doping is performed, the doping ions are phosphorus (P), arsenic (As), aluminum (Al), or the like, the doping concentration of the second high-voltage heavily doped region 132 is, for example, 1.2 times to 1.5 times that of the second low-voltage heavily doped region 134, the doping concentrations of the first high-voltage heavily doped region 131 and the second high-voltage heavily doped region 132 are equal, and the doping concentrations of the first low-voltage heavily doped region 133 and the second low-voltage heavily doped region 134 are equal. By forming the heavily doped region, a plurality of different semiconductor devices are formed on the substrate 100, and the manufacturing efficiency of the semiconductor devices is improved.
In summary, according to the semiconductor integrated device and the manufacturing method thereof provided by the invention, after the insulating layer is formed, the insulating layer in the low-voltage region is removed by dry etching, so that the drilling phenomenon between different regions can be reduced, and the electrical performance of the semiconductor integrated device can be improved. And the insulating layer and the first grid oxide layer are removed through a photomask, different etching gases are selected, damage to the substrate is reduced, interface integrity between different areas is improved, and performance of the semiconductor device is improved. Meanwhile, the manufacturing process is simplified, and the cost is reduced. And the production efficiency of the semiconductor device can be improved, and the production cost can be reduced. In summary, the present invention provides a semiconductor integrated device and a method for manufacturing the same, which can improve the performance of the semiconductor integrated device and the manufacturing yield.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. A method of fabricating a semiconductor integrated device, comprising at least the steps of:
providing a substrate, wherein the substrate comprises a flash memory area, a first area and a second area;
forming a plurality of well regions in the substrate, wherein the well regions comprise a low-voltage well region and a high-voltage well region, the low-voltage well region is arranged in the substrate on the second region, the high-voltage well region is arranged in the substrate on the first region, and the depth of the low-voltage well region is smaller than that of the high-voltage well region;
forming a gate oxide layer on the well region;
forming a first gate structure on the flash memory region and the gate oxide layer on the first region, wherein the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer;
forming a second gate structure on the gate oxide layer on the second region, wherein the second gate structure comprises the second gate layer; and
forming a heavy doping region in the well region at two sides of the first gate structure and the second gate structure, wherein the heavy doping region comprises a high-voltage heavy doping region and a low-voltage heavy doping region, and the doping concentration of the high-voltage heavy doping region is 1.2-1.5 times of that of the low-voltage heavy doping region;
the manufacturing method further comprises the following steps:
forming a first gate oxide layer on the well region;
forming a first gate layer on the first gate oxide layer, the first gate layer covering the flash memory region and the well region on the first region;
forming the insulating layer on the first gate layer and the second region;
forming a photoresist layer on the flash memory region and the first region, an
Etching the insulating layer and the first gate oxide layer on the second region by taking the photoresist layer as a mask;
the etching includes dry etching, and the dry etching includes the steps of:
etching the insulating layer on the second region, wherein etching gas comprises at least one of argon, oxygen, hydrogen and nitrogen;
etching the first gate oxide layer, wherein the etching gas comprises at least one of octafluorocyclobutane, perfluorobutadiene and difluoromethane;
the dry etching is performed through inductively coupled plasma, the pressure of an etching chamber is 10 mT-60 mT, the source power is 50W-500W, and the bias power is 10W-30W.
2. The method for manufacturing a semiconductor integrated device according to claim 1, wherein the insulating layer is one of an oxide layer, a nitride layer, and a stack of the oxide layer and the nitride layer.
3. The method of manufacturing a semiconductor integrated device according to claim 1, wherein the gate oxide layer includes a first gate oxide layer, the first gate oxide layer being provided over the first region.
4. The method of manufacturing a semiconductor integrated device according to claim 3, wherein the gate oxide layer includes a second gate oxide layer, wherein the second gate oxide layer is disposed on the second region, and wherein a thickness of the first gate oxide layer is 1.5 times to 2.5 times a thickness of the second gate oxide layer.
5. The method according to claim 1, wherein the well region includes a high-voltage well region, wherein the high-voltage well region is provided in the substrate over the first region, and wherein a doping concentration of the high-voltage well region is 1.2 times to 1.5 times a doping concentration of the low-voltage well region.
6. The method for manufacturing the semiconductor integrated device according to claim 1, wherein the manufacturing method comprises:
etching to remove the first gate oxide layer, and forming a second gate oxide layer on the second region; and
and forming a second gate layer on the insulating layer and the second gate oxide layer.
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| KR100669103B1 (en) * | 2005-06-28 | 2007-01-15 | 삼성전자주식회사 | Method of manufacturing a flash memory device |
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