JP2007311409A - Semiconductor device, and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the height of a gate electrode is equal at the memory cell and the peripheral logic part, and to provide its fabrication process. <P>SOLUTION: A semiconductor device comprises a memory device and a logic device wherein the memory device comprises a first gate electrode having a first conductor film formed on a semiconductor substrate through a first gate insulating film, and a second conductor film formed on the first conductor film through an inter-electrode insulating film. The logic device comprises a second gate electrode formed on the semiconductor substrate through a second gate insulating film. The second gate electrode includes a third conductor film formed on the second conductor film, and has a height equivalent to that of the first gate electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In a hybrid semiconductor device including a memory circuit and a peripheral logic circuit, in particular, in a hybrid semiconductor device including a nonvolatile memory having a two-layer gate electrode structure, the height of the gate electrode in the memory cell portion and the peripheral logic portion is reduced. The difference has become a problem when the semiconductor device is further miniaturized.

  A conventional hybrid semiconductor device is disclosed in Patent Document 1, for example. The gate electrode of the nonvolatile memory cell portion of this semiconductor device has a two-layer gate structure of a floating gate electrode and a control gate electrode. On the other hand, the gate electrode of the peripheral logic portion has a single-layer gate structure and is lower than the memory cell portion. As described above, in the semiconductor device in which the height of the gate electrode is different between the memory cell portion and the peripheral logic portion, a problem occurs in a manufacturing process such as lithography and CMP (chemical mechanical polishing). As an example, in the lithography process, for example, there are problems such as uneven application of resist film thickness, defocusing due to a step, and the necessity of performing lithography processing separately for each region.

A semiconductor device in which a step difference of the gate electrode is eliminated is disclosed in Patent Document 2. In this semiconductor device, a gate electrode structure similar to a memory cell of a flash memory is used for a gate electrode of a peripheral logic portion. In this device, the same electrode layer as the floating gate electrode and the control gate electrode of the memory cell of the flash memory is connected to form the gate electrode of the peripheral logic portion. Since the electrode layer for forming the floating gate electrode is used as the gate electrode of the peripheral logic portion, it is necessary to add impurities, form a contact with the control gate electrode, and process the gate electrode. For this reason, there is a problem that the manufacturing process becomes complicated or difficult. Furthermore, since impurities that can be doped into the electrode layer are limited to n-type, for example, it is difficult to improve the performance of the p-channel transistor.
JP-A-8-306888 JP 2002-176114 A

  The present invention provides a semiconductor device having the same gate electrode height in a memory cell portion and a peripheral logic portion, and a method for manufacturing the same.

  A semiconductor device according to an aspect of the present invention is a semiconductor device including a memory device and a logic device, and the memory device is formed through a first gate insulating film formed over a semiconductor substrate. A first gate electrode comprising a first conductive film and a second conductive film formed on the first conductive film via an interelectrode insulating film; A second gate electrode formed through a second insulating film formed on the semiconductor substrate is provided, and the second gate electrode is a third conductor formed on the second conductive film. It includes a film and has a height equivalent to that of the first gate electrode.

  A method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a memory cell region and a logic region on a semiconductor substrate, and a first conductor on the semiconductor substrate via a first gate insulating film. A step of depositing a film, a step of patterning the first conductor film into a strip shape, a step of forming an interelectrode insulating film on the first conductor film, and the interelectrode insulation in the logic region. Removing the film, the first conductor film, and the first gate insulating film; forming a second gate insulating film on the semiconductor substrate in the logic region; and forming a second gate insulating film on the entire surface above the semiconductor substrate. A step of depositing a second conductor film, a step of depositing a third conductor film on the second conductor film, and removing and flattening at least the third conductor film in the memory cell region And a memory in the memory cell region Comprising forming a Rugate electrode Oyobi the logic region by patterning the gate electrode of the transistor, and forming a source / drain in the semiconductor substrate using the gate electrode as a mask of the memory cell gate electrode and the transistor.

  According to the present invention, there are provided a semiconductor device having the same gate electrode height in the memory cell portion and the peripheral logic portion, and a manufacturing method thereof.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the figure, corresponding parts are indicated by corresponding reference numerals. The following embodiment is shown as an example, and various modifications can be made without departing from the spirit of the present invention.

  According to the embodiment of the present invention, the semiconductor device includes a memory cell unit and a peripheral logic unit, and the gate electrode of the transistor in the peripheral logic unit has a height substantially equal to the gate electrode of the memory cell unit. Here, the memory cell unit includes a nonvolatile memory device such as a flash memory, for example, and has an electrode structure of at least two layers.

  An example of a planar layout of a semiconductor device 100 according to an embodiment of the present invention is shown in FIG. The semiconductor device 100 includes a memory cell unit (MC) including a flash memory, and a peripheral logic unit (LG) including a high breakdown voltage transistor unit (HV) and a low breakdown voltage transistor unit (LV). The high breakdown voltage transistor portion (HV) is disposed so as to surround the memory cell portion (MC), and supplies a high voltage necessary for the operation of the flash memory to the memory cell portion (MC). The low withstand voltage transistor portion (LV) executes a logical operation or the like, and is preferably composed of a CMOS. The gate electrodes of the memory cell part (MC) and the peripheral logic part (LG) are formed at substantially the same height. Here, it is particularly important that the height of the gate electrode of the memory cell portion (MC) and the gate electrode of the high voltage transistor portion (HV) adjacent to and surrounding the gate electrode are substantially equal.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention includes a semiconductor device in which a conductor film is added to the peripheral logic portion so that the height of the gate electrode of the peripheral logic portion is substantially equal to the height of the gate electrode of the memory cell portion. It is the manufacturing method.

  An example of the cross-sectional structure of the gate electrode of the semiconductor device 100 of this embodiment is shown in FIG. In the figure, MC represents a memory cell region, LG represents a peripheral logic region, HV represents a high breakdown voltage transistor region, and LV represents a low breakdown voltage transistor region. Subscripts p and n of the low breakdown voltage transistor region represent a p-channel region and an n-channel region, respectively. The peripheral logic region (LG) includes both a high breakdown voltage transistor region (HV) and a low breakdown voltage transistor region (LV).

  In the illustrated example of the semiconductor device 100 of the present embodiment, the gate electrode GEm of the memory cell in the memory cell region (MC) is formed from the floating gate electrode made of the first conductive film 14 and the second conductive film 22. The gate electrodes (GEh, GEl-n, GEl-p) of the transistors in the peripheral logic region (LG) having the same thickness as the first conductive film 14 are included. A film 24 and a second conductive film 22 are included. By forming the respective gate electrodes in this way, the gate electrodes in both regions are formed at substantially the same height.

  An example of the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the process cross-sectional view shown in FIG.

  Although not shown, first, wells and element isolations forming the memory cell region (MC) and the peripheral logic region (LG) are formed on the semiconductor substrate 10, for example, a silicon substrate. The element isolation can be formed by, for example, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon).

Referring to FIG. 3A, a first gate insulating film 12, for example, a silicon oxide film (SiO ₂ film) is formed on the entire surface of the semiconductor substrate 10 by thermal oxidation. The first gate insulating film 12 functions as a gate insulating film (tunnel insulating film) of the flash memory. A first conductive film 14 is deposited on the first gate insulating film 12. As the first conductive film 14, for example, a polysilicon film formed by CVD (Chemical Vapor Deposition) can be used, which is later patterned into a floating gate electrode. The thickness of the first conductive film 14 is 60 nm, for example. The first conductive film 14 is doped with an n-type impurity such as phosphorus (P).

Next, the first conductive film 14 in the memory cell region (MC) is patterned into a strip shape. The strip-shaped pattern is formed long in a direction parallel to the paper surface of FIG. Thereafter, an interelectrode insulating film 16 is deposited on the entire surface. As the interelectrode insulating film 16, for example, an ONO film in which a SiO ₂ film / silicon nitride film (Si ₃ N ₄ film) / SiO ₂ film having a thickness of 15 nm is laminated can be used. The interelectrode insulating film 16 is formed not only on the upper surface of the patterned first conductive film 14 but also on the side surface.

Referring to FIG. 3B, the interelectrode insulating film 16, the first conductive film 14, and the first gate insulating film in the peripheral logic region (LG) are removed. A second gate insulating film 18 is formed in the high breakdown voltage transistor region (HV), and a third gate insulating film 20 is formed in the low breakdown voltage transistor region (LV). The second and third gate insulating films are, for example, SiO ₂ films having a thickness of 18 nm and 3 nm, respectively.

  Next, a second conductive film 22 is deposited on the entire surface of the inter-electrode insulating film 16 in the memory cell region (MC) and the second and third gate insulating films 18 and 20 in the peripheral logic region (LG). . As the second conductive film 22, for example, a polysilicon film deposited by CVD can be used as in the case of the first conductive film 14. In the second conductive film 22 of the memory cell region (MC), the high breakdown voltage transistor region (HV), and the n-channel low breakdown voltage transistor region (LV-n), n-type impurities such as phosphorus (P), arsenic ( As) is doped, and the second conductive film 22p in the p-channel low breakdown voltage transistor region (LV-p) is doped with a p-type impurity, for example, boron (B).

  After the second conductive film 22 is deposited, as shown in FIG. 3B, the first conductive film is substantially between the memory cell region (MC) and the peripheral logic region (LG). There is a step corresponding to a thickness of 14.

  Therefore, as shown in FIG. 3C, the third conductive film 24 having the same thickness as that of the first conductive film 14 is formed only in the peripheral logic region (LG). The step is substantially flattened. Specifically, the third conductive film 24 is deposited on the entire surface. As the third conductive film 24, a polysilicon film deposited by CVD, for example, can be used in the same manner as the first and second conductive films 14 and 22. The third conductive film 24 in the memory cell region (MC) is selectively removed. The third conductive film 24 is also doped with the same n-type or p-type impurity as the second conductive film.

  In this manner, the heights of the conductive films stacked in the memory cell region (MC) and the peripheral logic region (LG) can be made substantially the same. In particular, it is possible to eliminate a step between the memory cell region (MC) and the high-breakdown-voltage transistor region (HV) adjacent to the periphery, which is important in the next lithography process. Strictly speaking, there is a difference in film thickness difference (about 15 nm) between the second gate insulating film 18 and the third gate insulating film 20 between the high breakdown voltage transistor region (HV) and the low breakdown voltage transistor region (LV). However, there is no problem in the manufacturing process if the level difference is this level.

  Thereafter, the gate electrodes GEm, GEh, and GEl are patterned by lithography and etching. In this patterning, since there is no step between the memory cell region (MC) and the adjacent high voltage transistor region (HV), a resist film having a uniform thickness as a whole can be formed. Therefore, fine and uniform patterning is possible inside the memory cell region (MC). Conventionally, since there is a step between the memory cell region (MC) and the high breakdown voltage transistor region (HV), the resist film is thickened around the memory cell region (MC), and the difference is made within the memory cell region (MC). Patterning with various dimensions could not be performed. The memory cell portion thus formed, that is, the gate electrode GEm of the flash memory, includes the first gate insulating film 12, the floating gate electrode 14 made of the first conductive film, the interelectrode insulating film 16, and the second gate electrode GEm. The control gate electrode 22 is formed of the conductive film 16. The gate electrode GEh of the high breakdown voltage transistor is composed of the second gate insulating film 18 and the second and third conductive films. The gate electrode GE1 of the low breakdown voltage transistor is composed of the third gate insulating film 20 and the second and third conductive films. Since the first conductive film and the third conductive film have substantially the same thickness, all the gate electrodes GE are formed at substantially the same height.

  Next, a sidewall insulating film 26 is formed on each gate electrode GE. Then, for example, arsenic (As) or boron (B) is doped, for example, by ion implantation into the semiconductor substrate 10 using the gate electrodes GEm, GEh, GE1, and the sidewall insulating film 26 as a mask, and each source / drain 28m. , 28h, 28l-n, 28l-p. In this way, the gate electrode structure of the semiconductor device 100 of this embodiment shown in FIG. 2 can be formed.

  Furthermore, the semiconductor device 100 of the present embodiment can be completed by performing processes necessary for the semiconductor device such as multilayer wiring.

  As described above, according to the present embodiment, the semiconductor memory device in which the height of the gate electrode GE is formed to be substantially the same in the memory cell region (MC) and the peripheral logic region (LG) is mixedly mounted. A semiconductor device and a manufacturing method thereof are realized. By forming the gate electrodes at the same height, in particular, patterning in the lithography process becomes easy, and the processing margin can be set to a small value. Furthermore, it is possible to simultaneously perform processing such as patterning, which has been performed for each region having a different height, and to simplify the manufacturing process.

  Therefore, according to the present embodiment, a semiconductor device and a method for manufacturing the same that can secure a margin for process processing and simplify a manufacturing process while maintaining high speed of peripheral transistors are provided.

(Second Embodiment)
In the second embodiment of the present invention, a plurality of gate electrode structures having different heights are planarized using a planarization process in order to form gate electrodes having substantially the same height in the memory cell region and the peripheral logic region. And a method of manufacturing the same.

  As an example, the gate electrode structure of the semiconductor device 200 according to the present embodiment is such that the gate electrodes GEh and GEl in the peripheral logic region (LG) have the same height as the gate electrode GEm in the memory cell region (MC) as shown in FIG. A third conductive film is formed in the peripheral logic region (LG) so as to be equal to. The third conductive film 24 can be first deposited thick and planarized by a planarization process such as CMP or etchback.

  Next, an example of a method for manufacturing the semiconductor device 200 of this embodiment will be briefly described with reference to FIG.

  The process up to the deposition of the third conductive film 24 is substantially the same as that of the first embodiment, and thus the description thereof is omitted. The difference is that the third conductive film 24 is deposited thicker than in the first embodiment, as shown in FIG. That is, the surface of the third conductive film 24 immediately after deposition in the high breakdown voltage transistor region (HV) and the low breakdown voltage transistor region (LV) is higher than the surface of the second conductive film 22 in the memory cell region (MC). It will be higher than that.

  After that, as shown in FIG. 5B, the third conductive film 24 is planarized to the height of the surface of the second conductive film 22 in the memory cell region (MC), for example, CMP, etch back. To remove and planarize. That is, the thickness of the third conductive film 24 is adjusted so that the heights of the gate electrodes are equal between the regions. In this way, the step between the memory cell region (MC) and the peripheral logic region (LG) can be eliminated.

  Then, the gate electrodes GEm, GEh, and GE1 are patterned by lithography and etching. During this patterning, as in the first embodiment, there is no step between the memory cell region (MC) and the high voltage transistor region (HV) adjacent to the memory cell region (MC). Then, fine and uniform patterning becomes possible. The gate electrode GEm of the formed flash memory of the memory cell portion includes the first gate insulating film 12, the floating gate electrode 14 made of the first conductive film, the interelectrode insulating film 16, and the second conductive film 16. Is formed so as to include a control gate electrode 22 made of The gate electrode GEh of the high breakdown voltage transistor is composed of the second gate insulating film 18, the second conductive film, and the third conductive films 22 and 24. The gate electrode GE1 of the low breakdown voltage transistor is composed of the third gate insulating film 20 and the second and third conductive films 22 and 24. In this way, all the gate electrodes GEm, GEh, GEl are formed at the same height.

  Further, the gate insulating film 26 of the gate electrode GE is formed, the source / drains 28m, 28h, 28l-n, and 28l-p are formed, etc., and the gate of the semiconductor device 200 of the present embodiment shown in FIG. An electrode structure can be formed.

  Thereafter, a process necessary for the semiconductor device such as multilayer wiring is performed to complete the semiconductor device of this embodiment.

  As described above, according to the present embodiment, the semiconductor memory device in which the height of the gate electrode GE is formed to be substantially the same in the memory cell region (MC) and the peripheral logic region (LG) is mixedly mounted. A semiconductor device and a manufacturing method thereof can be provided.

  Therefore, similarly to the first embodiment, according to the present embodiment, it is possible to secure a margin for process processing and simplify the manufacturing process while maintaining the high speed of the peripheral transistors.

  In the above embodiment, the gate electrodes are formed so as to have substantially the same height in all regions of the semiconductor device. However, the height of the gate electrode GEh of the high breakdown voltage transistor region (HV) that is disposed adjacent to and surrounds at least the memory cell region (MC) that requires the finest processing is defined as the gate electrode GEm of the memory cell region (MC). By forming them substantially equal, it is possible to prevent the processing accuracy of the memory cell region (MC) from being lowered.

  In the above embodiment, the semiconductor device in which the semiconductor memory device is mixed is described by taking the flash memory as an example. However, the semiconductor memory device is not limited to the flash memory, and the semiconductor memory having a two-layer gate electrode structure. It can also be applied to a device, for example an EEPROM.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, and can be applied to other embodiments without departing from the spirit of the present invention and can be applied to a wide range. It is.

FIG. 1 is an example of a plan layout diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a cross-sectional structure of the gate electrode of the semiconductor device according to the first embodiment of the present invention. 3A to 3C are process cross-sectional views shown for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram showing an example of a cross-sectional structure of the gate electrode of the semiconductor device according to the second embodiment of the present invention. FIGS. 5A and 5B are process cross-sectional views shown to describe an example of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

Explanation of symbols

  MC ... Memory cell region, LG ... Peripheral logic region, HV ... High breakdown voltage transistor region, LV ... Low breakdown voltage transistor region, GE ... Gate electrode, 10 ... Semiconductor substrate, 12, 18, 20 ... Gate insulation film, 14, 22, 24 ... conductor film, 16 ... interelectrode insulating film, 26 ... sidewall insulating film, 28 ... source / drain, 100,200 ... semiconductor device.

Claims (5)

A semiconductor device comprising a memory device and a logic device,
The memory device includes:
A first conductor film formed via a first gate insulating film formed on a semiconductor substrate;
A first gate electrode comprising a second conductor film formed on the first conductor film via an interelectrode insulating film;
The logic device is:
Comprising a second gate electrode formed through a second insulating film formed on the semiconductor substrate;
The semiconductor device, wherein the second gate electrode includes a third conductor film formed on the second conductive film, and has a height equivalent to that of the first gate electrode.   The semiconductor device according to claim 1, wherein the memory device is a flash memory.   The semiconductor device according to claim 1, wherein the logic device is arranged so as to surround a periphery of the memory device.   The semiconductor device according to claim 1, wherein the logic device includes a high breakdown voltage transistor and a low breakdown voltage transistor. Forming a memory cell region and a logic region on a semiconductor substrate;
Depositing a first conductor film on the semiconductor substrate via a first gate insulating film;
Patterning the first conductor film into a strip shape;
Forming an interelectrode insulating film on the first conductor film;
Removing the interelectrode insulating film, the first conductor film and the first gate insulating film in the logic region;
Forming a second gate insulating film on the semiconductor substrate in the logic region;
Depositing a second conductor film on the entire surface above the semiconductor substrate;
Depositing a third conductor film on the second conductor film;
Removing and flattening at least the third conductor film in the memory cell region;
Forming a memory cell gate electrode in the memory cell region and a gate electrode of a transistor in the logic region by patterning;
Forming a source / drain on the semiconductor substrate using the memory cell gate electrode and the gate electrode of the transistor as a mask.

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