CN106796937A - Semiconductor device and electrostatic discharge protective equipment including diode - Google Patents

Semiconductor device and electrostatic discharge protective equipment including diode Download PDF

Info

Publication number
CN106796937A
CN106796937A CN201580050455.7A CN201580050455A CN106796937A CN 106796937 A CN106796937 A CN 106796937A CN 201580050455 A CN201580050455 A CN 201580050455A CN 106796937 A CN106796937 A CN 106796937A
Authority
CN
China
Prior art keywords
diode
hole
groove
width
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580050455.7A
Other languages
Chinese (zh)
Inventor
吉莱斯·弗鲁
尼库拉斯·诺赫利厄
伯特兰德·考里沃德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of CN106796937A publication Critical patent/CN106796937A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66106—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission

Abstract

The present invention relates to a kind of semiconductor device, it is included at least two holes (18 with respective width and depth implemented in substrate (6), 20), and form a kind of diode (4), wherein, substrate (6) is with the doping type for determining, and, wherein, adulterate the inwall in each hole (18,20), makes its doping type different from substrate (6) doping, the width and/or depth of one hole (18,20) are different from the width and/or depth of adjacent holes.

Description

Semiconductor device and electrostatic discharge protective equipment including diode
Technical field
The present invention relates to include a kind of semiconductor device of diode, more specifically, it is related to a kind of static discharge (ESD) protection device.
Background technology
In recent years, light emitting diode (LED) is integrated be in the such application of such as signaling or home lighting in it is main Problem.It is indeed desired to use LED in illumination applications in several years, more specifically, conventional lamp is replaced with high-brightness LED.
Generally, with the high brightness of the developing material based on InGaN (indium gallium) generated on the sapphire substrate LED, the sapphire substrate is insulating materials.The use of this substrate causes high-brightness LED to the high sensitive of static discharge.
Static discharge and electrostatic damage can occur to any point of Site Service from production.Because not receiving In the environment of control by inappropriate ESD control measure operation device caused by.For example, forward bias esd pulse is without damage LED is passed through in the case of evil, but reverse biased esd pulse can but produce catastrophe failure.
(mil-std-1686c) is controlled according to military standard static discharge, it is generally recognized that InGaN LED dies are " 1 grades " Device.It is considered as " 1 grade " that part needs to test the bias and 130 volts of voltage that bear 20 volts by manikin.For Avoid because the integrity problem that produces of esd discharge, LED manufacturer there are many electronic installations available.Most popular It is ceramic capacitor, Zener diode, transient voltage suppression (TVS) diode and Schottky diode.
In these devices, all over the world the widely used Zener diode of design engineer, because its low cost of manufacture. And, Zener diode is than ceramic capacitor efficiency high, because their protection to overshoot voltage are stronger.Additionally, the Zener Diode also has clamper ratio (ratio between Pulse clamp voltage and DC breakdown voltages) higher, and ESD radiatings are relatively slow, Thereby increase clamp voltage level.
Zener diode parallel to the correct setting of LED reverse bias enables voltage peak to be passed through according to both direction Circuit, without damaging LED.Capacitor be added to smooth input signal be prevent electrostatic overload one of (EOS) failure it is appropriate Corrective measure.Therefore, generally using and the Zener diode parallel to LED reverse bias on ceramic monolith, so that obtain can The lighting source for leaning on.
Some LED manufacturers prefer back-to-back formula Zener diode to be protected for ESD, so as to obtain symmetrical dress Put, and on the substrate with Zener diode assembling after, the leakage current of LED can be measured.The shortcoming of this solution It is the increase in the complexity and cost of LED component.In highly competititve environment, it is necessary to which the price for reducing LED is one and asks Topic.So it is very high to be applied to pressure in the price of ESD diode protection.
In order to reduce the price of ESD protections, Zener diode must be less and less, while keeping ESD robustness constant.For Overcome this problem, US 2007/0145411 proposes a kind of method for manufacturing slot type polysilicon diode.The method is included in N- (P-) type epitaxial regions are constituted on upper N+ (P+) type substrate and groove is constituted in N- (P-) type epitaxial region.The method is entered One step includes forming insulating barrier in the trench and fills groove with polysilicon, and the polysilicon constitutes the top surface of groove.The party Method further includes to constitute P+ (N+) type DOPOS doped polycrystalline silicon region and N+ (P+) type DOPOS doped polycrystalline silicon region in the trench, and Diode is constituted in the trench, and in the trench, a part of diode is less than groove top surface.By better profiting from 1mm2It is interior Available silicon chip completes the structure.The advantage of trench diodes is the whole volume for utilizing silicon, and huge P/N knots are presented Point area.
The content of the invention
It is an object of the invention to provide an alternative solution for increasing electric current maintenance in diode.Another mesh of the invention Be be used in ESD protection bi-directional zener diode miniaturization.The structure for being proposed is advantageously used for LED protections or uses In other unit protections.
According to the first aspect of the invention, a kind of semiconductor device is proposed, the semiconductor device includes implementing in a substrate At least two holes with respective width and depth, and form a kind of diode：
Wherein, substrate has the doping type for determining, and
Wherein, adulterate the inwall in each hole, makes its doping type different from substrate doping,
Characterized in that, the width and/or depth in hole are different from the width and/or depth of adjacent holes.
This new construction of diode enables to increase the electric current for being driven into diode.Observed according to inventor, by two The electric current that pole pipe drives is not as (identical) hole of diode or the quantity of post are linearly increasing.Experiment shows that current convergence exists In first few lines hole (or post).So, increasing the size of the diode of prior art does not substantially increase the ESD robustness of device. The new construction of the diode for herein proposing enables in the structure preferably redistribution current, and therefore in the increase of its size In the case of increase by diode drive electric current.
In one embodiment, each hole is circular port, and the width in each hole is corresponding with its diameter, makes The size and dimension that can control diode.
In another exemplary embodiment for the diode for being proposed, diode includes at least two row holes, and often row hole is all Parallel to another row hole；Width with a line hole is identical with depth, and hole depth and/or width according to from a line Kong Xiangxiang The direction in adjacent rows hole increases.So, the distribution of electric current line is controlled in diode.
In the preferred embodiment of the diode for being proposed, each hole is the ditch that can reduce diode leakage electric current Groove.
Advantageously, each groove is parallel to other grooves, and groove depth and/or width according to from a ditch Groove increases to the direction of adjacent trenches.Therefore, the electric current in control diode enables to reduce overheat.
The length that groove is presented advantageously increases according to from a groove to the direction of adjacent trenches.So, increased guarantor Hold electric current in the diode.
Advantageously, the hole of the diode that coupled in parallel is proposed, to make electric current line distribute in the substrate of diode, And enable monopole ESD protections.
The invention further relates to a kind of static discharge device, including two diodes as described above.This device can Optimization ESD protections.
In the exemplary embodiment of the static discharge device, each diode includes multirow hole, and second two The multirow hole of pole pipe is parallel to first multirow hole of diode.Therefore, the integrated of diode is optimized.
In a preferred embodiment, each diode include groove, and second groove of diode parallel to First groove of diode.
In order to realize that bi-directional ESD is protected, first diode and second diode are coupled with back-to-back position.
In one exemplary embodiment, static discharge device includes at least two semiconductor devices being stacked, Enable to optimize the integrated of diode.
In one exemplary embodiment, static discharge device is couple to active electron component and/or passive electronic components, To carry out effective ESD protections.
Brief description of the drawings
In each figure of accompanying drawing by way of example, and unrestricted mode illustrates embodiments of the invention, each Reference number same in figure refers to similar element, in the various figures：
Fig. 1 is the schematic cross-section of the diode according to several embodiments,
Fig. 2 is the schematic cross-section of the method and step of the diode for manufacturing Fig. 1,
Fig. 3 is the schematic cross-section of another method and step of the diode for manufacturing Fig. 1,
Fig. 4 is the fragmentary isometric view on diode one embodiment corresponding with Fig. 3,
Fig. 5 be it is corresponding with Fig. 3 on second fragmentary isometric view of embodiment,
Fig. 6 be it is corresponding with Fig. 3 on the 3rd fragmentary isometric view of embodiment,
Fig. 7 is the schematic isometric view for constituting the groove of diode,
Fig. 8 is the sectional view of another method and step of the diode for manufacturing Fig. 1,
Fig. 9 is a sectional view for alternative embodiment of the diode of Fig. 1,
Figure 10 is two isometric views of diode that back-to-back position is according to Fig. 9,
Figure 11 shows the trial curve according to the diode of Figure 10 and the diode of prior art,
Figure 12 is coupled to the cross-view of the diode of Figure 11 of circuit, and
Figure 13 is the equivalent circuit of structure shown in Figure 12.
Specific embodiment
Fig. 1 shows the schematic cross-section of integrated diode 4 in semiconductor devices.The base as such as silicon substrate Implement diode 4 on plate 6.In this manual, it is assumed that substrate 6 is to obtain P-type doped substrate with determination doping values.Additionally, adopting The leakage of current of diode 4 is reduced with feature of being adulterated as such as bearer type and carrier lumped values.Must be carefully selected The doping level of substrate 6, because the breakdown voltage for diode being determined by its.Carrier lumped values can (property purpose merely to illustrate, And non-limiting purpose) it is equal to 1 × 1018cm-3.The all other value listed in this specification is all merely exemplary, rather than limit Property processed.
Doping method is well known by persons skilled in the art, so being repeated no more to the method in this manual.
Alternatively, SOI (silicon-on-insulator) substrate can be used.
Substrate 6 includes the second side 10 relative with first side 8 of first side 8, top margin 12 and relative with top margin 12 Base 14, and show the thickness of determination.The thickness of substrate 6 is adapted to improve the integrated diode density value of diode 4.Example Such as, the thickness of substrate 6 may approximately equal to 100 μm (1 μm=1 × 10-6m)。
As shown in figure 1, diode 4 is included at least three holes etched in substrate 6.Each hole has the wall of nitrating (herein we assume that, as described above, substrate 6 is p-doped), that is, wall doping type and substrate doping type not Together.Each hole is filled with polysilicon, and polysilicon extends to top margin 12, so connecting all holes by polysilicon.In polycrystalline Implement electrode in silicon top.
As shown in figure 1, each hole is different in substrate 6.In the preferred embodiment that Fig. 1 is explained, the width and depth in each hole It is different.In the embodiment in figure 1, it can be seen that the width and depth in each hole subtract from first side 8 to second side 10 It is few.
Because Fig. 1 " only " is cross-sectional view, the shape in each hole is not shown.Two poles according to Fig. 1 are manufactured from explaination The method of pipe it is as described below in visible, each Kong Kewei different shapes explained herein.
As first step of manufacture diode 4, protective layer 16 is deposited on the top margin 12 of substrate 6.Fig. 2 is illustrated This method and step.Protective layer 16 is adapted to the etching step of resistance substrate 6.Etching step will be said in the following description It is bright.For example, protective layer 16 includes the silica (SiO2) obtained by the oxidation step of substrate 6.By wet oxidation process or dry type Oxidizing process implements oxidation step.No longer state these oxidations well known by persons skilled in the art in further detail in this manual Method.For example, the thickness of protective layer 16 is approximately equal to 1 μm.
In order to implement hole in substrate 6, the light of photoresist layer (not shown) is filed out in implementation on protective layer 16 Step is carved, and the size and dimension in hole to be etched is determined by the lithography step.
Substrate 6 is carved by each pitting implemented in protective layer 16.Fig. 3 illustrates this method and step.Pushed up by substrate 6 At least one etching step on side 12 implements each hole.For example, being existed by wet etching step or dry etch step, or handle After dry etching the implementation etching step is combined with wet etch step.Therefore, it can control each hole wall it is coarse Degree.
As described above, each hole shape is different.Fig. 4 shows one embodiment, wherein etching three holes in substrate 6： First hole 18, the second hole 20 and the 3rd hole 22, these three holes are circular hole.It is spaced apart between each hole.First hole 18 It is the hole nearest from the first side 8 of substrate 6, the 3rd hole 22 is nearest from the second side 10 of substrate 6.Second hole 20 the first hole 18 with Between 3rd hole 22.In an example, distance is equal to 2 μm between holes.The diameter and depth in each hole are from first side 8 to base Reduce the second side 10 of plate 6.Such as each bore dia changes between 1 μm to 2 μm, anaplasia of each hole depth at 20 μm to 60 μm Change.
Fig. 5 illustrates another example, and wherein diode 4 includes multirow hole.Fig. 5 illustrates the diode in only three row holes 4, often row hole only include two holes.Therefore, diode 4 have the first hole 18 of the first row 24, the second row 26 the second hole 20 with And the 3rd hole 22 of the third line 28.
Each row hole is parallel to each other.The depth and width in each hole from a line to adjacent lines are according to from second side 10 to the first The direction of side 8 increases.The hole of each row 24,26,28 parallel to substrate 6 first side 8, and each hole width and depth according to The direction vertical with each row increases.
It will be apparent to those skilled in the art that the embodiment can be promoted, and the N rows hole of quantification can be implemented.And, The quantity of each row mesopore is frequently different than two.The quantity of a line mesopore can also be different from another row.For example, the quantity in hole from The first row 24 is reduced to last column (in Fig. 5, be the third line 28).Preferably relative to the plane of symmetry distribution perpendicular to each row hole respectively Hole in row.
It is advantageously possible to the change in any one cited parameter is combined with another parameter.For example, can be with The change of the line number in hole is combined with the change of the diameter in each row hole.
In a preferred implementation example, the shape of each Kong Doucheng groove.Fig. 6 shows first of the embodiment Example, wherein, diode 4 includes three grooves 38,40,42.Each groove 38,40,42 is presented certain depth and width, And parallel to the first side 8 of substrate 6.In order to optimize distribution of the electric current line in diode 4, the depth and width of groove are pressed Increase according to the direction from a groove to adjacent trenches.Second side 10 of the groove 38,40,42 parallel to substrate 6.Note, ditch The variable amounts of groove.
For all grooves, the distance between two adjacent trenches can be with identical, for example, 10m.But, two phases The distance between adjacent groove is also variable.
In an example of embodiment, the length of groove 38,40,42 is also different.Thus, for example, the length of groove is pressed Increase to the 3rd direction of groove 42 according to from first groove 38, as shown in Figure 7.
Etch after each hole, precognition is doped step (Fig. 8) in each hole.For example, being diffused into silicon substrate 6 by carrier Implement this doping step.Advantageously, because protective layer 16, implements carrier diffusion only on the wall in each hole.Because we recognize For substrate 6 is phosphorus doping, so the carrier for being used herein to doping is N- carriers.Deposited by vapor-gas phase or planted by ion Enter step and implement carrier implantation step.
If the distance between each hole is less than the diffusion length of dopant (such as containing phosphorus dopant), Kong Ze is deeper as one Unified PN junction, but if the distance between each hole is larger, then then obtain parallel several diodes.This second herein Option is preferred, and selects this second option.
Statement deposition step well known by persons skilled in the art no longer more detailed in this manual and diffusing step. Advantageously, because adulterated on each hole wall, so the series resistance rate of diode 4 is relatively low.
Then, polysilicon layer 46 is deposited in hole (Fig. 8).For example, precipitating (LPCVD) by low pressure chemical phase precipitates many Crystal silicon layer 46.Advantageously, polysilicon layer 46 is doped polysilicon, because this helps to reduce the contact resistance of diode, but It is that can also use non-crystalline silicon.Advantageously, polysilicon layer 46 fills each hole, and covers certain area of the top margin 12 of substrate 6, So as to all holes are linked together.In a preferred embodiment of the invention, polysilicon layer 46 at least 16 surpasses than protective layer Go out 1 μm.Then it is figuratum.
Passivation layer 48 (Fig. 9) is deposited on the top margin 12 of substrate 6, and corresponding with the part of polysilicon layer 46 for exceeding is certain Except area.
Passivation layer 48 is that first electrode 44 and such as silica (SiO2) or thickness are more than polycrystalline in this manual Silicon nitride layer of the silicon layer 46 beyond thickness.Passivation Treatment well known by persons skilled in the art is not described in detail herein.By leading The sputtering sedimentation of electric layer implements second electrode 50, such as described conductive layer is aluminium (Al), or other types of metals, is have pattern 's.Deposition process well known by persons skilled in the art is not described in detail in this manual.First electrode 44 is conductively coupled to Second electrode 50, is couple to polysilicon layer 46 by substrate 6.Advantageously, the first electrode 44 of diode 4 and second electrode 50 In the integration value on the top margin 12 of substrate 6, enabling increase diode.
In order to increase the ability of driving current, make each hole of diode 4 parallel.
Diode 4 can be couple to passive and/or active component or element group
Advantageously, diode 4 is protected for static discharge (ESD).For example, diode 4 can be couple to capacitor or ditch The input of trench capacitor.Note, by the first electrode 44 and second electrode of the polarity diode 4 that consider diode 4 50 are couple to element to be protected.
If thus, for example, by diode 4 realize circuit input end ESD positive poles protect, the second of diode 4 Electrode 50 is couple to power end, first electrode 44 is couple to the input of the circuit.
Can also realize that ESD negative polarity is protected by diode 4.
In order to realize that bipolarity ESD is protected, proposition includes a kind of two electrostatic discharge protective equipments of diode.Figure 10 shows This electrostatic discharge protective equipment including diode 4 and second diode 41 is shown.Advantageously, second diode 41 is identical with the characteristic of diode 4 and symmetrical therewith.Furthermore, it is possible to obtain second by with the identical manufacture method of diode 4 Individual diode 41.
Second diode 41 and diode 4 are manufactured on same substrate 6.Therefore, electrostatic discharge (ESD) protection dress is optimized The integration density put.
Second diode 41 in Figure 10 has three holes：First hole 62, the second hole 60 and the 3rd hole 58.Because second Individual diode 41 is symmetrical with diode 4, and the depth and width in its hole are reduced from second side 10 to first side 8.Place Second position of diode 41, makes its first hole 62 be located at the side of the first side 8 of substrate 6.Second the of diode 41 One hole 62 is separated by a distance with the first hole 18 of diode 4.For example, the first hole 62 of second diode 41 and diode 4 The distance between the first hole 18 be equal to 75 μm.
For protection circuit, diode 4 advantageously with second coupled in series of diode 41, more specifically, diode 4 Coupled with back-to-back position with second diode 41.The original structure can obtain the ESD protections of optimization, with protection circuit Normal operation mode supports positive pulse and negative pulse.
Can be passed through by this structure, including diode 4 and second electrostatic discharge protective equipment of diode 41 Bi-directional ESD protection circuit, and obtain the circuit that electric current is preferably distributed in substrate 6.
In order to show the benefit of the new construction for herein proposing, the ESD robustness of two structures is compared.Compare (all structures are all 24000 μm to the area of coverage2) identical back to back diode structure.
First structure has groove width, depth and length whole identical 3D diodes.Two poles are back-to-back set The position of pipe, and the distance between diode is 75 μm.Each diode is made up of six grooves that width is equal to 1 μm. Diode area is (18*224) μm2=4032 μm2.All structural areas are 24000 μm2。
Second structure has 3D diodes, and its trench length is identical, but the width of groove and depth are from before diode Face increases to behind diode.One minimum groove of diode is before the minimum groove of another diode.Back-to-back The position of diode is placed on ground, and the distance between diode (the distance between minimum groove) is 75 μm.Each diode Six grooves by width between 1 μm to 2.2 μm are constituted.Diode area is (18*224) μm2=4032 μm2, Suo Youjie Structure area is 24000 μm2。
Figure 11 shows the curve for representing measured value experimental result.In the figure, there are groove width and depth all identical Prior art in back to back diode four curves, first entitled A1 of curve (expression leakage current), Article 2 is bent The entitled A2 of line (represents electric current and voltage (I-V)).Entitled B1 (expression leakage current) and B2 (represent electric current and voltage (I- V)) the two other curve back to back diode different from groove width and depth (there are six diodes 4,41 of groove) phase Correspondence.
The ESD robustness of diode, the transmission line pulse (TLP) are constituted by using transmission line pulse (TLP) system System is effective analysis tool.The current impulse that the system is produced within the duration of 100ns is from 1mA to 20A.Each pulse Measurement direct current (DC) l leakages afterwards, enable to detect the damage of sample.In the case where not causing to damage to it, drive Electric current through diode is higher, and ESD robustness is higher.Because groove width is different with depth, in back to back diode 4,41 TLP electric current of the TLP electric currents of middle circulation more than the back to back diode of prior art.Therefore, in this illustration, back-to-back two Current impulse can be maintained the about maximum of 13A by pole pipe 4,41, and had identical structural area and be all 19V Zeners Current impulse can only be maintained about 11A by the back to back diode in the prior art of voltage.Therefore, back to back diode 4,41 TLP performances it is higher by 20% than prior art back to back diode structure.
Further, since the series resistance of original structure diode 4,41 is relatively low, so the electric current distribution in improving substrate, makes Can realize the good ESD level of protection with good ESD robustness.
Figure 12 shows an example of integrated electrostatic discharge device, and the static discharge device includes being couple to active electrical Two diodes 4,41 on road, the active circuit includes inductor 70 and high level capacitor 72.
Figure 13 illustrates the schematic circuit diagram of this device.In the situation shown in figure 13, with the circuit of input 76 The 74 high level capacitors 72 and inductor 70 for signifying Figure 12.
The first electrode 44 of diode 4 is couple to electrical ground, and the second electrode 50 of diode 4 is couple to the of diode 41 Two electrodes 55.The first electrode 54 of diode 41 is couple to input 76.For example, the input 76 of protection circuit 74 is adapted to receive Signal (not shown).
Due to electrostatic discharge protective equipment, two-way interference can be evacuated.Therefore, the positive interference of input 76 is couple to The negative interference of input 76, is couple to VCC by ground G ND.It is contemplated that other types of coupling.
Additionally, in an advantageous embodiment of the invention, diode 4 can be stacked on another diode.Can be with Electrostatic discharge protective equipment including at least two diodes 4,41 is stacked on another electrostatic discharge protective equipment, so as to Multiple circuit input ends can be protected.
Note, electrostatic discharge protective equipment can be couple to active circuit and/or passive circuit.Can also be static discharge Protection device is connected to other types of element or circuit, such as inductor or high level capacitor.
The present invention provides a kind of easily fabricated diode.The present invention also provides a kind of electrostatic discharge protective equipment, including Two diodes of coupled in series, the diode has integration density value and TLP electric currents higher higher.
By structure as described above, propose that the resistance by reducing each hole (preferably groove) in back-to-back topology is obtained More preferable current spread.This point is realized by the width and/or depth of widening each hole (groove) behind diode structure.
Width from before from diode to increase hole behind diode produces first physical effect.If behind diode Hole width it is larger, then compared with the hole before diode, the series resistance in the hole behind diode is relatively low.So in device The uniformity of electric current is more preferable.For given applied current, current density (, the Kong Xiang identical relative to size in front aperture As prior art diode for) it is relatively low, and have several focuses in silicon.Therefore the ESD robustness of device is more preferable.
Second physical effect is produced by the depth for increasing hole.Kong Yueshen behind diode, more being capable of more preferable land productivity With the purposes of silicon, because greater part silicon is utilized.During esd event, therefore electric current is better distributed in substrate In.
The present invention is illustrated and described in detail in each figure and preceding description, it is necessary to which this explaination and explanation are considered as explanation Property is illustrative, and not restrictive, and the present invention is not limited only to the disclosed embodiments.Putting into practice the claimed present invention During, by studying accompanying drawing, patent application specification and appended claims, it will be appreciated by those skilled in the art that simultaneously Implement the variant of the disclosed embodiments.

Claims (13)

1. a kind of semiconductor device, be included in substrate (6) implement with respective width and depth at least two holes (18, 20), and a kind of diode (4) is formed
Wherein, doping type of the substrate (6) with determination, and
Wherein, adulterate the inwall in each hole (18,20), and μ makes its doping type different from substrate (6) doping,
Characterized in that, the width and/or depth of hole (18,20) are different from the width and/or depth of adjacent holes.
2. semiconductor device according to claim 1, it is characterised in that each hole (18,20) is all circular port, Er Qiete Levy also reside in each hole width it is corresponding with its diameter.
3. semiconductor device according to claim 1 and 2, it is characterised in that diode (4) includes
At least two row holes (24,26), often row hole (24,26) be parallel to another row hole,
It is further characterized in that, the width with a line hole is identical with depth, and
It is further characterized in that, the depth and/or width in hole increase according to from a line hole to the direction in adjacent lines hole.
4. semiconductor device according to claim 1, it is characterised in that each hole (18,20) is all groove (38,40).
5. semiconductor device according to claim 4, it is characterised in that each groove (38,40) is parallel to other ditches Groove (38,40), and
It is further characterized in that the depth and/or width of groove (38,40) increase according to the direction from a groove to adjacent trenches.
6. semiconductor device according to claim 5, it is characterised in that each groove (38,40) is presented a length,
It is further characterized in that the length of groove increases according to the direction from a groove to adjacent trenches.
7. semiconductor device according to any one of claim 1 to 6, it is characterised in that hole (18,20) coupled in parallel.
8. a kind of static discharge device, it is characterised in that including two two poles according to any one of claim 1 to 7 Pipe (4,41).
9. static discharge device according to claim 8, it is characterised in that each diode (4,41) all includes multirow Hole, and second multirow hole of diode (41) is parallel to first multirow hole (24,26) of diode (4).
10. static discharge device according to claim 8, it is characterised in that each diode (4,41) all includes groove, And second groove of diode (41) is parallel to first groove (38,40) of diode (4).
11. static discharge device according to any one of claim 8 to 10, it is characterised in that with back-to-back position Coupling first diode (4) and second diode (41).
12. static discharge device according to any one of claim 8 to 11, it is characterised in that it includes being stacked on one At least two semiconductor devices (2) for rising.
13. static discharge device according to any one of claim 8 to 12, it is characterised in that it is couple to active electrical Subcomponent and/or passive electronic components.
CN201580050455.7A 2014-09-10 2015-09-07 Semiconductor device and electrostatic discharge protective equipment including diode Pending CN106796937A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP14306394.9A EP2996156A1 (en) 2014-09-10 2014-09-10 Semiconductor device comprising a diode and electrostatic discharge protection device
EP14306394.9 2014-09-10
PCT/EP2015/070411 WO2016037990A1 (en) 2014-09-10 2015-09-07 Semiconductor device comprising a diode and electrostatic discharge protection device

Publications (1)

Publication Number Publication Date
CN106796937A true CN106796937A (en) 2017-05-31

Family

ID=51625977

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580050455.7A Pending CN106796937A (en) 2014-09-10 2015-09-07 Semiconductor device and electrostatic discharge protective equipment including diode

Country Status (5)

Country Link
US (1) US10177258B2 (en)
EP (2) EP2996156A1 (en)
JP (1) JP2017533581A (en)
CN (1) CN106796937A (en)
WO (1) WO2016037990A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086501A (en) * 2019-06-13 2020-12-15 彩优微电子(昆山)有限公司 Diode with high electrostatic protection capability and forming method thereof
TWI695479B (en) * 2019-07-02 2020-06-01 大陸商彩優微電子（昆山）有限公司 Diode with high esd protection capability and method for forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1524298A (en) * 2001-05-22 2004-08-25 ͨ�ð뵼�幫˾ DMOS with zener diode for ESD protection
US20130153916A1 (en) * 2011-12-16 2013-06-20 Infineon Technologies Ag Semiconductor Device Including a Diode
WO2014132937A1 (en) * 2013-02-28 2014-09-04 株式会社村田製作所 Esd protection device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534759B1 (en) * 2001-09-10 2003-03-18 National Semiconductor Corporation Vertical photodetector with improved photocarrier separation and low capacitance
US7544545B2 (en) 2005-12-28 2009-06-09 Vishay-Siliconix Trench polysilicon diode
EP2130226B1 (en) * 2007-02-12 2012-06-06 Nxp B.V. ESD-protection device, a semiconductor device and an integrated system in a package comprising such a device
CN101847663B (en) * 2010-04-30 2012-08-15 上海新进半导体制造有限公司 Transient voltage suppressor (TVS) and method for forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1524298A (en) * 2001-05-22 2004-08-25 ͨ�ð뵼�幫˾ DMOS with zener diode for ESD protection
US20130153916A1 (en) * 2011-12-16 2013-06-20 Infineon Technologies Ag Semiconductor Device Including a Diode
WO2014132937A1 (en) * 2013-02-28 2014-09-04 株式会社村田製作所 Esd protection device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
B.COURIVAUD ET AL: "Novel 3D back-to-back diodes ESD protection", 《ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM》 *

Also Published As

Publication number Publication date
WO2016037990A1 (en) 2016-03-17
EP2996156A1 (en) 2016-03-16
US10177258B2 (en) 2019-01-08
JP2017533581A (en) 2017-11-09
EP3192102A1 (en) 2017-07-19
US20170243984A1 (en) 2017-08-24

Similar Documents

Publication Publication Date Title
CN103972303B (en) Diode, esd protection circuit and its manufacturing method
CN104851919B (en) Two-way break-through semiconductor devices and its manufacture method
CN106449634B (en) Transient Voltage Suppressor and its manufacturing method
TWI408814B (en) Bi-directional transient voltage suppression device and forming method thereof
US7514751B2 (en) SiGe DIAC ESD protection structure
CN105261616A (en) Transient voltage suppressor and manufacturing method thereof
US20060216913A1 (en) Asymmetric bidirectional transient voltage suppressor and method of forming same
CN106449633B (en) Transient Voltage Suppressor and its manufacturing method
US9330961B2 (en) Stacked protection devices and related fabrication methods
CN101847663A (en) Transient voltage suppressor (TVS) and method for forming same
US20190103396A1 (en) Single-stack bipolar-based esd protection device
JP2014096590A (en) Protection device and related fabrication method
US9543420B2 (en) Protection device and related fabrication methods
TWI591792B (en) Electrostatic discharge devices and method of making the same
KR102076374B1 (en) ElectroStatic Discharge device and method of fabricating the same
CN106796937A (en) Semiconductor device and electrostatic discharge protective equipment including diode
US11430780B2 (en) TVS device and manufacturing method therefor
US20230122120A1 (en) Transient Voltage Suppression Device And Manufacturing Method Therefor
CN108565260B (en) Semiconductor device with a plurality of transistors
KR101006768B1 (en) Structure of a tvs diode array and its fabrication method
CN113540072B (en) Electrostatic discharge protection device and method of forming an electrostatic discharge protection device
JP6594296B2 (en) Zener diode with polysilicon layer with improved reverse surge capability and reduced leakage current
US8921973B2 (en) Semiconductor device
US8853026B2 (en) Semiconductor device having deep wells and fabrication method thereof
CN108565259B (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Caen, France

Applicant after: Murata integrated passive solutions company

Address before: Caen, France

Applicant before: Nxp BV

WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170531