TWI695479B - Diode with high esd protection capability and method for forming the same - Google Patents

Abstract

A diode with high ESD protection capability is provided. The diode includes a silicon substrate layer of a first conductivity type, plural first trenches and plural second trenches formed in the silicon substrate layer, plural shallow trench isolation structures, and a polysilicon layer of a second conductivity type. The shallow trench isolation structures are respectively disposed within the first trenches, thereby filling the first trenches. The polysilicon layer is conformally formed on a surface of the second trenches.

Description

Diode with high electrostatic protection capability and its Forming method

The disclosed embodiments relate to a diode, and particularly to a diode with high electrostatic protection capability and a method of forming the same.

The damage of static electricity to electronic products has always been a problem that is not easy to solve, especially in the application of high-frequency circuits. In order not to affect the normal working performance of the product, the input and output interfaces of the circuit usually require electrostatic protection components to have a strong current discharge capability. Most of the common high-frequency circuits nowadays, the electrostatic protection components of the input and output interfaces are mostly diodes. When electrostatic discharge occurs, the N-type diode is used to discharge the forward current from the ground terminal to the input and output interface, and the P-type diode is used to discharge the forward current from the input and output interface to the power supply terminal. In order to improve the current withstand capability of the diode itself and thus improve the electrostatic protection capability, it is usually necessary to increase the area of the diode, however, this method is disadvantageous for the miniaturization of the product.

The purpose of this disclosure is to propose a high electrostatic protection By using a trench structure and forming a polysilicon layer on the trench structure as the electrode of the diode, Li diode can increase the contact area of the P/N interface, thereby improving the current tolerance of the diode itself ability. The disclosure can enable the diode to have a high electrostatic protection capability without increasing the area of the diode.

According to the above object of the present disclosure, a diode with high electrostatic protection capability is proposed including: a silicon base layer having a first conductivity type, a plurality of first trenches and a plurality of second trenches formed in the silicon base layer 3. A plurality of shallow trench isolation (STI) structures and polysilicon layers with a second conductivity type. The shallow trench isolation structures are respectively disposed in the first trench to fill the first trench. The polysilicon layer is conformally formed on the surface of the second trench.

In some embodiments, the silicon base layer further includes a highly doped region with the first conductivity type, wherein the highly doped region is sandwiched between two adjacent shallow trench isolation structures.

In some embodiments, the first trench surrounds the second trench.

In some embodiments, the above shallow trench isolation structure is used to isolate the highly doped region with the first conductivity type from the polysilicon layer with the second conductivity type.

In some embodiments, the second trenches are arranged in a matrix on the surface of the silicon base layer.

In some embodiments, the second trenches are arranged in a ring and concentrically on the surface of the silicon base layer.

According to the above purpose of the present disclosure, another method for forming a diode with high electrostatic protection capability is provided, which includes: etching a silicon base layer having a first conductivity type to form a plurality of first trenches and a plurality of second trenches The trench is in a silicon base layer having a first conductivity type; the first trench is filled with a dielectric material to form a plurality of shallow trench isolation structures in the first trench; and a polysilicon material is deposited on the second trench On the surface, a polysilicon layer is conformally formed on the surface of the second trench.

In some embodiments, the polysilicon material is a polysilicon material with a second conductivity type, so that the polysilicon layer becomes a polysilicon layer with a second conductivity type.

In some embodiments, the method for forming a diode with high electrostatic protection capability further includes: performing an ion implantation process on the polysilicon layer to dope the polysilicon layer so that the polysilicon layer becomes A polysilicon layer of the second conductivity type.

In some embodiments, the method for forming a diode with high electrostatic protection capability further includes: performing ion implantation treatment on the silicon base layer to form a A highly doped region of conductivity type.

In some embodiments, the first trench surrounds the second trench.

In some embodiments, the above shallow trench isolation structure is used to isolate the highly doped region having the first conductivity type from the polysilicon layer.

In some embodiments, the second trenches are arranged in a matrix on the surface of the silicon base layer.

In some embodiments, the second trenches are arranged in a ring and concentrically on the surface of the silicon base layer.

In order to make the above-mentioned features and advantages of the present disclosure more comprehensible, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

100, 200‧‧‧ diode

110、210‧‧‧Si base layer

120、220‧‧‧Shallow trench isolation structure

130‧‧‧Si layer

140, 240‧‧‧Highly doped area

210a‧‧‧The first groove

210b‧‧‧Second groove

230, 250‧‧‧polysilicon layer

230a‧‧‧Upper

230b‧‧‧Trench area

260‧‧‧Photoresist

270‧‧‧Conductor column

280‧‧‧electrode layer

290‧‧‧gap

300‧‧‧Formation method

310, 320, 330, 340‧‧‧ steps

From the following detailed description made in conjunction with the attached drawings, we can have a better understanding of the present disclosure. It should be noted that according to industry standard practices, the features are not drawn to scale. In fact, in order to make the discussion clearer, the size of each feature can be arbitrarily increased or decreased.

[FIG. 1A] A schematic cross-sectional view showing the structure of one of the conventional diodes.

[Fig. 1B] is a schematic top view showing the structure of one of the conventional diodes.

[FIG. 2] A schematic cross-sectional view of a structure of a diode according to an embodiment of the present disclosure.

[FIG. 3] A flowchart of a method of forming a diode according to an embodiment of the present disclosure.

[FIG. 4A]-[FIG. 4E] are schematic diagrams of steps of a method of forming a diode according to an embodiment of the present disclosure.

5 is a schematic top view of the structure of the diode according to the first embodiment of the present disclosure.

6 is a schematic top view of the structure of the diode according to the second embodiment of the present disclosure.

7 is a schematic cross-sectional view of the structure of a complete device of a diode according to an embodiment of the present disclosure.

The embodiments of the present invention are discussed in detail below. However, it can be understood that the embodiments provide many applicable concepts that can be implemented in a variety of specific contents. The discussed and disclosed embodiments are for illustration only and are not intended to limit the scope of the present invention. In addition, with regard to the "first", "second", ... etc. used in this article, it does not specifically mean the order or order, but only distinguishes the elements or operations described in the same technical terms.

FIG. 1A is a schematic cross-sectional view of one of the conventional diodes 100, and FIG. 1B is a schematic top view of the structure of one of the conventional diodes 100. FIG. The conventional diode 100 includes a silicon base layer 110, a plurality of shallow trench isolation (STI) structures 120, a silicon layer 130, and a highly doped region 140. The silicon base layer 110 has a first conductivity type. The first conductivity type is, for example, P-type, that is, the silicon base layer 110 is a P-type silicon base layer. A plurality of shallow trench isolation (STI) structures 120 are formed on the silicon base layer 110, and as shown in FIG. 1B, the shallow trench isolation structures 120 are annularly and concentrically arranged on the silicon base layer 110 . The silicon layer 130 is formed on the silicon base layer 110 and is disposed in the innermost shallow trench isolation structure 120, as shown in FIG. 1B. The silicon layer 130 has a second conductivity type. The second conductivity type is, for example, N-type, that is, the silicon layer 130 is an N-type silicon layer. The highly doped region 140 is formed on the silicon base layer 110 and is disposed between two adjacent shallow trench isolation structures 120 and also presents an annular configuration, as shown in FIG. 1B. Highly doped region 140 has the first conductivity type and the doping concentration is higher than that of the silicon base layer 110, that is, the highly doped region 140 is a P-type highly doped region (P+ doped region).

For the conventional diode 100, the contact area of the P/N interface is equivalent to the area at the junction of the silicon layer 130 and the silicon base layer 110. Therefore, in order to improve the current withstand capability of the conventional diode 100 itself To improve the electrostatic protection capability, it is usually necessary to increase the area of the conventional diode 100. However, this method is disadvantageous for the miniaturization of products. The purpose of this disclosure is to propose a diode 200 with high electrostatic protection capability to improve the disadvantages of the above-mentioned conventional diode 100.

2 is a schematic cross-sectional view of a structure of a diode 200 according to an embodiment of the present disclosure. The diode 200 includes: a silicon base layer 210, a plurality of shallow trench isolation structures 220, a polysilicon layer 230, and a highly doped region 240. The silicon base layer 210 has a first conductivity type. In the embodiment of the present disclosure, the first conductivity type is, for example, P-type, that is, the silicon base layer 210 is a P-type silicon base layer. However, the present disclosure is not limited to this, the first conductivity The type may also be, for example, N-type, that is, the silicon base layer 210 is an N-type silicon base layer. The polysilicon layer 230 has a second conductivity type, and the second conductivity type is different from the first conductivity type. In other words, when the first conductivity type is P type, the second conductivity type is N type, that is, the polysilicon layer 230 is N type Polysilicon layer; when the first conductivity type is N-type, the second conductivity type is P-type, that is, the polysilicon layer 230 is a P-type polysilicon layer. The highly doped region 240 has a first conductivity type and a doping concentration higher than that of the silicon base layer 210. When the first conductivity type is a P type, the highly doped region 240 is a P type doped region (P+ doped region); when If the first conductivity type is N-type, the highly doped region 240 is an N-type highly doped region (N+ doped region). It is worth mentioning that what is shown in Figure 2 The number of shallow trench isolation structures 220 and highly doped regions 240 are only examples, and the disclosure is not limited thereto. The structural details of the diode 200 will be further described below.

It should be noted that, as shown in FIG. 2, the contact area of the P/N interface of the diode 200 is equivalent to the area at the junction of the polysilicon layer 230 and the silicon base layer 210. Compared with the conventional diode 100, the diode The contact area of the P/N interface of the body 200 is significantly increased, so the current withstand capability of the diode 200 is better than that of the conventional diode 100. In other words, for the same area of the conventional diode 100 and the diode In terms of 200, the electrostatic protection capability of the diode 200 is better than that of the conventional diode 100. From another perspective, since the diode 200 has better electrostatic protection capability, the area of the diode 200 can be smaller than that of the conventional diode 100 under the condition of ensuring the static protection capability unchanged, so that it can be reduced The area of the product containing diode 200.

FIG. 3 is a flowchart of a method 300 for forming a diode 200 according to an embodiment of the present disclosure. 4A to 4E are schematic diagrams of steps of a method for forming a diode 200 according to an embodiment of the present disclosure. The method 300 for forming the diode 200 includes step 310: setting a patterned hard mask layer (not shown) on the silicon base layer 210 as a mask, and etching the silicon base layer having the first conductivity type through an etching process 210. A plurality of first trenches 210a and a plurality of second trenches 210b are formed in the silicon base layer 210 having the first conductivity type, as shown in FIG. 4A. In the embodiment of the present disclosure, the depths of the first trench 210a and the second trench 210b are about 0.7 micrometers (μm), but the present disclosure is not limited thereto. It is worth mentioning that the numbers of the first trench 210a and the second trench 210b shown in FIG. 4A are only examples, and the disclosure is not limited thereto.

After step 310, proceed to step 320: fill the first trench 210a with a dielectric material to form a plurality of shallow trench isolation structures 220 in the first trench 210a, as shown in FIG. 4B, the shallow trench isolation structure The 220 series fills the first trench 210a. In the embodiments of the present disclosure, the method for forming the dielectric material may be Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or chemical vapor deposition ( Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), Low-pressure Chemical Vapor Deposition (Low-Pressure Chemical Vapor Deposition (LPCVD) and other similar methods. It should be noted that in the actual manufacturing process, the first trench 210a and the second trench 210b are filled with dielectric material first, and then the dielectric material formed in the second trench 210b is removed through the etching process .

After step 320, step 330 is performed: depositing polysilicon material on the surface of the second trench 210b to conformally form a polysilicon layer 250 on the surface of the second trench 210b, as shown in FIG. 4C. It is worth mentioning that the polysilicon layer 250 is also formed on the surface of the shallow trench isolation structure 220 and the silicon base layer 210. In the embodiments of the present disclosure, the method for depositing polysilicon material may be, for example, chemical vapor deposition (CVD).

After step 330, the polysilicon layer 250 formed on the surface of the shallow trench isolation structure 220 and the silicon base layer 210 is removed by an etching process to implement the polysilicon layer 230, as shown in FIG. 4D. In other words, polysilicon The layer 230 is conformally formed on the surface of the second trench 210b.

As previously mentioned, the polysilicon layer 230 has the second conductivity type. In some embodiments of the present disclosure, the polysilicon material of step 330 may be a polysilicon material with a second conductivity type. In this way, through the foregoing steps, the polysilicon layer 230 will therefore have the second conductivity type. In other embodiments of the present disclosure, if the polysilicon material in step 330 is undoped, the polysilicon layer 230 may be further ion-implanted to dope the polysilicon layer 230 to The polysilicon layer 230 becomes the polysilicon layer 230 with the second conductivity type. When performing the ion implantation process, as shown in FIG. 4E, a photoresist 260 is formed on the surface of the shallow trench isolation structure 220 and the silicon base layer 210, and then the ion implantation process is performed to ensure The shallow trench isolation structure 220 and the silicon base layer 210 are not doped. It is worth mentioning that if the second conductivity type is N type, the ion implantation treatment system implants pentavalent ions; if the second conductivity type is P type, the ion implantation treatment system implants trivalent ions.

After the polysilicon layer 230 is formed, step 340 is performed: the portion of the silicon base layer 210 interposed between the two adjacent shallow trench isolation structures 220 is ion implanted to isolate the two adjacent shallow trenches Highly doped regions 240 having the first conductivity type are formed between the structures 220, as shown in FIG.

It is worth mentioning that all the steps of the above-mentioned method 200 for forming the diode 200 can correspond to the steps of the known method for forming the diode. In other words, the method 300 for forming the diode 200 of the present disclosure does not require additional process steps. Further, in the normal integrated circuit (IC) manufacturing process, there are shallow trench isolation (STI) steps can be It is used to realize the first trench 210a and the second trench 210b. In addition, the polysilicon layer 230 does not need to add other process steps. The polysilicon material can be deposited through the poly gate in the normal IC manufacturing process. The doping method of the polysilicon layer 230 can be based on the specific process Make sure that if the process is compatible with N-type polycrystalline silicon deposition or P-type polycrystalline silicon deposition, no new doping step is required. If the process is not compatible with N-type polycrystalline silicon deposition or P-type polycrystalline silicon deposition, ion distribution can be used in subsequent steps In the implantation process, the polysilicon layer 230 is doped so that the polysilicon layer 230 becomes the polysilicon layer 230 with the second conductivity type.

FIG. 5 is a schematic top view of the structure of the diode 200 according to the first embodiment of the present disclosure. As can be seen from FIG. 5, the first trench 210 a corresponding to the shallow trench isolation structure 220 surrounds the second trench 210 b corresponding to the polysilicon layer 230, and the shallow trench isolation structure 220 is used to isolate the first conductivity type The highly doped region 240 and the polysilicon layer 230 having the second conductivity type. 2 and 5 together, the polysilicon layer 230 includes an upper part 230a and a trench region 230b, the upper part 230a corresponds to the top surface of the second trench 210b, and the trench region 230b corresponds to the bottom surface and the side wall of the second trench 210b . As can be seen from FIG. 5, the trench regions 230 b of the polysilicon layer 230 corresponding to the second trench 210 b are arranged in a matrix on the surface of the silicon base layer 210. It is worth mentioning that the matrix arrangement shown in FIG. 5 is only an example, and the disclosure is not limited thereto.

FIG. 6 is a schematic top view of the structure of the diode 200 according to the second embodiment of the present disclosure. 6 that the first trench 210a corresponding to the shallow trench isolation structure 220 surrounds the second trench 210b corresponding to the polysilicon layer 230, and the shallow trench isolation structure 220 is used to isolate the first conductivity type The highly doped region 240 and the polysilicon layer 230 having the second conductivity type. As can be seen from FIG. 6, the trench regions 230 b of the polysilicon layer 230 corresponding to the second trench 210 b are arranged in a ring and concentrically on the surface of the silicon base layer 210.

7 is a schematic cross-sectional view of a structure of a complete device of a diode 200 according to an embodiment of the present disclosure. The complete device of the diode 200 includes a conductor post 270, an electrode layer 280 and a spacer 290, the conductor post 270 is formed on the highly doped region 240 and the polysilicon layer 230, the electrode layer 280 is formed on the conductor post 270, the spacer 290 is formed on both sides of the conductor post 270. The conductive post 270 is used to electrically connect the highly doped region 240 and the electrode layer 280 and/or to electrically connect the polysilicon layer 230 and the electrode layer 280. In the embodiment of the present disclosure, the spacer 290 is filled with tetraethoxysilane (TEOS) and/or high density plasma (HDP), but the present disclosure is not limited thereto.

In summary, the present disclosure proposes a diode 200 with high electrostatic protection capability. By using a trench structure (second trench 210b) and forming a polysilicon layer 230 on the trench structure as an electrode of the diode, In order to increase the contact area of the P/N interface, the current withstand capability of the diode 200 itself is improved. The disclosure can enable the diode to have a high electrostatic protection capability without increasing the area of the diode.

The above outlines the features of several embodiments, so those skilled in the art can better understand the aspect of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures, thereby achieving the same goals and/or achieving the same advantages as the embodiments described herein . Those skilled in this art should also understand that these equivalent The structure does not deviate from the spirit and scope of this disclosure, and they can make various changes, replacements, and changes without departing from the spirit and scope of this disclosure.

200‧‧‧ Diode

210‧‧‧Si base layer

220‧‧‧Shallow trench isolation structure

230‧‧‧polysilicon layer

230a‧‧‧Upper

230b‧‧‧Trench area

240‧‧‧Highly doped area

Claims (14)

A diode with high electrostatic protection capability, comprising: a silicon base layer with a first conductivity type; a plurality of first trenches and a plurality of second trenches formed in the silicon base layer; a plurality of shallow A trench isolation (STI) structure is respectively disposed in the first trenches to fill the first trenches; and a polysilicon layer with a second conductivity type is conformally formed in the On a surface of the second trenches. The diode with high electrostatic protection capability as described in item 1 of the patent scope, wherein the silicon base layer further includes a highly doped region having the first conductivity type, wherein the highly doped region is interposed between Between two adjacent shallow trench isolation structures. The diode with high electrostatic protection capability as described in item 1 of the patent application scope, wherein the first trenches surround the second trenches. The diode with high electrostatic protection capability as described in item 2 of the patent application scope, wherein the shallow trench isolation structures are used to isolate the highly doped region having the first conductivity type from the second conductivity type The polysilicon layer. The diode with high electrostatic protection capability as described in item 1 of the patent application scope, wherein the second trenches are arranged in a matrix on the surface of the silicon base layer. The diode with high electrostatic protection capability as described in item 1 of the patent application scope, wherein the second trenches are arranged in a ring and concentrically on the surface of the silicon base layer. A method for forming a diode with high electrostatic protection capability includes: etching a silicon base layer having a first conductivity type to form a plurality of first trenches and a plurality of second trenches having the first conductivity In the silicon base layer of the type; filling the first trenches with a dielectric material to form a plurality of shallow trench isolation structures in the first trenches; and depositing a polysilicon material on the second trenches On a surface of the trench, a polysilicon layer is conformally formed on the surface of the second trenches. The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent scope, wherein the polysilicon material is the polysilicon material with a second conductivity type, so that the polysilicon layer becomes the second conductivity Type of this polysilicon layer. The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent application scope further includes: performing an ion implantation process on the polysilicon layer to dope the polysilicon layer, So that the polysilicon layer becomes the polysilicon layer with a second conductivity type. The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent application scope further includes: performing an ion implantation treatment on the silicon base layer to isolate the two adjacent shallow trenches A highly doped region with the first conductivity type is formed between the structures. The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent application scope, wherein the first trenches surround the second trenches. The method for forming a diode with high electrostatic protection capability as described in item 10 of the patent application scope, wherein the shallow trench isolation structures are used to isolate the highly doped region having the first conductivity type from the polysilicon layer . The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent application scope, wherein the second trenches are arranged in a matrix on the surface of the silicon base layer. The method for forming a diode with high electrostatic protection capability as described in item 7 of the patent application scope, wherein the second trenches are arranged in a ring and concentrically on the surface of the silicon base layer.

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