JP2012174999A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a resistance element obtaining a stable resistance value without receiving the influences of electric charges in the surrounding area while preventing the increase of a layout area and has no limitation on the polarity of the electric potential applied to a resistor, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device includes a resistance element 10 formed on a LOCOS oxide film 3 on a silicon substrate 1, and the resistance element 10 has: a polysilicon film for shielding 11 formed on the LOCOS oxide film 3; a silicon oxide film 13 formed on the polysilicon film for shielding 11; a polysilicon resistor 15 formed on the silicon oxide film 13; a first electrode 21 joined to one end part of the polysilicon resistor 15; a second electrode 22 joined to the other end part of the polysilicon resistor 15; and a third electrode 23 joined to the polysilicon film for shielding 11. One of the first electrode 21 and the second electrode 22 is electrically connected with a third electrode 23 through wiring 25.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. For example, the present invention relates to a semiconductor device having a polysilicon resistor, and more particularly to a technique for stabilizing the resistance value of a polysilicon resistor for the purpose of reducing a change in resistance value due to a peripheral potential.

  In a semiconductor integrated circuit, a desired electronic circuit is configured by combining elements such as a resistance element, a capacitor, and a transistor. For this reason, it is desirable that the characteristics of each element remain as small as possible. Taking a resistive element as an example, the resistance value of the resistive element changes is not preferable in constructing an electronic circuit. However, many resistance elements are made of polysilicon or a diffusion layer, and a potential difference is generated between the potential of the semiconductor substrate or the like in the periphery (upper surface or lower surface) and the potential of the resistance element. Then, the spread state of the depletion layer changes due to this potential difference, and the width of the conductive region varies. For this reason, the resistance value of the resistance element may change.

JP 2003-282725 A

  For example, FIG. 5 of Patent Document 1 (hereinafter referred to as Conventional Example 1) discloses a polysilicon resistor formed as a resistive element above a well region with a LOCOS oxide film interposed therebetween. In Conventional Example 1, even if the voltage applied to the polysilicon resistor is the same, the resistance value of the polysilicon resistor changes if the potential condition of each electrode connected to the polysilicon resistor is different.

  The conventional example 1 will be described in detail. As shown in FIGS. 7A and 7B, a polysilicon resistor 105 is formed on a silicon substrate 101 with a LOCOS oxide film 103 interposed therebetween. A first electrode 111 is formed at one end of the body 105, and a second electrode 112 is formed at the other end of the polysilicon resistor 105. Here, as shown in FIG. 7A, it is assumed that Condition 3 ′ applies +3 [V] to the first electrode 111 and 0 [V] to the second electrode 112. . Further, as shown in FIG. 7B, it is assumed that the condition 2 ′ is that +4 [V] is applied to the first electrode 111 and +1 [V] is applied to the second electrode.

In both condition 1 ′ and condition 2 ′, the potential difference between the first electrode 111 and the second electrode 112 is 3 [V]. However, paying attention to the depletion layer in the polysilicon resistor 105, the expansion of the depletion layer is larger in the condition 2 ′ than in the condition 1 ′. This is because the potential difference between the second electrode 112 and the silicon substrate 101 is larger in the condition 2 ′ than in the condition 1 ′.
As a result, the current path in the polysilicon resistor 105 is narrower in the condition 2 ′ than in the condition 1 ′, and the resistance value of the polysilicon resistor 105 is increased accordingly. That is, in the conventional example 1, the resistance value of the polysilicon resistor 105 depends on the electrode potential and is unstable (hereinafter referred to as a first problem).

As a solution to the first problem, there is a structure disclosed in FIG. 1 (hereinafter referred to as Conventional Example 2) of Patent Document 1 described above.
The conventional example 2 will be described in detail. As shown in FIGS. 8A and 8B, an N− type epitaxial layer 202 is formed on a P type semiconductor substrate 201, and the epitaxial layer 202 is separated from the element. An element is isolated from the surroundings by a region (not shown), and a resistance element includes a polysilicon resistor 205 formed above the epitaxial layer 202 via a LOCOS oxide film 203. One end is electrically connected to the epitaxial layer 202 through the second electrode 212, the wiring, and the third electrode 213.

  According to Conventional Example 2, the second electrode 212 and the epitaxial layer 202 are held at the same potential, and the potential difference between the first electrode 211 and the epitaxial layer 202 is independent of the potential of the first electrode 211. ) Keep the same value. For this reason, said 1st subject can be solved. However, in Conventional Example 2, the polarity of the potential that can be applied to the first electrode 211 and the second electrode 212 is limited.

  For concrete explanation, as shown in FIG. 8A, as condition 1 ″, +4 [V] is applied to the first electrode 211 and +1 [V] is applied to the second electrode 212. Thus, it is assumed that the potential difference between the first electrode 211 and the second electrode 212 is set to 3 [V]. At this time, the potential of the third electrode 213 is +1 [V], and the potential of the epitaxial layer 202 is also +1 [V]. Since the potential of the semiconductor substrate 201 is GND, that is, 0 [V], a reverse bias is applied to the PN junction between the N− type epitaxial layer 202 and the P type semiconductor substrate 201 and no substrate current flows. .

  On the other hand, as shown in FIG. 8B, as condition 2 ″, −4 [V] is applied to the first electrode 211, −1 [V] is applied to the second electrode 212, and Assume that the potential difference between the first electrode 211 and the second electrode 212 is set to 3 [V]. At this time, each potential of the third electrode 213 and the epitaxial layer 202 is −1 [V]. Since the potential of the semiconductor substrate 201 is 0 [V], a forward bias is applied to the PN junction between the N− type epitaxial layer 202 and the P type semiconductor substrate 201, and the substrate current flows. When the substrate current flows, the resistance value of the polysilicon resistor 205 becomes unstable.

  As described above, in Conventional Example 2, there is a limit to the polarity condition of the potential that can be applied to the polysilicon resistor 205 on the circuit. A bias may be applied. For this reason, Conventional Example 2 has a problem (hereinafter referred to as a second problem) that it is unsuitable for a circuit in which a negative potential is applied to the polysilicon resistor 205, for example.

Furthermore, in Conventional Example 2, it is necessary to provide an element isolation region such as STI (Shallow Trench Isolation) on the outer periphery of the epitaxial layer 202 in order to electrically isolate the epitaxial layer 202 provided on the substrate from other regions. For this reason, there is also a problem (third problem) that the layout area of the resistor element including the polysilicon resistor 205 and the epitaxial layer 202 increases.
Accordingly, the present invention has been made in view of the above first to third problems, and a resistance element has a stable resistance value without being influenced by peripheral charges while preventing an increase in layout area. Another object of the present invention is to provide a semiconductor device that can be obtained and has no limitation on the polarity of the potential that can be applied to the resistor, and a manufacturing method thereof.

  In order to solve the above problems, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, and a resistor formed over the first insulating film. An element, and the resistance element includes a conductor formed on the first insulating film, a second insulating film formed on the conductor, and the second A resistor formed on the insulating film, a first electrode bonded to the resistor, a second electrode bonded to the resistor at a position away from the first electrode, and the conductive A third electrode bonded to the body, wherein one of the first electrode and the second electrode is electrically connected to the third electrode through a wiring. Features.

  In such a configuration, since one of the first electrode and the second electrode has the same potential as the third electrode, the depletion layer in the resistor has the first electrode, the second electrode, If the potential difference (i.e., voltage condition) is the same, the voltage is constant regardless of the potential of each electrode. For this reason, it is possible to obtain a stable resistance value of the resistor without being affected by peripheral charges. In addition, since the resistor is shielded by a conductor that is electrically separated from the semiconductor substrate by the first insulating film, a current path such as a PN junction is generated between the conductor and the semiconductor substrate. Absent. For this reason, there is no restriction | limiting in the polarity of the electric potential which can be applied to a resistor. Furthermore, since it is not necessary to provide an element isolation layer on the outer periphery of the resistance element, an increase in layout area can be prevented.

  The “semiconductor substrate” of the present invention corresponds to, for example, a silicon substrate 1 described later. As the “first insulating film”, for example, a LOCOS oxide film 3 described later corresponds. As the “conductor”, for example, a shielding polysilicon film 11 described later corresponds. As the “second insulating film”, for example, a silicon oxide film 13 described later corresponds. As the “resistor”, for example, a polysilicon resistor 15 described later corresponds.

  The semiconductor device may further include a capacitor element formed on the first insulating film, the capacitor element being formed on the lower electrode and the lower electrode formed on the insulating film. A third insulating film and an upper electrode formed on the third insulating film, wherein the lower electrode and the conductor are each composed of a first polysilicon film, and the second electrode The insulating film and the third insulating film may each be composed of a first silicon oxide film, and the upper electrode and the resistor may be each composed of a second polysilicon film.

  With such a configuration, it is possible to simultaneously form the resistor element and the capacitor element while using the manufacturing process. Thereby, the increase in the number of processes can be prevented. For example, a conductor and a lower electrode can be formed simultaneously by forming a first polysilicon film and patterning it using photolithography and etching techniques. Further, for example, the second insulating film and the third insulating film can be simultaneously formed by thermally oxidizing the first polysilicon to form the first silicon oxide film. Further, the resistor and the upper electrode can be formed at the same time by forming a second polysilicon film and patterning it using photolithography and etching techniques.

  The “capacitance element” of the present invention corresponds to, for example, an IPO capacitor 30 described later. As the “third insulating film”, for example, a silicon oxide film 14 to be described later corresponds. As the “first polysilicon film”, for example, a polysilicon film 11 ′ described later corresponds. As the “second polysilicon film”, for example, a polysilicon film 15 ′ described later corresponds.

A manufacturing method of a semiconductor device according to still another aspect of the present invention includes a step of forming a resistance element on a semiconductor substrate via a first insulating film, and the step of forming the resistance element includes the first step. A step of forming a conductor on the insulating film; a step of forming a second insulating film on the conductor; a step of forming a resistor on the second insulating film; Bonding the second electrode to the resistor, bonding the second electrode to the resistor at a position away from the first electrode, bonding the third electrode to the conductor, and the first And one of the second electrode and the second electrode is electrically connected to the third electrode through a wiring.
With such a method, as described above, it is possible to obtain a stable resistance value without being affected by peripheral charges while preventing an increase in the layout area of the resistive element, and applying it to the resistor. A semiconductor device in which the polarity of the potential that can be generated is not limited can be manufactured.

  According to the present invention, it is possible to obtain a stable resistance value without being influenced by peripheral charges while preventing an increase in the layout area of the resistance element, and it is possible to limit the polarity of the potential that can be applied to the resistor. Semiconductor device and method for manufacturing the same can be provided.

1 is a diagram illustrating a configuration example of a semiconductor device 100 according to a first embodiment. The figure which shows the relationship between the electrode potential in the resistive element 10, and the breadth of a depletion layer. FIG. 10 is a diagram illustrating another configuration example of the semiconductor device 100. The figure which shows the structural example of the semiconductor device 200 which concerns on 2nd Embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device 200 (part 1); FIG. 6 is a diagram (No. 2) illustrating a method for manufacturing the semiconductor device 200; The figure for demonstrating the subject of the prior art example 1. FIG. The figure for demonstrating the subject of the prior art example 2. FIG.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof may be omitted.
(1) First Embodiment FIGS. 1A and 1B are diagrams showing a configuration example of a semiconductor device 100 according to a first embodiment of the present invention. 1A is a cross-sectional view of FIG. 1B cut along the line XX ′, and FIG. 1B is a plan view.
As shown in FIGS. 1A and 1B, the semiconductor device 100 includes a silicon substrate 1, a LOCOS oxide film 3 formed on the silicon substrate 1, and a resistance element formed on the LOCOS oxide film 3. 10. The silicon substrate 1 is, for example, a P-type bulk silicon substrate (P-Sub). The LOCOS oxide film 3 is a silicon oxide film formed by the LOCOS method.

  The resistance element 10 is formed on the shielding polysilicon film 11 formed on the LOCOS oxide film 3, the silicon oxide film 13 formed on the shielding polysilicon film 11, and the silicon oxide film 13. A polysilicon resistor 15. The shielding polysilicon film 11 is a polysilicon film formed by, for example, a CVD (Chemical Vapor Deposition) method. The shielding polysilicon film 11 is doped with a P-type impurity such as boron or an N-type impurity such as phosphorus or arsenic, and has a predetermined conductivity. The thickness of the shielding polysilicon film 11 is, for example, 150 to 400 nm. The silicon oxide film 13 is formed, for example, by thermally oxidizing the shielding polysilicon film 11 (or by the CVD method), and has a thickness of, for example, 10 to 50 nm. The polysilicon resistor 15 is a polysilicon film formed by, for example, a CVD method. The polysilicon resistor 15 is added with the P-type impurity or the N-type impurity as described above, and has a predetermined conductivity. The thickness of the polysilicon resistor 15 is, for example, 150 to 400 nm.

  The resistance element 10 includes a first electrode 21 bonded to the polysilicon resistor 15, a second electrode 22 bonded to the polysilicon resistor 15 at a position away from the first electrode 21, And a third electrode 23 bonded to the shielding polysilicon film 11. For example, as shown in FIGS. 1A and 1B, the first electrode 21 is bonded to one end of the upper surface of the polysilicon resistor 15. The second electrode 22 is joined to the other end of the upper surface of the polysilicon resistor 15. Further, the third electrode 23 is joined to the portion of the upper surface of the shielding polysilicon film 11 that is out of the polysilicon resistor 15 (that is, the portion not covered with the polysilicon resistor 15). Yes.

  Although not shown in FIGS. 1A and 1B, the shielding polysilicon film 11, the silicon oxide film 13, and the polysilicon resistor 15 are covered with an interlayer insulating film. The upper surfaces of the first electrode 21, the second electrode 22, and the third electrode 23 are exposed on the interlayer insulating film. In this example, the second electrode 22 and the third electrode 23 are electrically connected through the wiring 25 formed on the interlayer insulating film. The first electrode 21, the second electrode 22, and the third electrode 23 are, for example, a contact electrode formed of a low melting point metal such as aluminum or a plug electrode formed of a high melting point metal such as tungsten. It is. The wiring 25 is made of, for example, aluminum or an alloy thereof, or copper.

Incidentally, in the resistance element 10 shown in FIGS. 1A and 1B, the resistance value of the polysilicon resistor 15 is the potential difference between the first electrode 21 and the second electrode 22 (that is, voltage condition). Are the same regardless of the potentials of the first electrode 21 and the second electrode 22. This will be described below.
2A and 2B are cross-sectional views showing the relationship between the electrode potential in the resistance element 10 and the spread of the depletion layer. Here, for specific description, as shown in FIG. 2A, as condition 1, +3 [V] is applied to the first electrode 21 and 0 [V] is applied to the second electrode 12. Assume that the potential difference between the first electrode 21 and the second electrode 22 is set to 3 [V]. Further, as shown in FIG. 2B, as condition 2, +4 [V] is applied to the first electrode 21, +1 [V] is applied to the second electrode 12, and the first electrode 21 is applied. Assume that the potential difference between the first electrode 22 and the second electrode 22 is set to 3 [V].

  Under the condition 1 shown in FIG. 2A, the potential of the shielding polysilicon film 11 is maintained at 0 [V], which is the same as the potential of the second electrode 22. The potential of the shielding polysilicon film 11 and the potential of the silicon substrate 1 are both 0 [V], and there is no potential difference between them. For this reason, a depletion layer does not occur in the portion of the shielding polysilicon film 11 on the LOCOS oxide film 3 side. The depletion layer is generated only in the silicon oxide film 13 side in the shielding polysilicon film 11.

  On the other hand, under the condition 2 shown in FIG. 2B, the potential of the shielding polysilicon film 11 is held at +1 [V], which is the same as the potential of the second electrode 22. A potential difference of 1 [V] is generated between the shielding polysilicon film 11 and the silicon substrate 1. For this reason, a depletion layer is also formed in the portion of the shielding polysilicon film 11 on the LOCOS oxide film 3 side. In addition, a depletion layer is also generated at the site on the silicon oxide film 13 side in the shielding polysilicon film 11.

  However, focusing on the potential difference between the polysilicon resistor 15 and the shielding polysilicon film 11 under both conditions 1 and 2, the potential difference between them is 0 [V] to 3 [V], and the potential gradient Are the same. In other words, the spread of the depletion layer inside the polysilicon resistor 15 is the same for both conditions 1 and 2, and even if the condition 1 is changed to the condition 2 (or the condition 2 is changed to the condition 1) ) The spread of the depletion layer does not change. This means that the resistance value of the polysilicon resistor 15 is stable without depending on the electrode potential. Compared to the conventional example 1, the resistance value is stable without depending on the electrode potential, and a stable resistance value can be obtained without being affected by the peripheral charges.

  In the semiconductor device 100, a LOCOS oxide film 3 is interposed between the silicon substrate 1 and the shielding polysilicon film 11, and the LOCOS oxide film 3 allows the silicon substrate 1 and the shielding polysilicon film 11 to be connected. Are electrically insulated. For this reason, a current path does not occur regardless of whether the potential of the second electrode 22 is positive or negative. For example, there is no need to consider the concentration profile in the silicon substrate 1 in order to suppress the substrate current. . Compared to Conventional Example 2, it can be said that there is no limit to the polarity of the potential that can be applied to the polysilicon resistor 15.

Further, in the semiconductor device 100, the LOCOS oxide film 3 exists below the resistance element 10, and the upper side and the periphery thereof are covered and surrounded by the interlayer insulating film. For this reason, it is not necessary to provide an element isolation layer such as STI on the outer periphery of the resistance element 10 as compared with the conventional example 2, and an increase in layout area can be prevented.
As described above, according to the first embodiment of the present invention, it is possible to obtain a stable resistance value of the resistance element 10 without being influenced by peripheral charges, while preventing an increase in layout area. It is possible to realize a semiconductor device in which the polarity of potential that can be applied to the silicon resistor 15 is not limited.

  In the first embodiment, the case where the second electrode 22 on the low potential side is electrically connected to the third electrode 23 has been described. However, in the present invention, for example, as shown in FIG. 3, the first electrode 21 on the high potential side instead of the low potential side may be electrically connected to the third electrode 23 via the wiring 25. . Even in such a case, the same effect can be obtained by the same mechanism as described above.

  In the first embodiment, the case where the shielding polysilicon film (that is, the conductive polysilicon film) is used as the “conductor” of the present invention has been described. However, the “conductor” in the present invention is not limited to polysilicon. The “conductor” may be, for example, amorphous silicon, or a semiconductor other than silicon such as GaAs. Alternatively, the “conductor” may be a metal film having higher conductivity instead of a semiconductor. Examples of the metal film include aluminum or an alloy thereof, titanium, nickel, and copper.

(2) Second Embodiment The resistance element of the present invention has the same vertical structure as an IPO (Inter Poly Oxide) capacitor. Therefore, the resistance element and the IPO capacitor can be mixedly mounted on the same substrate, and the resistance element and the IPO capacitor can be simultaneously formed while using the manufacturing process. In the second embodiment, this point will be described.

  FIG. 4 is a cross-sectional view showing a configuration example of a semiconductor device 200 according to the second embodiment of the present invention. As shown in FIG. 4, the semiconductor device 200 includes a resistance element 10 and an IPO capacitor 30. Among these, the IPO capacitor 30 includes a lower electrode 12 formed on the LOCOS oxide film 3, a silicon oxide film 14 formed on the lower electrode 12, and an upper electrode 16 formed on the silicon oxide film 14. And having. The lower electrode 12 is a polysilicon film formed by, for example, a CVD method. The lower electrode 12 is doped with a P-type impurity such as boron or an N-type impurity such as phosphorus or arsenic, and has a predetermined conductivity. The thickness of the lower electrode 12 is the same as the thickness of the shielding polysilicon film 11 included in the resistance element 10.

  The silicon oxide film 14 is formed by, for example, thermally oxidizing the lower electrode 12 (or by a CVD method). The thickness of the silicon oxide film 14 is the same as the thickness of the silicon oxide film 13 included in the resistance element 10. The upper electrode 16 is a polysilicon film formed by, for example, a CVD method. The upper electrode 16 is doped with a P-type impurity or an N-type impurity as described above, and has predetermined conductivity. The thickness of the upper electrode 16 is the same as the thickness of the polysilicon resistor 15 included in the resistance element 10.

  The IPO capacitor 30 includes a fourth electrode 34, a fifth electrode 35, a sixth electrode 36, and a seventh electrode 37. The fourth electrode 34 is joined to one end of the upper surface of the upper electrode 16. The fifth electrode 35 is joined to the other end of the upper surface of the upper electrode 16. In addition, the sixth electrode 36 is joined to one end portion on the upper surface of the lower electrode 12 and at a position deviated from directly below the upper electrode 16. The seventh electrode 37 is joined to the other end portion on the upper surface of the lower electrode 12 and at a position off from directly below the upper electrode 16.

  Although not shown in FIG. 4, the IPO capacitor 30 configured as described above is covered with an interlayer insulating film, and the upper surfaces of the fourth electrode 34, the fifth electrode 35, the sixth electrode 36, and the seventh electrode 37. Are exposed on the interlayer insulating film. In this example, the fourth electrode 34 and the fifth electrode 35 are electrically connected via the wiring 38 formed on the interlayer insulating film. Further, the sixth electrode 36 and the seventh electrode 37 are electrically connected through the wiring 39 formed on the interlayer insulating film.

  The fourth electrode 34, the fifth electrode 35, the sixth electrode 36, and the seventh electrode 37 are, for example, a contact electrode formed of a low melting point metal such as aluminum or a high melting point metal such as tungsten. It is a plug electrode formed by. The wirings 38 and 39 are made of, for example, aluminum or an alloy thereof, or copper. Next, a method for manufacturing the semiconductor device 200 will be described.

FIG. 5A to FIG. 6B are cross-sectional views illustrating a method for manufacturing a semiconductor device 200 according to the second embodiment of the present invention.
As shown in FIG. 5A, after the LOCOS oxide film 3 is formed on the silicon substrate 1, a polysilicon film 11 'is formed on the LOCOS oxide film 3 by, eg, CVD. Next, P-type impurities or N-type impurities are introduced into the polysilicon film 11 ′ by, for example, an ion implantation technique, so that the polysilicon film 11 ′ has predetermined conductivity. Next, as shown in FIG. 5B, this polysilicon film 11 'is thermally oxidized, for example, to form a silicon oxide film 13'. Further, a polysilicon film 15 ′ is formed on the silicon oxide film 13 ′ by, eg, CVD. Then, for example, by using an ion implantation technique, a P-type impurity or an N-type impurity is introduced into the polysilicon film 15 ′ to give the polysilicon film 15 ′ predetermined conductivity.

  Note that the introduction process of P-type impurities or N-type impurities into the polysilicon films 11 ′ and 15 ′ shown in FIG. 5A or 5B is not an ion implantation technique but a film formation process (that is, in). -Situ). In addition, in the impurity introduction step, for example, the dose amount of the impurity with respect to the resistance element formation region and the dose amount with respect to the capacitor formation region may be made different by combining a photolithography technique and an ion implantation technique. The impurity species to be implanted may be made different in each region by the same method. As a result, the resistance values of the shielding polysilicon film 11 and the lower electrode 12 formed of the same polysilicon film 11 ′ can be set to different values. Also, the resistance values of the polysilicon resistor 15 and the upper electrode 16 formed of the same polysilicon film 15 'can be set to different values.

  Next, as shown in FIG. 5C, a resist pattern 41 is formed on the polysilicon film 15 'by, for example, photolithography. Then, using this resist pattern 41 as a mask, the polysilicon film 15 'is etched. As a result, as shown in FIG. 5D, the polysilicon resistor 15 is formed in the resistance element formation region, and at the same time, the upper electrode 16 is formed in the capacitor formation region. After the polysilicon resistor 15 and the upper electrode 16 are formed, the resist pattern 41 shown in FIG. 5C is removed.

  Next, as shown in FIG. 6A, resist patterns 42 each having a shape covering the polysilicon resistor 15 and the upper electrode 16 are formed by, for example, photolithography. Then, using the resist pattern 42 as a mask, the silicon oxide film 13 'and the polysilicon film 11' are sequentially etched. As a result, as shown in FIG. 6B, the silicon oxide film 13 is formed in the resistance element formation region, and at the same time, the silicon oxide film 14 is formed in the capacitor formation region. Further, simultaneously with the formation of the shielding polysilicon film 11 in the resistance element formation region, the lower electrode 12 is formed in the capacitor formation region.

  Next, as shown in FIG. 6C, an interlayer insulating film 45 is formed on the entire upper surface of the silicon substrate 1 by, eg, CVD. Then, contact holes are formed in the interlayer insulating film by using a photolithography technique and an etching technique. Subsequently, a metal film is deposited so as to fill the contact hole by, for example, a sputtering method, and the deposited metal film is ground by, for example, a CMP method. Thereby, as shown in FIG.6 (c), the 1st electrode 21-the 7th electrode 37 are formed. Thereafter, wiring is formed, and the semiconductor device 200 shown in FIG. 4 is completed.

  As described above, according to the second embodiment of the present invention, the resistance element 10 and the IPO capacitor 30 can be simultaneously formed while using the manufacturing process. For example, by forming a polysilicon film 11 ′ and patterning it using photolithography and etching techniques, the shielding polysilicon film 11 and the lower electrode 12 can be formed simultaneously. Further, for example, the silicon oxide film 13 of the resistance element 10 and the silicon oxide film 14 of the IPO capacitor 30 can be simultaneously formed by thermally oxidizing the polysilicon 11 ′ (or by CVD). Further, the polysilicon resistor 15 and the upper electrode 16 can be formed simultaneously by forming a polysilicon film 15 'and patterning it using photolithography and etching techniques. Thereby, the increase in the number of processes can be prevented.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 LOCOS oxide film 10 Resistor element 11 Shielding polysilicon film 12 Lower electrode 11 ', 15' Polysilicon film 13, 14 Silicon oxide film 15 Polysilicon resistor 16 Upper electrode 21, 23, 34-37 Electrode 25, 37, 38 Wiring 30 IPO capacitors 41, 42 Resist pattern 45 Interlayer insulating film 100, 200 Semiconductor device

Claims (3)

A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A resistance element formed on the first insulating film, and a semiconductor device comprising:
The resistance element is
A conductor formed on the first insulating film;
A second insulating film formed on the conductor;
A resistor formed on the second insulating film;
A first electrode joined to the resistor;
A second electrode joined to the resistor at a position away from the first electrode;
A third electrode bonded to the conductor,
One of the first electrode and the second electrode is electrically connected to the third electrode through a wiring. A capacitive element formed on the first insulating film,
The capacitive element is
A lower electrode formed on the insulating film;
A third insulating film formed on the lower electrode;
An upper electrode formed on the third insulating film,
The lower electrode and the conductor are each composed of a first polysilicon film,
The second insulating film and the third insulating film are each composed of a first silicon oxide film,
2. The semiconductor device according to claim 1, wherein each of the upper electrode and the resistor is made of a second polysilicon film. Forming a resistance element on a semiconductor substrate via a first insulating film,
The step of forming the resistance element includes:
Forming a conductor on the first insulating film;
Forming a second insulating film on the conductor;
Forming a resistor on the second insulating film;
Bonding a first electrode to the resistor;
Bonding a second electrode to the resistor at a position away from the first electrode;
Bonding a third electrode to the conductor;
And a step of electrically connecting one of the first electrode and the second electrode to the third electrode through a wiring.

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