JP4276118B2 - Semiconductor device - Google Patents

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JP4276118B2
JP4276118B2 JP2004102505A JP2004102505A JP4276118B2 JP 4276118 B2 JP4276118 B2 JP 4276118B2 JP 2004102505 A JP2004102505 A JP 2004102505A JP 2004102505 A JP2004102505 A JP 2004102505A JP 4276118 B2 JP4276118 B2 JP 4276118B2
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智則 林
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New Japan Radio Co Ltd
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本発明は静電破壊保護素子を備えた半導体装置に関し、特に大電流が流れた場合でも破損しない静電破壊保護素子を備えた半導体装置に関する。   The present invention relates to a semiconductor device including an electrostatic breakdown protection element, and more particularly to a semiconductor device including an electrostatic breakdown protection element that is not damaged even when a large current flows.

一般に半導体装置は、静電気による破壊を受けやすい。そのため、入出力電極と内部回路との間には、静電破壊保護素子を備えるのが一般的である(特許文献1参照)。   In general, semiconductor devices are easily damaged by static electricity. For this reason, an electrostatic breakdown protection element is generally provided between the input / output electrode and the internal circuit (see Patent Document 1).

この種の静電破壊保護素子の一例を図2(a)に示す。図2(a)において、1はP型半導体基板、2はコレクタ領域の一部を構成するN+型埋込層、3は分離領域の一部を構成するP+型埋込層、4はN型エピタキシャル層、5はLOCOS酸化膜、6はP+型埋込層3と共に分離領域を構成するP型拡散層、7はN+型埋込層2と共にコレクタ領域の一部を構成するN型コレクタ領域、8はP型ベース領域、9はN型エミッタ領域、10は酸化膜、11は層間絶縁膜、12a、12bはアルミニウム配線、13はP+型拡散層を示している。 An example of this type of electrostatic breakdown protection element is shown in FIG. In FIG. 2A, 1 is a P-type semiconductor substrate, 2 is an N + type buried layer constituting a part of the collector region, 3 is a P + type buried layer constituting a part of the isolation region, N-type epitaxial layer, 5 is a LOCOS oxide film, 6 is a P-type diffusion layer that forms an isolation region together with P + -type buried layer 3, and 7 is an N-type that forms part of a collector region together with N + -type buried layer 2 The reference numeral 8 denotes a P-type base region, 9 denotes an N-type emitter region, 10 denotes an oxide film, 11 denotes an interlayer insulating film, 12a and 12b denote aluminum wirings, and 13 denotes a P + -type diffusion layer.

図2(a)に示す静電破壊保護素子は、内部回路を構成するNPNバイポーラトランジスタと同時形成される。まず、P型半導体基板1上にコレクタ領域の一部を構成するN+型埋込層2と分離領域の一部を構成するP+型埋込層3を形成するため、イオン注入し、拡散を行う。その後、N型エピタキシャル層4を成長させ、N+型埋込層2とP+型埋込層3を形成する。N型エピタキシャル層4表面から不純物イオンを注入し、先に形成したP+型埋込層3に達するP型拡散層6を形成することで、分離領域を形成する。LOCOS酸化膜5を形成した後、コレクタ領域形成予定領域に不純物イオンを注入し、先に形成したN+型埋込層2に達するN型コレクタ領域7を形成し、コレクタ領域を形成する。次に表面に酸化膜10を形成する。ベース領域形成予定領域に不純物イオンを注入し、P型ベース領域8を形成する。同様に、エミッタ領域形成予定領域に、酸化膜10を通して不純物イオンを注入し、N型エミッタ領域9を形成する。P型ベース領域8に接続するベース取り出し領域を形成するため、不純物イオンを注入し、P+型拡散層13を形成する。層間絶縁膜11を形成した後、N型コレクタ領域7、N型エミッタ領域9、P+型拡散層13上の酸化膜10を除去し、N型コレクタ領域7に接続するアルミニウム配線12a、P型ベース領域8及びN型エミッタ領域9に接続するアルミニウム配線12bを形成する。アルミニウム配線12aは電源電圧電位(Vcc)に、アルミニウム配線12bは接地電位に接続し、静電保護素子を完成する。 The electrostatic breakdown protection element shown in FIG. 2A is formed simultaneously with the NPN bipolar transistor constituting the internal circuit. First, in order to form the N + type buried layer 2 constituting a part of the collector region and the P + type buried layer 3 constituting a part of the isolation region on the P type semiconductor substrate 1, ions are implanted and diffused. I do. Thereafter, an N type epitaxial layer 4 is grown, and an N + type buried layer 2 and a P + type buried layer 3 are formed. Impurity ions are implanted from the surface of the N-type epitaxial layer 4 to form a P-type diffusion layer 6 that reaches the previously formed P + -type buried layer 3, thereby forming an isolation region. After the LOCOS oxide film 5 is formed, impurity ions are implanted into the region where the collector region is to be formed, and an N-type collector region 7 reaching the N + -type buried layer 2 formed earlier is formed, thereby forming a collector region. Next, an oxide film 10 is formed on the surface. Impurity ions are implanted into the base region formation planned region to form the P-type base region 8. Similarly, impurity ions are implanted into the emitter region formation planned region through the oxide film 10 to form the N-type emitter region 9. In order to form a base extraction region connected to the P-type base region 8, impurity ions are implanted to form a P + -type diffusion layer 13. After forming the interlayer insulating film 11, the oxide film 10 on the N-type collector region 7, the N-type emitter region 9, and the P + -type diffusion layer 13 is removed, and an aluminum wiring 12 a connected to the N-type collector region 7, P-type An aluminum wiring 12b connected to the base region 8 and the N-type emitter region 9 is formed. The aluminum wiring 12a is connected to the power supply voltage potential (Vcc), and the aluminum wiring 12b is connected to the ground potential to complete the electrostatic protection element.

このような構造の静電破壊保護素子では、N型コレクタ領域7を接続したアルミニウム配線12aに強い負電圧が印加した場合、N型エピタキシャル層4とP+型拡散層13とのPN接合の順方向に電流が流れ、電荷はP+型拡散層13とN型エミッタ領域9を短絡させて接地したアルミニウム配線12b側に排出される。この場合、PN接合は順方向特性となり、静電保護素子の破壊電流は十分大きく、PN接合に大電流が流れても、静電保護素子が破壊されることはない。 In the electrostatic breakdown protection element having such a structure, when a strong negative voltage is applied to the aluminum wiring 12a connected to the N-type collector region 7, the order of the PN junction between the N-type epitaxial layer 4 and the P + -type diffusion layer 13 is increased. A current flows in the direction, and the electric charge is discharged to the side of the aluminum wiring 12b grounded by short-circuiting the P + -type diffusion layer 13 and the N-type emitter region 9. In this case, the PN junction has forward characteristics, the breakdown current of the electrostatic protection element is sufficiently large, and even if a large current flows through the PN junction, the electrostatic protection element is not destroyed.

一方、N型コレクタ領域を接続したアルミニウム配線12aに強い正電圧が印加した場合の電流電圧特性を図2(b)に示す。上述の負電圧が印加したときと異なり、印加電圧が上昇するに従い、PN接合の逆方向電流が徐々に増加し、N+型埋込層2に逆方向電流が流れ込み、電圧降下によって、P型ベース領域8の電位は上昇する。この電位が図2(b)のアバランシュ・ブレイクダウン現象を発生させる電圧V2に達すると、その瞬間、NPN型バイポーラトランジスタがオンし、P+型拡散層13とN型エピタキシャル層4間を大電流が通過し、接地に電荷を排出する構成となっている。
特開2001−144191号
On the other hand, FIG. 2B shows current-voltage characteristics when a strong positive voltage is applied to the aluminum wiring 12a connected to the N-type collector region. Unlike the case where the negative voltage is applied, the reverse current of the PN junction gradually increases as the applied voltage increases, and the reverse current flows into the N + -type buried layer 2. The potential of the base region 8 rises. When this potential reaches the voltage V2 that causes the avalanche breakdown phenomenon of FIG. 2B, the NPN bipolar transistor is turned on at that moment, and a large current flows between the P + -type diffusion layer 13 and the N-type epitaxial layer 4. Passes, and the electric charge is discharged to the ground.
JP 2001-144191 A

図2(a)に示す構造の静電破壊保護素子において、N型エミッタ領域9周囲の抵抗値が高く、電流が流れにくい。そのため、アバランシュ・ブレイクダウン現象が発生し大電流が通過するとき、N型エミッタ領域9周囲の電流通路で高熱が発生し、静電破壊保護素子が破壊してしまうという問題があった。静電破壊保護素子の破壊を防ぐため、エミッタ面積を大きくしても、N型エミッタ領域9周囲の抵抗値が高く、電流が流れにくく、静電破壊保護素子の破壊を防ぐことができなかった。そこで本発明は、大電流が発生しても破壊することのない静電破壊保護素子を備えた半導体装置を提供することを目的とする。   In the electrostatic breakdown protection element having the structure shown in FIG. 2A, the resistance value around the N-type emitter region 9 is high and current does not easily flow. Therefore, when an avalanche breakdown phenomenon occurs and a large current passes, high heat is generated in the current path around the N-type emitter region 9 and the electrostatic breakdown protection element is destroyed. In order to prevent the destruction of the electrostatic discharge protection element, even if the emitter area is increased, the resistance value around the N-type emitter region 9 is high, the current does not flow easily, and the breakdown of the electrostatic discharge protection element cannot be prevented. . Therefore, an object of the present invention is to provide a semiconductor device including an electrostatic breakdown protection element that does not break down even when a large current is generated.

上記目的を解決するため本発明は、一導電型のエピタキシャル層が形成された半導体基板上に、該半導体基板と前記エピタキシャル層との間の一導電型の埋込層と前記エピタキシャル層表面から前記埋込層に達する一導電型の拡散層で構成されるコレクタ領域と、前記エピタキシャル層表面に形成された逆導電型の拡散領域からなるベース領域と、該ベース領域表面に形成された一導電型の拡散領域からなるエミッタ領域と、該エミッタ領域と前記ベース領域とを接続する第1の電極と、前記コレクタ領域に接続する第2の電極とからなる静電破壊保護素子を備え、内部回路を静電破壊から保護する半導体装置において、前記ベース領域に接し、前記エミッタ領域を取り囲むように配置した、前記ベース領域より不純物濃度が高く、一部が前記エピタキシャル層と接した、一導電型の高濃度領域を備え、前記第1の電極及び前記第2の電極間の印加電圧が上昇したとき、前記静電破壊保護素子の前記高濃度領域と前記エピタキシャル層とで構成するPN接合に電流を流し、前記第1の電極及び前記第2の電極間の印加電位がさらに上昇し、前記ベース領域に印加する電位が上昇したとき、前記静電破壊保護素子の前記エミッタ領域と前記ベース領域とで構成するPN接合に電流を流すことを特徴とするものである。 In order to solve the above-described object, the present invention provides a semiconductor substrate on which a one-conductivity type epitaxial layer is formed, the one-conductivity type buried layer between the semiconductor substrate and the epitaxial layer, and the surface of the epitaxial layer. A collector region composed of a diffusion layer of one conductivity type reaching the buried layer, a base region composed of a diffusion region of reverse conductivity type formed on the surface of the epitaxial layer, and a conductivity type formed on the surface of the base region An electrostatic breakdown protection element comprising an emitter region composed of a diffusion region, a first electrode connecting the emitter region and the base region, and a second electrode connected to the collector region, in the semiconductor device to be protected from electrostatic breakdown, the base region in contact with the disposed so as to surround the emitter region, the base region impurity concentration rather higher than, partially pre In contact with the epitaxial layer comprises a heavily doped region of the one conductivity type, wherein, when the first electrode and the voltage applied between the second electrode is increased, the epitaxial and the high concentration region of the electrostatic discharge protection element When an electric current is passed through a PN junction composed of a layer, the applied potential between the first electrode and the second electrode further increases, and the potential applied to the base region increases, the electrostatic breakdown protection element A current is passed through a PN junction formed by the emitter region and the base region.

本発明の半導体装置は、コレクタ領域に大きな正の電圧が印加したとき、アバランシェ・ブレイクダウンが起こるまで電圧が上昇し、ベース領域とエミッタ領域で構成するPN接合に電流を流すことにより、高熱が発生しない構造とした。その結果、熱起因による静電破壊保護素子の破壊を防止することができる。また高熱が発生しないため、PN接合間に流れる電流値を大きくすることができる。   In the semiconductor device of the present invention, when a large positive voltage is applied to the collector region, the voltage rises until avalanche breakdown occurs, and a current flows through the PN junction composed of the base region and the emitter region. The structure does not occur. As a result, it is possible to prevent destruction of the electrostatic breakdown protection element due to heat. Further, since no high heat is generated, the value of the current flowing between the PN junctions can be increased.

本願発明の静電破壊保護素子は、上述のように静電気などの急激な電位変化に対し、高濃度領域とエミッタ領域との間に大電流を流すことができるように、エミッタ領域の近傍に、ベース領域より不純物濃度の高い高濃度領域を、エミッタ領域を取り囲み、その一部がエピタキシャル層と接するように配置している。以下本願発明に関して詳細に説明する。 In the electrostatic breakdown protection element of the present invention, as described above, in the vicinity of the emitter region, a large current can flow between the high concentration region and the emitter region with respect to a rapid potential change such as static electricity. high high-concentration region impurity concentration than the base region, enclose take emitter region, a portion is placed in contact with the epitaxial layer. Hereinafter, the present invention will be described in detail.

図1に、本願発明に係る静電破壊保護素子をNPN型バイポーラトランジスタで構成した断面図を示す。本発明に係る静電破壊保護素子は、次のように形成することができる。まずP型半導体基板1上に、コレクタ領域の一部を構成するN+型埋込層2、分離領域の一部を構成するP+型埋込層3を形成するため、不純物イオンを注入する。その後、N型エピタキシャル層4を厚さ5μm程度成長させる。先に形成したP+型埋込層3に接続するP型拡散層6を形成し、素子分離層を形成する。さらにN型エピタキシャル層4の表面にLOCOS酸化膜5を形成する。その後、N+型埋込層2に達するN型コレクタ領域7を形成する。次に、P型ベース領域8を形成する。 FIG. 1 shows a cross-sectional view in which an electrostatic breakdown protection element according to the present invention is formed of an NPN bipolar transistor. The electrostatic breakdown protection element according to the present invention can be formed as follows. First, impurity ions are implanted on the P-type semiconductor substrate 1 to form an N + -type buried layer 2 constituting a part of the collector region and a P + -type buried layer 3 constituting a part of the isolation region. . Thereafter, the N-type epitaxial layer 4 is grown to a thickness of about 5 μm. A P-type diffusion layer 6 connected to the previously formed P + -type buried layer 3 is formed, and an element isolation layer is formed. Further, a LOCOS oxide film 5 is formed on the surface of the N type epitaxial layer 4. Thereafter, an N type collector region 7 reaching the N + type buried layer 2 is formed. Next, the P-type base region 8 is formed.

露出する表面に酸化膜10を形成した後、N型エミッタ領域9を形成する。次にP+型の高濃度不純物層14を形成する。高濃度不純物層14は、N型エミッタ領域9の端部から1μm程度離れた周辺にその端部を配置し、N型エミッタ領域9の周囲を取り囲むように形成する。また高濃度不純物層14の一部は、N型コレクタ領域7側のN型エピタキシャル層4と接するように配置する。 After forming the oxide film 10 on the exposed surface, the N-type emitter region 9 is formed. Next, a P + type high concentration impurity layer 14 is formed. The high-concentration impurity layer 14 is formed so as to surround the periphery of the N-type emitter region 9, with the end portion disposed around 1 μm away from the end portion of the N-type emitter region 9. The part of the high concentration impurity layer 14, placed in contact with the N-type epitaxial layer 4 of the N-type collector region 7 side.

その後、層間絶縁膜11を全面に形成し、N型コレクタ領域7、高濃度不純物層14及びN型エミッタ領域9表面を露出し、それぞれに接続するアルミニウム配線12a、12bを形成する。アルミニウム配線12aは電源電圧電位(Vcc)に、アルミニウム配線12bは接地電位にそれぞれ接続し、静電破壊保護素子を完成する。   Thereafter, an interlayer insulating film 11 is formed on the entire surface, and the surfaces of the N-type collector region 7, the high-concentration impurity layer 14, and the N-type emitter region 9 are exposed, and aluminum wirings 12a and 12b connected to the respective surfaces are formed. The aluminum wiring 12a is connected to the power supply voltage potential (Vcc), and the aluminum wiring 12b is connected to the ground potential, thereby completing the electrostatic breakdown protection element.

以上のような静電破壊保護素子を備えた半導体装置は、アルミニウム配線12aに過剰な負電圧が印加した場合、N型エピタキシャル層4と高濃度不純物層14とのPN接合の順方向特性により、電荷を接地に排出する。   The semiconductor device including the electrostatic breakdown protection element as described above has a forward characteristic of the PN junction between the N-type epitaxial layer 4 and the high-concentration impurity layer 14 when an excessive negative voltage is applied to the aluminum wiring 12a. Discharge charge to ground.

またアルミニウム配線12aに過剰な正電圧が印加した場合には、図1(b)に示す電気的特性を示すことになる。すなわち、N型エピタキシャル層4と高濃度不純物層14とのPN接合は逆方向であるため空乏層が広がり、電流は流れない。しかし、アバランシェ・ブレイクダウン現象によって電圧V1に達すると、PN接合を逆方向電流が流れる。流れる電流が徐々に増加すると、N型埋込層2に逆方向電流が流れ込み、電圧降下によってP型ベース領域8の電位が上昇する。この電位の上昇により、NPNトランジスタがオンし、N型エピタキシャル層4、高濃度不純物層14、P型ベース領域8、N型エミッタ領域9からなるNPN接合に逆方向電流が流れ、アルミニウム配線12aからアルミニウム配線12bへ大電流を流すことができ、電荷を接地に排出する。   Further, when an excessive positive voltage is applied to the aluminum wiring 12a, the electrical characteristics shown in FIG. That is, since the PN junction between the N-type epitaxial layer 4 and the high-concentration impurity layer 14 is in the opposite direction, the depletion layer spreads and no current flows. However, when the voltage V1 is reached due to the avalanche breakdown phenomenon, a reverse current flows through the PN junction. When the flowing current gradually increases, a reverse current flows into the N-type buried layer 2 and the potential of the P-type base region 8 rises due to a voltage drop. With this potential increase, the NPN transistor is turned on, and a reverse current flows through the NPN junction composed of the N-type epitaxial layer 4, the high-concentration impurity layer 14, the P-type base region 8, and the N-type emitter region 9, and the aluminum wiring 12a A large current can flow through the aluminum wiring 12b, and the charge is discharged to the ground.

特に本発明では、高濃度不純物層14によって、N型エミッタ領域9の周囲の抵抗を低くすることができるため、P型ベース領域8周辺に高抵抗の部分が発生することがないので、N型エミッタ領域9周辺のP型ベース領域8が高温とならない。しかも、N型エミッタ領域9を取り囲むように高濃度不純物層14を配置しているため、電流が集中することがない。その結果、熱起因による素子破壊を防止することができる。   In particular, according to the present invention, since the high-concentration impurity layer 14 can reduce the resistance around the N-type emitter region 9, a high-resistance portion is not generated around the P-type base region 8. The P-type base region 8 around the emitter region 9 does not reach a high temperature. In addition, since the high-concentration impurity layer 14 is disposed so as to surround the N-type emitter region 9, current does not concentrate. As a result, element destruction due to heat can be prevented.

なお本実施例中ではN型エミッタ領域9と高濃度不純物層14との間の寸法を1μmとしたが、N型エミッタ領域9と高濃度不純物層14が接触せず、抵抗が高くならない範囲で適宜設定可能である。また、静電破壊保護素子の電圧V1、N型エピタキシャル層4と高濃度不純物層14とのPN接合、P型ベース領域8とN型エミッタ領域9とのPN接合に流れる電流値は、それぞれの半導体領域の不純物濃度、寸法等を適宜設定することで、所望の値に設定することができる。   In this embodiment, the dimension between the N-type emitter region 9 and the high-concentration impurity layer 14 is 1 μm, but the N-type emitter region 9 and the high-concentration impurity layer 14 are not in contact with each other and the resistance does not increase. It can be set as appropriate. Further, the voltage V1 of the electrostatic breakdown protection element, the current value flowing through the PN junction between the N-type epitaxial layer 4 and the high-concentration impurity layer 14, and the PN junction between the P-type base region 8 and the N-type emitter region 9 are A desired value can be set by appropriately setting the impurity concentration, size, and the like of the semiconductor region.

たとえば、図1(b)に示す特性を示す静電破壊保護素子は、N型エピタキシャル層4の比抵抗が5Ω・cm、厚さが5μm、エミッタサイズが6μm×50μm、高濃度不純物層14の幅が4μmの場合を示しているが、エミッタ幅のみを広くすることで、静電破壊保護素子に流すことができる電流値を大きくすることができる。   For example, in the electrostatic breakdown protection element having the characteristics shown in FIG. 1B, the N-type epitaxial layer 4 has a specific resistance of 5 Ω · cm, a thickness of 5 μm, an emitter size of 6 μm × 50 μm, and a high-concentration impurity layer 14. Although the case where the width is 4 μm is shown, the current value that can be passed through the electrostatic breakdown protection element can be increased by increasing only the emitter width.

また、高濃度不純物層14幅を2μmとした場合、4μmの場合と比較して静電破壊保護素子の破壊電流(破壊に至る電流値)が減少し、ばらつくことが確認された。具体的には、高濃度不純物層14幅が4μmの場合、平均破壊電流2.5A、バラツキ1.12%であったものが、幅2μmの場合は、平均破壊電流1.98A、バラツキ9.62%となることを確認している。従って、上記電圧V1が大きい場合、高濃度不純物層14幅をひろげ、バラツキ等が小さくなる幅に設定する必要がある。   In addition, it was confirmed that when the width of the high concentration impurity layer 14 is 2 μm, the breakdown current (current value leading to breakdown) of the electrostatic breakdown protection element decreases and varies as compared with the case of 4 μm. Specifically, when the width of the high-concentration impurity layer 14 is 4 μm, the average breakdown current is 2.5 A and the variation is 1.12%. When the width is 2 μm, the average breakdown current is 1.98 A and the variation is 9.2. Confirmed to be 62%. Therefore, when the voltage V1 is large, the width of the high-concentration impurity layer 14 needs to be widened and set to a width where variations and the like are small.

なお本発明では、電流をより分散して流すことができるように、N型エミッタ領域9の周囲全部を取り囲むように高濃度不純物層14を配置する必要がある。それは、エミッタサイズ、高濃度不純物層の幅等の形成条件は同一で、高濃度不純物層をエミッタ領域の周辺を取り囲むように配置した場合と、コレクタ領域側のみに配置した場合とを比較したとき、前者の平均破壊電流が2.5A、バラツキが1.12%であったものが、後者の平均破壊電流は1.68Aに低下し、バラツキは12.5%に増大することを確認しているからである。   In the present invention, the high-concentration impurity layer 14 needs to be disposed so as to surround the entire periphery of the N-type emitter region 9 so that the current can be more dispersed. That is, when the formation conditions such as the emitter size and the width of the high-concentration impurity layer are the same, and the case where the high-concentration impurity layer is disposed so as to surround the periphery of the emitter region is compared with the case where it is disposed only on the collector region side. It was confirmed that the former average breakdown current was 2.5 A and the variation was 1.12%, but the latter average breakdown current was decreased to 1.68 A and the variation was increased to 12.5%. Because.

本願発明の半導体装置の一実施例を説明する図である。It is a figure explaining one Example of the semiconductor device of this invention. 従来のこの種の半導体装置を説明する図である。It is a figure explaining this kind of conventional semiconductor device.

符号の説明Explanation of symbols

1:P型半導体基板、2:N+型埋込層、3:P+型埋込層、4:N型エピタキシャル層、5:LOCOS層、6:P型拡散層、7:N型コレクタ領域、8:P型ベース領域、9:N型エミッタ領域、10:酸化膜、11:絶縁酸化膜、12a、12b:アルミニウム配線、13:P+型拡散層、14:高濃度不純物層 1: P type semiconductor substrate, 2: N + type buried layer, 3: P + type buried layer, 4: N type epitaxial layer, 5: LOCOS layer, 6: P type diffusion layer, 7: N type collector region 8: P-type base region, 9: N-type emitter region, 10: oxide film, 11: insulating oxide film, 12a, 12b: aluminum wiring, 13: P + type diffusion layer, 14: high-concentration impurity layer

Claims (1)

一導電型のエピタキシャル層が形成された半導体基板上に、該半導体基板と前記エピタキシャル層との間の一導電型の埋込層と前記エピタキシャル層表面から前記埋込層に達する一導電型の拡散層で構成されるコレクタ領域と、前記エピタキシャル層表面に形成された逆導電型の拡散領域からなるベース領域と、該ベース領域表面に形成された一導電型の拡散領域からなるエミッタ領域と、該エミッタ領域と前記ベース領域とを接続する第1の電極と、前記コレクタ領域に接続する第2の電極とからなる静電破壊保護素子を備え、内部回路を静電破壊から保護する半導体装置において、
前記ベース領域に接し、前記エミッタ領域を取り囲むように配置した、前記ベース領域より不純物濃度が高く、一部が前記エピタキシャル層と接した、一導電型の高濃度領域を備え、
前記第1の電極及び前記第2の電極間の印加電圧が上昇したとき、前記静電破壊保護素子の前記高濃度領域と前記エピタキシャル層とで構成するPN接合に電流を流し、
前記第1の電極及び前記第2の電極間の印加電位がさらに上昇し、前記ベース領域に印加する電位が上昇したとき、前記静電破壊保護素子の前記エミッタ領域と前記ベース領域とで構成するPN接合に電流を流すことを特徴とする半導体装置。
One conductivity type buried layer between the semiconductor substrate and the epitaxial layer, and one conductivity type diffusion reaching the buried layer from the surface of the epitaxial layer on the semiconductor substrate on which the one conductivity type epitaxial layer is formed A collector region composed of layers, a base region composed of a reverse conductivity type diffusion region formed on the surface of the epitaxial layer, an emitter region composed of a one conductivity type diffusion region formed on the surface of the base region, and In a semiconductor device that includes an electrostatic breakdown protection element including a first electrode that connects an emitter region and the base region and a second electrode that is connected to the collector region, and protects an internal circuit from electrostatic breakdown.
The base region in contact and arranged to surround said emitter region, said base region impurity concentration rather higher than, part is in contact with the epitaxial layer comprises a heavily doped region of the one conductivity type,
When an applied voltage between the first electrode and the second electrode rises, a current is passed through a PN junction constituted by the high concentration region of the electrostatic breakdown protection element and the epitaxial layer,
When the potential applied between the first electrode and the second electrode is further increased and the potential applied to the base region is increased, the emitter region and the base region of the electrostatic breakdown protection element are configured. A semiconductor device characterized by passing a current through a PN junction.
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