JP2020123606A - Semiconductor device - Google Patents

Abstract

To achieve a miniaturization, the reduction in a loss, and a wide band.SOLUTION: In an MMIC 1, a first wiring layer 11 has a first electrode part 11a and a wiring part 11b, a second wiring layer 12 has a second electrode part 12a and land parts 12b and 12b, and 12c and 12c, which are electrically independent, and a third wiring layer 13 includes a third electrode part 13a, and a pad part 13b continued to the third electrode part 13a. A first MIM capacitor 101 is formed by the second electrode part 12a, the first electrode part 11a, an insulator layer 21, A second MIM capacitor 102 which is overlapped with the first MIM capacitor 101 is formed by the second electrode part 12a, the third electrode part 13a, and the insulator layer 22, and the first MIM capacitor 101 and the second MIM capacitor 102 are formed in a trapezoidal shape in a plan view. The third electrode part 13a has first vias 131 and 131 connected to the first electrode part 11a in a lower bottom part 13v.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device.

In an IC that operates at high speed, the wavelength of a signal propagating in the circuit may be approximately the same as the size of one side of a capacitor provided in the IC. In this case, a resonance phenomenon may occur at the signal wavelength corresponding to one side of the capacitor, and the circuit operation may become unstable. In the semiconductor device described in Patent Document 1, in a MIM (Metal-Insulator-Metal) capacitor, opposing sides have a shape having no parallel portion, so that the resonance frequency is continuously changed and the specific frequency is changed. It suppresses the occurrence of resonance phenomenon.

JP, 2004-172245, A

Here, in a monolithic microwave integrated circuit (MMIC) that employs a WLCSP (Wafer level Chip Size Package), which is a package format suitable for miniaturization, the width of the pad that is continuous with the electrode portion that constitutes the MIM capacitor. Is as large as about 100 μm, while the width of the wiring continuous to the electrode portion is as small as about 10 μm. In this way, when a pad and a wiring whose widths are significantly different from each other (that is, impedances are significantly different) are connected to each other, signal reflection occurs due to the difference in width, and also with the configuration of Patent Document 1 described above, The circuit operation may become unstable. For example, the above-mentioned signal reflection is reduced by forming the electrode portion of the MIM capacitor in a tapered shape and gradually reducing its width from the side continuous with the pad toward the side continuous with the wiring. be able to. However, in the configuration in which the electrode portion of the MIM capacitor is formed in a tapered shape, the facing area is reduced and the capacitance value of the MIM capacitor is reduced as compared with the case where the electrode portion of the MIM capacitor is rectangular. As a result, the loss and the band are deteriorated.

Therefore, an object of one embodiment of the present invention is to provide an MMIC that realizes downsizing, low loss, and wide bandwidth.

A semiconductor device according to an aspect of the present invention is a semiconductor device including a first wiring layer, a second wiring layer, and a third wiring layer in order from a substrate side, and the first wiring layer includes a first electrode portion. The second wiring layer has a second electrode portion and a land portion which are electrically independent from each other, the second electrode portion is continuous with the wiring structure of the semiconductor device, and the third wiring layer is The third electrode portion and a pad portion continuous with the third electrode portion are provided, and the second electrode portion and the first electrode portion, and the first interlayer film interposed between the second wiring layer and the first wiring layer make A first MIM capacitor is formed, and a second MIM capacitor that overlaps the first MIM capacitor is formed by the second electrode portion and the third electrode portion and the second interlayer film interposed between the second wiring layer and the third wiring layer. The capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion in plan view, and the third electrode portion has the first electrode on the lower bottom portion. A first via connected to the section.

A semiconductor device according to another aspect of the present invention is a semiconductor device including a first wiring layer, a second wiring layer, and a third wiring layer in this order from the substrate side, wherein the first wiring layer is the first electrode portion. And a wiring portion independent of the first electrode portion and continuous with the wiring structure of the semiconductor device, the second wiring layer has a second electrode portion and a land portion electrically independent of each other, and a third wiring layer Has a third electrode portion and a pad portion continuous with the third electrode portion, and is formed by the second electrode portion and the first electrode portion, and the first wiring layer and the first interlayer film interposed between the first wiring layers. A first MIM capacitor is formed, and a second MIM capacitor that overlaps the first MIM capacitor is formed by the second electrode portion and the third electrode portion, and the second interlayer film interposed between the second wiring layer and the third wiring layer, When viewed in a plan view, the first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side being the lower bottom portion and the side on the wiring structure side being the upper bottom portion, and the third electrode portion is It has a first via connected to one electrode portion.

Based on the above, it is possible to provide an MMIC that realizes downsizing, low loss, and wide bandwidth.

It is a figure which shows the MMIC which concerns on 1 aspect of this invention, (a) is a top view, (b) is sectional drawing along the bb line of (a), (c) is cc of (a). Sectional drawing which followed the line, (d) is sectional drawing which followed the dd line of (a). It is a figure which shows typically the electrode structure of each wiring layer in MMIC shown in FIG. It is a figure which shows the MMIC which concerns on a comparative example typically, (a) is a top view, (b) is sectional drawing which followed the bb line|wire of (a). It is a figure explaining the subject of MMIC which concerns on a comparative example, (a) is a figure explaining the reduction of a facing area, (b) is a figure explaining an edge functioning as an open stub. 6 is a graph showing the band improvement and loss improvement effects of the MMIC according to an aspect of the present invention. It is a figure which shows the MMIC which concerns on the modification of this invention, (a) is a top view, (b) is sectional drawing which followed the bb line of (a), (c) is cc of (a). Sectional drawing which followed the line, (d) is sectional drawing which followed the dd line of (a).

A specific example of a monolithic microwave integrated circuit (MMIC) according to an embodiment of the present invention will be described below with reference to the drawings. In the description, the same elements or elements having the same function will be denoted by the same reference symbols, without redundant description. The present invention is not limited to the following examples, but is shown by the scope of the claims, and is intended to include the equivalents of the scope of the claims and all modifications within the scope.

1A and 1B are views showing an MMIC 1 (semiconductor device) according to the present embodiment, where (a) is a plan view, (b) is a sectional view taken along line bb of (a), and (c) is ( (a) is a sectional view taken along the line cc, and (d) is a sectional view taken along the line dd of (a). The MMIC 1 is a type of microwave integrated circuit, and is an integrated circuit in which a microwave circuit (functions such as a microwave band mixer, amplification, and switching) is formed on a single semiconductor substrate by a microfabrication technique. The MMIC 1 is formed by a WLCSP (Wafer level Chip Size Package) which is a package format suitable for downsizing, for example. The WLCSP is a package format in which terminals are formed and wiring is performed before cutting a wafer on which semiconductor elements are formed.

The MMIC 1 shown in FIGS. 1A to 1D includes a first wiring layer 11, an insulator layer 21 (first interlayer film, see FIG. 1C), and a second wiring layer 11 in order from the substrate (not shown) side. The wiring layer 12, the insulator layer 22 (second interlayer film, see FIG. 1C), and the third wiring layer 13 are laminated (three-layer structure). When the substrate is an insulating substrate, the first wiring layer 11 may be formed directly on the substrate.

The first wiring layer 11 is, for example, a metal layer made of gold and having a thickness of 1 μm. The second wiring layer 12 is, for example, a metal layer made of gold and having a thickness of 1 μm. The third wiring layer 13 is, for example, a metal layer made of gold and having a thickness of 1 μm. A well-known vapor deposition method and a lift-off method thereafter, or a method such as an ion milling method after forming a gold layer by a sputtering method can be used for forming each wiring layer. As the insulating layers 21 and 22, for example, polyimide or the like can be used. Each of the insulator layers 21 and 22 is formed to have a thickness larger than that of the metal layer, for example, 2 μm. A method such as a plasma CVD method or a spin coating method can be used to form the insulator layers 21 and 22.

FIG. 2 is a diagram schematically showing an electrode structure of each wiring layer in the MMIC 1 shown in FIG. In FIG. 2, the structure related to the first wiring layer 11 is shown by a chain double-dashed line, the structure related to the second wiring layer 12 is shown by a broken line, and the structure related to the third wiring layer 13 is shown by a solid line. As shown in FIG. 2, the third wiring layer 13 has a third electrode portion 13a and a pad portion 13b continuous with the third electrode portion 13a. The pad portion 13b has a substantially rectangular shape in a plan view, and the length in the width direction (direction intersecting the direction in which the pad portion 13b and the third electrode portion 13a are continuous) is, for example, about 100 μm to 200 μm. Solder balls 13x are provided on the pad portion 13b, and the solder ball 13x connects the pad portion 13b to an external configuration (printed wiring board or the like). The third electrode portion 13a is continuous with the pad portion 13b and is a trapezoidal electrode portion in plan view. More specifically, in plan view, the third electrode portion 13a is formed in a trapezoidal shape in which a side continuous with the pad portion 13b is a lower bottom portion 13v and a side separated from the pad portion 13b is an upper bottom portion 13w. The lower bottom portion 13v is longer than the upper bottom portion 13w. As a result, the third electrode portion 13a is formed in a tapered shape from the lower bottom portion 13v toward the upper bottom portion 13w when seen in a plan view.

The first wiring layer 11 has a first electrode portion 11a and a wiring portion 11b. The first electrode portion 11a is an electrode portion formed in a trapezoidal shape in plan view, and has the same shape as the third electrode portion 13a of the third wiring layer 13 in plan view, and the third electrode portion 13a and the formation area are Most of them overlap. That is, in plan view, the first electrode portion 11a is formed in a trapezoidal shape in which the side on the pad portion 13b side is the lower bottom portion 11v and the side away from the pad portion 13b is the upper bottom portion 11w. Then, in the first electrode portion 11a, the lower bottom portion 11v is longer than the upper bottom portion 11w, and is formed in a taper shape from the lower bottom portion 11v toward the upper bottom portion 11w in plan view. The wiring portion 11b is provided independently (separated) from the first electrode portion 11a, and is continuous with the wiring structure (for example, 50Ω wiring structure) in the MMIC 1. The length of the wiring portion 11b in the width direction (direction intersecting with the longitudinal direction of the wiring portion 11b) is about the same as the wiring structure, and is about 10 μm, for example.

The second wiring layer 12 has a second electrode portion 12a and a plurality of lands 12b, 12b, 12c, 12c. The plurality of lands 12b, 12b, 12c, 12c are provided independently of each other, and are also provided independently of the second electrode portion 12a. The lands 12b, 12b (first lands) are provided at both ends in the width direction on the lower bottom part 11v side of the third electrode part 13a in plan view. The lands 12c, 12c (second lands) are provided at both ends in the width direction on the upper bottom 11w side of the third electrode 13a when viewed in a plan view. The second electrode portion 12a is a first portion 12d formed in a substantially trapezoidal shape in plan view, and a second portion that is continuous with the first portion 12d and is electrically connected to the wiring portion 11b of the first wiring layer 11. 12f and. The first portion 12d is formed in a substantially trapezoidal shape so that the formation region substantially overlaps with the third electrode portion 13a in plan view, but the plurality of land portions 12b, 12b, 12c, 12c described above are formed. Area is not formed. That is, the first portion 12d is not formed on both widthwise end portions on the lower bottom side where the land portions 12b and 12b are formed and on both widthwise end portions on the upper bottom portion where the land portions 12c and 12c are formed. .. More specifically, the first portion 12d is formed slightly inside the third electrode portion 13a and the first electrode portion 11a in plan view. The second portion 12f is continuously provided on the upper bottom side of the first portion 12d. The second portion 12f is provided so as to overlap the wiring portion 11b of the first wiring layer 11 in the stacking direction. The second portion 12f is connected to the wiring portion 11b of the first wiring layer 11 via the via 12x (see FIG. 1C).

As shown in FIGS. 1B and 1C, the third electrode portion 13a of the third wiring layer 13 is further connected to the first electrode portion 11a of the first wiring layer 11 at the lower bottom portion 13v. First vias 131, 131 and second vias 132, 132 connected to the first electrode portion 11a of the first wiring layer 11 in the upper bottom portion 13w. The first vias 131, 131 and the second vias 132, 132 are holes (via holes) intended for conduction between the third electrode portion 13a and the first electrode portion 11a, and penetrate the insulating layers 21, 22. Is formed in. The first vias 131, 131 extend in the first electrode portion 11a direction from both ends in the width direction of the lower bottom portion 13v, and are connected to the lower bottom portion 11v of the first electrode portion 11a via the land portions 12b, 12b, respectively. ing. The second vias 132, 132 extend from both ends in the width direction of the upper bottom portion 13w in the direction of the first electrode portion 11a, and are connected to the upper bottom portion 11w of the first electrode portion 11a via the land portions 12c, 12c, respectively. ing.

In the MMIC 1 having such a configuration, as shown in FIG. 1C, an insulator interposed between the second electrode portion 12a and the first electrode portion 11a and the second wiring layer 12 and the first wiring layer 11. A first MIM capacitor 101 is formed by the layer 21, and the first MIM capacitor 101 is formed by the second electrode portion 12a and the third electrode portion 13a and the insulator layer 22 interposed between the second wiring layer 12 and the third wiring layer 13. A second MIM capacitor 102 that overlaps the capacitor 101 in the stacking direction is formed. Since the first electrode portion 11a, the second electrode portion 12a, and the third electrode portion 13a are all trapezoidal in plan view (or substantially trapezoidal), the first MIM capacitor 101 and the second MIM capacitor 102 are seen in plan view. All of them are formed in a trapezoidal shape with the side on the pad portion 13b side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion.

Next, the function and effect of the MMIC 1 according to this embodiment will be described in comparison with a comparative example.

3A and 3B are diagrams schematically showing an MMIC 501 according to a comparative example, FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along line bb of FIG. As shown in FIG. 3B, the MMIC 501 has a structure (two-layer structure) in which a first wiring layer 511, an insulator layer 521, and a second wiring layer 513 are stacked in order from the substrate (not shown) side. have. The second wiring layer 513 has an electrode portion 513a that is trapezoidal in plan view and a pad portion 513b that is continuous with the electrode portion 513a. The first wiring layer 511 has an electrode portion 511a having a trapezoidal shape in plan view, and a wiring portion 511b continuous with the wiring structure. Then, in the MMIC 501, as shown in FIG. 3B, the electrode section 511a and the electrode section 513a and the insulator layer 521 form a trapezoidal MIM capacitor 601 in plan view.

The MMIC 501 is formed of, for example, WLCSP. In the MMIC 501 formed by WLCSP, the width of the pad portion 513b is as large as about 100 μm, while the width of the wiring portion 511b and the wiring structure is as small as about 10 μm. When the pad portion 513b and the wiring structure whose widths are significantly different from each other (that is, impedances are significantly different) are connected to each other in this way, signal reflection occurs due to the difference in width and the circuit operation becomes unstable. There is a risk. In the MMIC 501, the electrode portions 511a and 513a of the MIM capacitor 601 are formed in a tapered shape from the lower bottom portion to the upper bottom portion, and the width thereof gradually increases from the side continuous with the pad portion 513b to the continuous side with the wiring portion 511b. Is formed so as to reduce the reflection of the signal described above. However, in such a configuration in which the electrode portion of the MIM capacitor is formed in a tapered shape, the facing area is reduced as compared with the case where the electrode portion of the MIM capacitor is rectangular. That is, as shown in FIG. 4A, the MIM capacitor 601 having a trapezoidal shape in plan view has a facing area which is smaller than that of the MIM capacitor having a rectangular shape in plan view only in a region RE (a region partitioned by a dashed line). Will decrease. As a result, the capacitance value of the MIM capacitor 601 is reduced, and as a result, the loss and the band are deteriorated.

On the other hand, the MMIC 1 according to the present embodiment is a semiconductor device including the first wiring layer 11, the second wiring layer 12, and the third wiring layer 13 in this order from the substrate side, and the first wiring layer 11 includes The second wiring layer 12 includes a first electrode portion 11a and a wiring portion 11b independent of the first electrode portion 11a and continuous in a wiring structure. The second wiring layer 12 is electrically independent of each other. The third wiring layer 13 has a third electrode portion 13a and a pad portion 13b continuous with the third electrode portion 13a, and has a second electrode portion 12a and a first electrode portion 11a. , The second wiring layer 12 and the insulating layer 21 interposed between the first wiring layer 11 form the first MIM capacitor 101, the second electrode portion 12a and the third electrode portion 13a, the second wiring layer 12 and A second MIM capacitor 102 that overlaps the first MIM capacitor 101 is formed by the insulator layer 22 that is interposed between the third wiring layers 13, and the first MIM capacitor 101 and the second MIM capacitor 102 are located on the pad portion 13b side when seen in a plan view. The third electrode portion 13a is formed in a trapezoidal shape with the side being the lower bottom portion and the wiring structure side being the upper bottom portion, and the third electrode portion 13a has first vias 131, 131 connected to the first electrode portion 11a at the lower bottom portion 13v. Have.

In the MMIC 501 according to the comparative example, the wiring layer has a two-layer structure, whereas in the MMIC 1 according to the present embodiment, the wiring layer has a three-layer structure, and the first electrode portion 11a of the first wiring layer 11 is included. And the second MIM capacitor 101 is formed including the second electrode portion 12a of the second wiring layer 12, and the first MIM capacitor 101 is formed including the third electrode portion 13a of the third wiring layer 13 and the second electrode portion 12a of the second wiring layer 12. The 2MIM capacitor 102 is formed, and the third electrode portion 13a and the first electrode portion 11a are connected by the first vias 131, 131 on the lower bottom portions 13v, 11v side. Since the wiring layer has a three-layer structure and two MIM capacitors are formed, the capacitance value can be increased as compared with the MMIC 501 having one MIM capacitor. That is, in the MMIC 1 that employs the WLCSP, which is a package format suitable for downsizing, the MIM capacitors (the first MIM capacitor 101 and the second MIM capacitor 101) are provided in order to reduce signal reflection due to the difference in width between the pad portion 13b and the wiring structure. Even in the configuration in which 102) is formed in a tapered shape (trapezoidal shape in plan view), the capacitance value can be secured by forming two MIM capacitors. By guaranteeing the capacity value, it is possible to suppress loss in the MMIC 1 and deterioration of the band. As described above, according to the configuration of the present embodiment, it is possible to provide the MMIC 1 that realizes downsizing, low loss, and wide band.

Further, in the MMIC 1 according to the present embodiment, the third electrode portion 13a has second vias 132, 132 connected to the first electrode portion 11a at the upper bottom portion 13w. In the configuration in which the first vias 131, 131 are formed on the lower bottom portions 13v, 11v sides, if no vias are formed on the upper bottom portions 13w, 11w sides, the end portions on the upper bottom portions 13w, 11w side are open stubs. This will function as 300 (see FIG. 4B), and the effective facing area of the MIM capacitor will be reduced. In this regard, since the third electrode portion 13a and the first electrode portion 11a are connected by the second vias 132, 132 on the upper bottom portions 13w, 11w side, the end portions on the upper bottom portions 13w, 11w side function as open stubs. It is possible to suppress the effective reduction of the facing area in the MIM capacitors (the first MIM capacitor 101 and the second MIM capacitor 102).

The effect obtained by suppressing the decrease in the facing area and ensuring the capacitance value will be described with reference to FIG. FIG. 5 is a graph showing the band improvement and loss improvement effects of MMIC1. In FIG. 5, the horizontal axis represents the band (GHz) and the vertical axis represents the S parameter (dB). Further, in FIG. 5, the graph indicated by the solid line is the graph of the MMIC 501 (MMIC having the two-layer structure) according to the comparative example, and the graph indicated by the broken line is the graph of the MMIC having the three-layer structure and without the second vias 132, 132. The graph indicated by the alternate long and short dash line is a graph of the MMIC 1 (three-layer structure and with the second vias 132, 132) according to this embodiment. As shown in FIG. 5, the MMIC having the three-layer structure is improved in band particularly in the low frequency band as compared with the MMIC having the two-layer structure. Further, when comparing the MMICs having the three-layer structure, the MMICs having the second vias 132 and 132 have the band improvement particularly in the high frequency band because the ends do not become the open stubs.

Further, in the MMIC 1 according to the present embodiment, the second wiring layer 12 has the land portions 12b and 12b and the land portions 12c and 12c that are electrically independent from each other as the land portion, and the first vias 131 and 131 are the land portions. The second vias 132, 132 are connected to the first electrode portion 11a via the portions 12b, 12b, and are connected to the first electrode portion 11a via the land portions 12c, 12c. The first vias 131, 131 and the second vias 132, 132 are connected to the first electrode portion 11a via the land portions 12b, 12b, 12c, 12c, whereby the first vias 131, 131 and the second vias are connected. The 132 and 132 can be provided more reliably.

Further, in the MMIC 1 according to this embodiment, the pad portion 13b has the solder ball 13x. As a result, the external configuration such as a printed circuit board and the MMIC 1 can be properly connected.

Although the MMIC according to the present embodiment has been described above, the present invention is not limited to these, and various modifications can be applied. It should be considered that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the present invention is shown not by the above meaning but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope. For example, in the MMIC 1 described above, the wiring portion of the first wiring layer 11 is described as being continuous with the wiring structure, that is, the wiring structure is drawn from the first wiring layer 11, but the present invention is not limited to this, and FIG. The wiring structure may be drawn from the second wiring layer 212 like the MMIC 201 shown in FIGS.

6A and 6B are views showing an MMIC 201 according to a modified example of the present invention, in which FIG. 6A is a plan view, FIG. 6B is a sectional view taken along line bb of FIG. 6A, and FIG. Is a cross-sectional view taken along the line cc of FIG. 6A, and FIG. 7D is a cross-sectional view taken along the line dd of FIG. The MMIC 201 includes a first wiring layer 211, an insulating layer 221 (first interlayer film, see FIG. 6C), a second wiring layer 212, and an insulating layer 222 (second interlayer) in order from the substrate (not shown) side. The film has a structure (three-layer structure) in which a third wiring layer 213 is stacked (see FIG. 6C). The third wiring layer 213 has a third electrode portion 213a that is trapezoidal in plan view, and a pad portion 213b that is continuous with the third electrode portion 213a. The first wiring layer 211 has a first electrode portion 211a that is trapezoidal in plan view. The second wiring layer 212 has a second electrode portion 212a and lands 212b, 212b, 212c, 212c that are electrically independent of each other. The land portions 212b and 212b (first land portions) are provided at both ends in the width direction on the lower bottom side when viewed in a plan view. The land portions 212c and 212c (second land portions) are provided at both end portions in the width direction on the upper bottom portion 11w side when seen in a plan view. The second electrode portion 212a is continuous with the wiring structure and is formed in a substantially trapezoidal shape in a plan view. However, the second electrode portion 212a is not formed in the region where the plurality of lands 212b, 212b, 212c, 212c described above are formed.

As shown in FIGS. 6B and 6C, the third electrode portion 213a of the third wiring layer 213 is further connected to the first electrode portion 211a of the first wiring layer 211 at the lower bottom portion. It has first vias 231 and 231 and second vias 232 and 232 connected to the first electrode portion 211a of the first wiring layer 211 at the upper bottom portion. The first vias 231 and 231 and the second vias 232 and 232 are holes (via holes) for the purpose of electrical connection between the third electrode portion 213a and the first electrode portion 211a, and penetrate the insulating layers 221 and 222. Is formed in. The first vias 231 and 231 extend in the first electrode portion 211a direction from both widthwise ends of the lower bottom portion, and are connected to the lower bottom portion of the first electrode portion 211a via the land portions 212b and 212b, respectively. .. The second vias 232 and 232 extend in the first electrode portion 211a direction from both ends in the width direction of the upper bottom portion, and are connected to the upper bottom portion of the first electrode portion 211a via the land portions 212c and 212c, respectively. ..

In the MMIC 201 having such a configuration, as shown in FIG. 6D, an insulator interposed between the second electrode portion 212a and the first electrode portion 211a and the second wiring layer 212 and the first wiring layer 211. A first MIM capacitor 251 is formed by the layer 221, and the first MIM capacitor 251 is formed by the second electrode portion 212a and the third electrode portion 213a and the insulating layer 222 interposed between the second wiring layer 212 and the third wiring layer 213. A second MIM capacitor 252 that overlaps the capacitor 251 in the stacking direction is formed. Since the first electrode portion 211a, the second electrode portion 212a, and the third electrode portion 213a are all trapezoidal (or substantially trapezoidal) in plan view, the first MIM capacitor 251 and the second MIM capacitor 252 are planarly viewed. All of them are formed in a trapezoidal shape with the side on the pad portion 213b side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion.

1, 201... MMIC (semiconductor device), 11, 211... First wiring layer, 11a, 211a... First electrode portion, 11b... Wiring portion, 12,212... Second wiring layer, 12a, 212a... Second electrode portion , 12b, 212b... Land portion (first land portion), 12c, 212c... Land portion (second land portion), 13, 213... Third wiring layer, 13a, 213a... Third electrode portion, 13b, 213b... Pad Part, 13x... Solder balls, 21,221... Insulator layer (first interlayer film), 22, 222... Insulator layer (second interlayer film) 101,251... First MIM capacitor, 102,252... Second MIM capacitor , 131, 231... First via, 132, 232... Second via.

Claims (5)

A semiconductor device comprising a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side,
The first wiring layer has a first electrode portion,
The second wiring layer has a second electrode portion and a land portion that are electrically independent of each other, and the second electrode portion is continuous with the wiring structure of the semiconductor device,
The third wiring layer has a third electrode portion and a pad portion continuous with the third electrode portion,
A first MIM capacitor is formed by the second electrode portion and the first electrode portion, and the first interlayer film interposed between the second wiring layer and the first wiring layer,
A second MIM capacitor overlapping the first MIM capacitor is formed by the second electrode part and the third electrode part, and the second interlayer film interposed between the second wiring layer and the third wiring layer,
The first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with a side on the pad portion side being a lower bottom portion and a side on the wiring structure side being an upper bottom portion in plan view,
The said 3rd electrode part is a semiconductor device which has a 1st via|veer connected to the said 1st electrode part in the said lower bottom part. A semiconductor device comprising a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side,
The first wiring layer has a first electrode portion and a wiring portion independent of the first electrode portion and continuous with the wiring structure of the semiconductor device,
The second wiring layer has a second electrode portion and a land portion that are electrically independent of each other,
The third wiring layer has a third electrode portion and a pad portion continuous with the third electrode portion,
A first MIM capacitor is formed by the second electrode portion and the first electrode portion, and the first interlayer film interposed between the second wiring layer and the first wiring layer,
A second MIM capacitor overlapping the first MIM capacitor is formed by the second electrode part and the third electrode part, and the second interlayer film interposed between the second wiring layer and the third wiring layer,
The first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with a side on the pad portion side being a lower bottom portion and a side on the wiring structure side being an upper bottom portion in plan view,
The said 3rd electrode part is a semiconductor device which has a 1st via|veer connected to the said 1st electrode part in the said lower bottom part. The semiconductor device according to claim 1 or 2, wherein the third electrode portion has a second via connected to the first electrode portion at the upper bottom portion. The second wiring layer has, as the land portion, a first land portion and a second land portion electrically independent from each other,
The first via is connected to the first electrode portion via the first land portion, and the second via is connected to the first electrode portion via the second land portion. The semiconductor device described. The semiconductor device according to claim 1, wherein the pad portion has a solder ball.