JP4280141B2 - Multilayer printed wiring board - Google Patents

Description

  The present invention relates to a multilayer printed wiring board having a capacitor in an inner layer, and more particularly to a multilayer printed wiring board in which a capacitor (function) is built using an inner layer material of a substrate.

  Until now, in order to reduce the noise generated between the power supply layer and the ground layer (grounding layer) in the printed wiring board, a method of mounting a capacitor on the surface of the printed wiring board has been used.

  In some cases, the capacitor is placed so that it is directly connected to the electronic device by surface wiring, and in other cases, the capacitor is placed close to the selected electronic device, and the power and ground layers are connected by through holes. It is well known that the noise component described above is attenuated by connection.

  However, on the other hand, it is well known that inductance is generated due to wiring connecting a capacitor and an electronic device, a through hole connecting a capacitor, a power supply layer, and a ground layer, and the effect of noise suppression is reduced.

  Further, since the capacitor has not only a capacitive property but also a dielectric property, the capacitor itself tends to affect the signal reliability of the electronic device.

  Furthermore, since electronic devices are a major factor in generating noise in a printed wiring board, not only are electronic devices properly arranged on the printed wiring board, but they are also operating at different speeds and frequencies. Corresponding to the characteristics of the electronic device, the capacitor needs to have a function of suppressing noise in both high-speed and low-speed operations.

  In order to solve these problems, printed wiring board design and electronic device arrangement methods have been studied. However, mounting a capacitor on the surface of the printed wiring board as described above is important for signal reliability. Not only did it have an undesirable effect, but it also complicates the printed wiring board and increases manufacturing costs.

  In view of this, a method has been proposed for solving the above-mentioned problems by incorporating a capacitor laminate having a capacitance component in which the electrodes formed on the front and back sides of the dielectric are respectively provided on the multilayer printed wiring board as a power supply layer and a ground layer. (For example, refer to Patent Document 1).

  That is, by allocating a local area of the capacitor laminate for each individual electronic device mounted on the surface layer of the multilayer printed wiring board, noise generated between the power supply layer and the ground layer is reduced, and About 50% of the capacitors on which the multilayer printed wiring board is mounted are made unnecessary.

  However, as described above, when a capacitor having a limited area is assigned to each electronic device, a dielectric material having a dielectric constant of about 200 is used, and a very thin dielectric having a thickness of only about 12.7 μm is used. Is required.

  Currently, dielectric materials having a dielectric constant of about 200 as described above are not available. Even if it is available, it is impossible to stably manufacture a capacitor laminate including a dielectric having a thickness of 12.7 μm as described above.

  Then, the method of eliminating the said malfunction by the concept of "borrowing capacitance" was proposed (for example, refer patent document 2).

  Here, the concept of the “borrowed capacitance” will be briefly described with reference to FIG. For convenience of explanation, the capacitor laminate, the wiring pattern other than the through-hole connecting the capacitor laminate and the device, the solder resist, and the like are omitted.

  FIG. 4A is a schematic cross-sectional explanatory view of a multilayer printed wiring board Pa in which a conventional capacitor multilayer body 4a is incorporated. The dielectric body 1, the power source layer 2 and the ground layer laminated on the front and back of the dielectric body 1 are shown. 3, a capacitor laminated body 4 a composed of 3, an interlayer insulating layer 6 laminated on the front and back of the capacitor laminated body 4 a, electronic devices 7 a and 7 b mounted on a wiring pattern (not shown) on the interlayer insulating layer 6, The electronic device 7a, 7b is configured to have a through hole 8 for connecting the capacitor laminate 4a and a wiring pattern (not shown).

  FIG. 4C shows an equivalent circuit in a state where the multilayer capacitor 4a and the electronic devices 7a and 7b are connected. In this way, a plurality of electronic devices 7a and 7b are connected to the same capacitor multilayer body 4a. Are connected to different positions (ie, a plurality of electronic devices share the same capacitor), and by utilizing the time difference in operation of the electronic devices 7a and 7b, the capacitance between the devices can be reduced. Borrowing is the concept of “borrowing capacitance”.

  In this way, by adopting the concept of “borrowed capacitance”, the capacitance of the capacitor stack is set to be smaller than the total capacitance required for all electronic devices mounted on the outer layer of the multilayer printed wiring board. Therefore, a dielectric having a thickness generally used (for example, FR-4 having a dielectric constant of about 4) can be used as the dielectric 1, and the above problem can be solved.

  However, in the above concept of “borrowed capacitance”, since a plurality of electronic devices share the same conductor surface of the same capacitor laminate, when the electronic devices are arranged close to each other, During operation, a (minute) fluctuation occurs in the power supply and ground potentials of other electronic devices in the vicinity, which are affected by the fluctuations in the power supply and ground potentials.

  For example, referring to FIG. 4C, when the electronic device 7a is set to start operating first and then the electronic device 7b starts operating, a large voltage is instantaneously absorbed by the electronic device 7a. As a result, the reaction causes the power supply voltage fluctuation during the operation of the electronic device 7b to increase, and as a result, the ground potential becomes difficult to stabilize.

This principle will be briefly described with reference to an enlarged plan view of a main part of the power supply layer 2 shown in FIG. 4B. The connection point between the electronic device 7a and the power supply line is a point A and the electronic device 7b is connected to the power supply line. When the connection point is the point B, the power supply voltage fluctuation 9 generated from the point A is transmitted to the point B linearly, that is, at the shortest distance, so that the influence on the operation of the electronic device 7b is increased. is there.
US Pat. No. 5,010,641 US Pat. No. 5,079,069

  The present invention has been made to solve the above problems, and the object of the present invention is to suppress fluctuations in the ground potential of an electronic device even when a capacitor laminate based on the concept of “borrowed capacitance” is incorporated. An object of the present invention is to provide a multilayer printed wiring board that can be used.

In order to achieve the above object, the present invention according to claim 1 incorporates a capacitor laminate composed of a power supply layer and a ground layer laminated on the front and back of a dielectric, and a plurality of electrons connected to the power supply layer and the ground layer. A multilayer printed wiring board having devices and / or functions, wherein the power supply layer and / or ground layer is completely separated between connection points of electronic devices and / or functions in the power supply layer and / or ground layer. The slit which is not formed is formed.

  Thereby, the influence which the electric potential fluctuation | variation generate | occur | produced at a certain point has on an adjacent certain point can be suppressed.

The present invention according to claim 2 is characterized in that the slit is formed in accordance with the number of electronic devices or functions to be connected.

  As a result, ground potential fluctuation due to power supply voltage fluctuation can be suppressed more efficiently.

Moreover, the present invention according to claim 3 is that the slit is formed by a slit formed by imposition according to the number of electronic devices or functions to be connected and a slit further separating the imposition. Features.

  Thereby, when there are a large number of electronic devices or functions, that is, when there is a need to finely separate the conductor layers, the conductor layers can be efficiently separated.

The present invention according to claim 4 is characterized in that an insulating layer and a conductor layer are alternately stacked above and below a core substrate having the slit.

  Thereby, the multilayer printed wiring board can be thinned.

  By adopting the configuration of the present invention for a multilayer printed wiring board having a built-in capacitor laminate, ground potential fluctuations that affect the operation of the electronic device to be mounted can be effectively and easily suppressed.

  A first embodiment of the present invention will be described with reference to FIG. As in the description of the above prior art, the capacitor laminate, the wiring pattern other than the through-hole connecting the capacitor laminate and the device, the solder resist, and the like are omitted.

  FIG. 1A is a schematic cross-sectional explanatory view of a multilayer printed wiring board P in which a capacitor multilayer body 4 of the present invention is incorporated. The dielectric body 1, a power source layer 2 laminated on the front and back of the dielectric body 1, and a ground A capacitor laminate 4 composed of the layer 3, an interlayer insulation layer 6 laminated on the front and back of the capacitor laminate 4, and electronic devices 7a and 7b mounted on a wiring pattern (not shown) on the interlayer insulation layer 6. The electronic devices 7a and 7b have through holes 8 for connecting the capacitor laminate 4 and a wiring pattern (not shown), and the power supply layer 2 has slits 5 to the extent that the power supply layer 2 is not completely separated. It has a formed configuration.

  FIG. 1C shows an equivalent circuit in a state in which the multilayer capacitor 4 and the electronic devices 7a and 7b are connected. In this way, by providing the power source layer 2 with the slit 5, The influence of voltage fluctuation can be suppressed.

  The above principle will be briefly described with reference to FIG.

  FIG. 1B is an enlarged plan view of a main part of the power supply layer 2, where point A indicates a connection point with the power supply line of the electronic device 7a, and point B indicates a connection point with the power supply line of the electronic device 7b. ing. When the operation order of the electronic devices 7a and 7b is the same as that in the above-described conventional example, when the electronic device 7a starts operating, a large voltage is instantaneously absorbed, and the reaction causes the fluctuation of the power supply voltage when the electronic device 7b operates. However, since the slit 5 is provided between the connection points A and B so that the power supply layer 2 is not completely separated, the power supply voltage fluctuation 9 that has conventionally been transmitted linearly between the points A and B is Since it is transmitted so as to avoid the slit 5, the transmission time to the electronic device 7b side becomes longer. As a result, the influence of the power supply voltage fluctuation on the electronic device 7b can be reduced, and the fluctuation of the ground potential can be suppressed.

  Next, a second embodiment will be described with reference to FIG.

  FIG. 2A shows the slit 5 provided in both the power supply layer 2 and the ground layer 3, and the other configuration is the same as that in FIG. 2B shows an enlarged plan view of the main part of the power supply layer 2 and the ground layer 3 provided with the slits 5, and FIG. 2C shows the multilayer capacitor 4 and the electronic device of FIG. 2A. The equivalent circuit of the state which connected 7a, 7b is shown.

  The operation of the second embodiment will be briefly described. Since the slits 5 are provided in both the power supply layer 2 and the ground layer 3, the ground voltage fluctuation is the same as the power supply voltage fluctuation 9 of the first embodiment. Similarly, since it is transmitted so as to avoid the slit 5, the ground potential can be further stabilized as compared with the first embodiment.

  In the above embodiment, the power supply layer 2 and the ground layer 3 are provided with only one straight slit 5, and the power supply layer and the ground layer are virtually divided into two. The number and form of the slits 5 are not limited to this, and may be a + shape as shown in FIG. 3 (a) or a + shape as shown in FIG. 3 (b), and as shown in FIG. If a plurality of slits 5 shown in FIGS. 3 (a) and 3 (b) are formed and a linear slit separator 5a that further divides the slit 5 is provided, the power supply layer 2 and the ground layer 3 can be further divided finely. It is effective for.

  Further, in the embodiment of the present invention, the description has been given using the four-layer multilayer printed wiring board having one built-in capacitor laminate, but of course, the present invention works effectively even with a larger number of layers. To do.

(A) is schematic sectional explanatory drawing which shows 1st embodiment of the multilayer printed wiring board of this invention, (b) is schematic plan explanatory drawing for demonstrating the transmission track | orbit of the power supply voltage fluctuation | variation, (c) is the equivalent circuit diagram. (A) is schematic sectional explanatory drawing which shows 2nd embodiment of the multilayer printed wiring board of this invention, (b) is schematic planar explanatory drawing for demonstrating the state which provided the slit in both the power supply layer and the ground layer (C) is the equivalent circuit diagram. The schematic plane explanatory drawing which shows the example of a shape of a slit. (A) is schematic sectional explanatory drawing which shows the structure of the conventional multilayer printed wiring board, (b) is a schematic plane explanatory drawing for demonstrating the transmission track | orbit of the power supply voltage fluctuation | variation, (c) is the equivalent price circuit diagram.

Explanation of symbols

1: Dielectric 2: Power layer 3: Ground layer 4, 4a: Capacitor laminate 5: Slit 5a: Slit separator 6: Interlayer insulating layer 7a, 7b: Electronic device 8: Through hole 9: Power supply voltage fluctuation P, Pa: Multilayer printed wiring board

Claims (4)

A multilayer printed wiring board having a plurality of electronic devices and / or functions connected to the power supply layer and the ground layer, including a capacitor laminate composed of a power supply layer and a ground layer laminated on the front and back of the dielectric A multilayer printed wiring, wherein a slit that does not completely separate the power supply layer and / or ground layer is formed between connection points of electronic devices and / or functions in the power supply layer and / or ground layer. Board.   The multilayer printed wiring board according to claim 1, wherein the slit is formed in accordance with the number of electronic devices or functions to be connected.   3. The multilayer according to claim 1, wherein the slit is formed by a slit formed by imposition according to the number of electronic devices or functions to be connected, and a slit further separating the imposition. Printed wiring board.   The multilayer printed wiring board according to any one of claims 1 to 3, wherein an insulating layer and a conductor layer are alternately laminated on the top and bottom of the core substrate provided with the slit.

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