JP2005310895A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board Download PDF

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Publication number
JP2005310895A
JP2005310895A JP2004122966A JP2004122966A JP2005310895A JP 2005310895 A JP2005310895 A JP 2005310895A JP 2004122966 A JP2004122966 A JP 2004122966A JP 2004122966 A JP2004122966 A JP 2004122966A JP 2005310895 A JP2005310895 A JP 2005310895A
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Prior art keywords
electrode
wiring board
layer
circuit pattern
multilayer wiring
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JP2004122966A
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Japanese (ja)
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Masaru Emori
優 江森
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to JP2004122966A priority Critical patent/JP2005310895A/en
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board which can improve the accuracy of capacitor characteristics, by preventing the generation of no stray capacitance. <P>SOLUTION: The multilayer printed wiring board is provided with a capacitor that comprises a first electrode formed in a lower layer of vertically continuous overlapping two layers and a second electrode formed, in parallel with the first electrode inside an upper layer of the two layers with a dielectric in-between. In this case, an interlayer connection conductor from the first electrode is connected to a circuit pattern formed in a layer beneath the lower layer, and an interlayer connection conductor from the second electrode is connected to a circuit pattern formed in the upper layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多層化されたプリント基板などの多層配線板に関する。   The present invention relates to a multilayer wiring board such as a multilayered printed circuit board.

従来、プリント基板上において、抵抗やキャパシタやコイルやICチップなどの回路構成部品を薄い銅線などによって接続し電子回路を構成する技術が存在する。そして近年、プリント基板上の電子回路をより高密度にすることが要求されており、プリント基板を多層化して各層に電子回路を構成し各層をビアなどを用いて結線した多層配線板が多く利用されている。なお、多層配線板の技術として特許文献1が公開されている。
特開平5−235554号公報
2. Description of the Related Art Conventionally, there is a technique for configuring an electronic circuit by connecting circuit components such as a resistor, a capacitor, a coil, and an IC chip on a printed circuit board with a thin copper wire. In recent years, there has been a demand for higher density electronic circuits on printed circuit boards, and multilayer printed circuit boards that use printed circuit boards in multiple layers to form electronic circuits on each layer and connect each layer using vias are often used. Has been. Patent Document 1 is disclosed as a technique of a multilayer wiring board.
JP-A-5-235554

ここで、従来、多層配線板に内蔵されるキャパシタは、図2に示すように2つの絶縁層の上層側の上部電極2が、下層の下の層に形成された回路パターンの接地導体層4にビアなどにより接続され、また下部電極1が上層に形成された回路パターンにビアなどにより接続されている。しかし、図2のようなキャパシタの構成であると、下部電極と接地導体層4との間の電位差によって、当該下部電極1と接地導体層4の間に浮遊容量が発生してしまう。そして、この浮遊容量により内蔵キャパシタの自己共振周波数が低下するという問題があった。特に、絶縁層が薄い場合やその絶縁層の誘電率が高い材質の場合には、浮遊容量の影響が顕著になり、キャパシタの特性劣化が大きくなる。   Here, a conventional capacitor built in a multilayer wiring board has a circuit pattern ground conductor layer 4 in which an upper electrode 2 on the upper side of two insulating layers is formed on a lower layer as shown in FIG. The lower electrode 1 is connected to a circuit pattern formed in the upper layer by a via or the like. However, in the capacitor configuration as shown in FIG. 2, stray capacitance is generated between the lower electrode 1 and the ground conductor layer 4 due to a potential difference between the lower electrode and the ground conductor layer 4. This stray capacitance has a problem that the self-resonant frequency of the built-in capacitor is lowered. In particular, when the insulating layer is thin, or when the insulating layer is made of a material having a high dielectric constant, the effect of stray capacitance becomes significant and the characteristics of the capacitor are greatly deteriorated.

そこでこの発明は、浮遊容量を発生させないことにより、キャパシタ特性の精度を向上させることのできる多層配線板を提供することを目的としている。   Accordingly, an object of the present invention is to provide a multilayer wiring board that can improve the accuracy of capacitor characteristics by not generating stray capacitance.

本発明は、上述の課題を解決すべくなされたもので、多層配線板において上下に連続して重なり合う2つの層の下層に形成された第1電極と、前記2つの層の上層の内部に誘電体を挟んで前記第1電極と平行に形成された第2電極とからなる内蔵キャパシタを備えた多層配線板であって、前記下層の下の層に形成された回路パターンへ、前記第1電極からの層間接続導体を接続し、前記上層に形成された回路パターンへ、前記第2電極からの層間接続導体を接続したことを特徴とする多層配線板である。   The present invention has been made to solve the above-described problems. In the multilayer wiring board, a first electrode formed in the lower layer of two layers that are continuously overlapped in the vertical direction, and a dielectric in the upper layer of the two layers. A multilayer wiring board having a built-in capacitor comprising a second electrode formed in parallel with the first electrode across a body, wherein the first electrode is connected to a circuit pattern formed in a layer below the lower layer The multilayer connection board is characterized in that the interlayer connection conductor from the second electrode is connected to the circuit pattern formed in the upper layer.

本発明によれば、第1電極と多層配線板において上下に連続して重なり合う2つの層の下層の下の層に形成された回路パターンとの間に電位差が生じなくなる。このため、第1電極と多層配線板において上下に連続して重なり合う2つの層の下層の下の層に形成された回路パターンとの間に浮遊容量が発生することが無くなり、自己共振周波数の低減を防止することができる。つまり、容量精度及び周波数特性の良好な内蔵キャパシタを備えた多層配線板を製造することができるという効果が得られる。   According to the present invention, there is no potential difference between the first electrode and the circuit pattern formed in the lower layer of the two lower layers that overlap in the vertical direction in the multilayer wiring board. For this reason, stray capacitance is not generated between the first electrode and the circuit pattern formed in the lower layer of the lower layer of the two layers that continuously overlap each other in the multilayer wiring board, and the self-resonant frequency is reduced. Can be prevented. That is, it is possible to produce a multilayer wiring board having a built-in capacitor with good capacitance accuracy and frequency characteristics.

以下、本発明の一実施形態による多層配線板を図面を参照して説明する。図1は同実施形態の多層配線板の構成を示すブロック図である。この図において、符号1は下部電極である。2は上部電極である。3は誘電体である。4は接地導体層である。5A、5bはビアまたはスルーホール(層間接続導体)である。また6A、6Bは絶縁層である。   Hereinafter, a multilayer wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the multilayer wiring board according to the embodiment. In this figure, reference numeral 1 denotes a lower electrode. Reference numeral 2 denotes an upper electrode. 3 is a dielectric. Reference numeral 4 denotes a ground conductor layer. 5A and 5b are vias or through holes (interlayer connection conductors). Reference numerals 6A and 6B denote insulating layers.

そして、図1の多層配線板は、連続する2つの上下の絶縁層(上層6A、下層6B)を示している。まず、下層の表面に回路パターンと一体の下部電極1が形成されている。また上層の内部に下部電極1と平行して上部電極2が形成されている。なお下部電極1と上部電極2とは誘電体3を挟んで隔てており、また上部電極2には回路パターンが一体化されている。そして、下部電極1と上部電極2と誘電体3で内蔵キャパシタを構成している。   The multilayer wiring board in FIG. 1 shows two continuous upper and lower insulating layers (upper layer 6A and lower layer 6B). First, the lower electrode 1 integrated with the circuit pattern is formed on the surface of the lower layer. An upper electrode 2 is formed in the upper layer in parallel with the lower electrode 1. The lower electrode 1 and the upper electrode 2 are separated from each other with the dielectric 3 interposed therebetween, and a circuit pattern is integrated with the upper electrode 2. The lower electrode 1, the upper electrode 2 and the dielectric 3 constitute a built-in capacitor.

また、図1の多層配線板においては、内蔵キャパシタの上部電極2に一体化された回路パターンは上層に形成された回路パターンとビア5Aを介して接続される。また内蔵キャパシタの下部電極2に一体化された回路パターンは下層の下の層に形成された回路パターンの接地導体層4にビア5Bを介して接続される。   In the multilayer wiring board of FIG. 1, the circuit pattern integrated with the upper electrode 2 of the built-in capacitor is connected to the circuit pattern formed in the upper layer through the via 5A. The circuit pattern integrated with the lower electrode 2 of the built-in capacitor is connected to the ground conductor layer 4 of the circuit pattern formed in the lower layer below via a via 5B.

そして、図1の多層配線板の構成により、内蔵キャパシタの下部電極1と接地導体層4との間は、ビア5Bによって接続されるので、電位差が生じなくなる。このため、下部電極1と接地導体層4との間に浮遊容量が発生することが無くなり、自己共振周波数の低減を防止することができる。つまり、容量精度及び周波数特性の良好な内蔵キャパシタを備える多層配線板を製造することができるようになる。   1, the lower electrode 1 of the built-in capacitor and the ground conductor layer 4 are connected by the via 5B, so that no potential difference occurs. For this reason, stray capacitance is not generated between the lower electrode 1 and the ground conductor layer 4, and the reduction of the self-resonance frequency can be prevented. That is, a multilayer wiring board having a built-in capacitor with good capacitance accuracy and frequency characteristics can be manufactured.

本発明の一実施形態による多層配線板の構成を示す図である。It is a figure which shows the structure of the multilayer wiring board by one Embodiment of this invention. 従来の多層配線板の構成を示す図である。It is a figure which shows the structure of the conventional multilayer wiring board.

符号の説明Explanation of symbols

1・・・下部電極
2・・・上部電極
3・・・誘電体
4・・・接地導体層
5A、5B・・・ビア
6・・・絶縁層
6A・・・絶縁層(上層)
6B・・・絶縁層(下層)
DESCRIPTION OF SYMBOLS 1 ... Lower electrode 2 ... Upper electrode 3 ... Dielectric 4 ... Grounding conductor layer 5A, 5B ... Via 6 ... Insulating layer 6A ... Insulating layer (upper layer)
6B ... Insulating layer (lower layer)

Claims (1)

多層配線板において上下に連続して重なり合う2つの層の下層に形成された第1電極と、
前記2つの層の上層の内部に誘電体を挟んで前記第1電極と平行に形成された第2電極と、
からなる内蔵キャパシタを備える多層配線板であって、
前記下層の下の層に形成された回路パターンへ、前記第1電極からの層間接続導体を接続し、
前記上層に形成された回路パターンへ、前記第2電極からの層間接続導体を接続した
ことを特徴とする多層配線板。
A first electrode formed in a lower layer of two layers that continuously overlap each other in the multilayer wiring board;
A second electrode formed in parallel with the first electrode with a dielectric sandwiched between the upper layers of the two layers;
A multilayer wiring board comprising a built-in capacitor comprising:
An interlayer connection conductor from the first electrode is connected to a circuit pattern formed in a layer below the lower layer,
A multilayer wiring board, wherein an interlayer connection conductor from the second electrode is connected to a circuit pattern formed in the upper layer.
JP2004122966A 2004-04-19 2004-04-19 Multilayer printed wiring board Pending JP2005310895A (en)

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JP2005310895A true JP2005310895A (en) 2005-11-04

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675519B (en) * 2007-05-22 2012-04-18 国际商业机器公司 Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density
JP2015018944A (en) * 2013-07-11 2015-01-29 キヤノン株式会社 Printed circuit board
CN106328339A (en) * 2015-06-30 2017-01-11 株式会社村田制作所 Coil component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332862A (en) * 2000-05-23 2001-11-30 Matsushita Electric Ind Co Ltd Capacitor holding substrate
JP2003234595A (en) * 2003-02-07 2003-08-22 Denso Corp Electromagnetic wave shielded type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332862A (en) * 2000-05-23 2001-11-30 Matsushita Electric Ind Co Ltd Capacitor holding substrate
JP2003234595A (en) * 2003-02-07 2003-08-22 Denso Corp Electromagnetic wave shielded type semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675519B (en) * 2007-05-22 2012-04-18 国际商业机器公司 Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density
JP2015018944A (en) * 2013-07-11 2015-01-29 キヤノン株式会社 Printed circuit board
CN106328339A (en) * 2015-06-30 2017-01-11 株式会社村田制作所 Coil component

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