JP2009111132A - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the inductance components of the power source or grounding circuit of a multilayer wiring board and to provide a structure of a thin multilayer wiring board. <P>SOLUTION: The multilayer wiring board has a strip line for which a wiring conductor 16 is disposed between two conductor layers 8 and 9 in the inside, the wiring conductor 16 and a semiconductor element 11 are connected, and the second conductor layer 10 of the roughly same area as a loading part 11a is provided between the conductor layers 8 and 9 and the wiring conductor 16 right below the loading part 11a of the semiconductor element 11. By providing the second conductor layer 10, the inductance components of a current route connecting the semiconductor element 11 and a connection pad 17 are suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring structure in a multilayer wiring board used for a high-frequency electronic circuit board or the like.

  In recent years, multilayer wiring boards on which electronic elements are mounted are required to have high-frequency transmission characteristics that can handle high-speed signal processing.

  Examples of obstacles to high-speed signal transmission include ringing noise due to reflection due to impedance mismatch, loss due to resistance components of signal wiring, crosstalk noise generated between signal wirings, and the like.

  Another obstacle to high-speed signal transmission is an inductance component of a wiring layer related to power supply or grounding and a through conductor connecting these wiring layers. This inductance component causes switching noise.

  As a structure of a multilayer wiring board that suppresses the inductance component of such a power supply or ground wiring, for example, a structure shown in JP-A-6-163739 has been proposed. FIG. 3 is an exploded perspective view showing the structure.

  In FIG. 3, 21, 22, 24, and 26 are insulators on which the power supply or ground wiring layers 28, 29, 31, and 33 are hatched for easy understanding, and 23 and 25 are on the surface. An insulator 27 in which the wiring groups 30 and 32 are formed is an insulator having a semiconductor element mounting portion 34 on the surface. And these insulators 21-27 are laminated | stacked, and the multilayer wiring board is formed.

  The power supply or ground wiring layers 28, 29, 31, 33 are electrically connected to the other wiring layers 28, 29, 31, 33 by through conductors (not shown). Also in the signal wiring groups 30 and 32, the semiconductor element and the lower surface electrode of the multilayer wiring board are connected by a through conductor (not shown).

In the wiring groups 30 and 32, power supply or ground wiring layers 28, 29, 31, and 33 are disposed above and below the wiring groups 30 and 32, thereby forming a stripline structure. In addition, the self-inductance of the electrode is reduced by ensuring a wide area of the power source or ground wiring layers 28, 29, 31, 33 in each layer.
JP-A-6-163739

  However, there is a problem in that the inductance component may not be sufficiently reduced only by these single-layer power supply or ground wiring layers 28, 29, 31, and 33.

  Further, a vertical current loop is formed in the power source or ground current path for driving the semiconductor element by the through conductors connecting the power source or ground wiring layers 28, 29, 31 and 33. When the inductance component increases in this current path, there is a problem that switching noise occurs.

  The present invention has been made to solve these problems, and an object thereof is to provide a thin multilayer wiring board while suppressing the inductance component of the power supply or ground circuit of the multilayer wiring board.

  The multilayer wiring board of the present invention has a mounting portion on which a semiconductor element is mounted, and internally includes a strip line in which a wiring conductor for electrically connecting the semiconductor element is disposed between two conductor layers. In the multilayer wiring board, at least a part of the conductor layer and the wiring conductor is disposed immediately below the mounting portion of the semiconductor element, and substantially the same as the mounting portion between the conductor layer and the wiring conductor. A second conductor layer having an area is provided, and preferably, the second conductor layer is provided on both upper and lower sides of the wiring conductor, and the wiring conductor has a line width in a formation region of the second conductor layer. It is thin. The conductor layer is connected to a reference potential or a power supply potential.

  According to the multilayer wiring board of the present invention, the strip line having the mounting portion on which the semiconductor element is mounted and the wiring conductor for electrically connecting the semiconductor element between the two conductor layers is disposed inside. In the multilayer wiring board provided, at least a part of the conductor layer and the wiring conductor is disposed immediately below the mounting portion of the semiconductor element, and the first portion having substantially the same area as the mounting portion is disposed between the conductor layer and the wiring conductor. Since the two conductor layers are provided, the power layers for driving the semiconductor elements or the conductor layers constituting the ground circuit are connected in parallel, so that the inductance of the power source or the ground circuit is reduced.

  In addition, when the second conductor layer is provided on both upper and lower sides of the wiring conductor, the power source or ground layer is arranged symmetrically with respect to the wiring conductor, so there is no bias in the spread of the electromagnetic field generated around the wiring conductor. More stable signal transmission is possible.

  Further, when the wiring conductor is formed with a narrow line width in the formation region of the second conductor layer, the second conductor layer can be disposed near the wiring conductor without changing the characteristic impedance of the wiring conductor. Therefore, the thickness of the multilayer wiring board can be reduced.

  Further, when the conductor layer is connected to the reference potential or the power supply potential, it can be a multilayer wiring board in which the layout design of the conductor layer that gives the power supply potential or the reference potential to the mounted semiconductor element is easy.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view of a multilayer wiring board of the present invention on which a semiconductor element is mounted, and FIG. 2 is an exploded perspective view showing the multilayer wiring board of the present invention in an exploded manner.

  In FIGS. 1 and 2, reference numerals 8 and 9 denote conductor layers, and reference numeral 16 denotes a wiring conductor disposed between the two conductor layers 8 and 9. Reference numeral 8 denotes a conductor layer that functions as a ground layer for the wiring conductor 16, and 9 functions as a ground layer for the narrowed portion 16 a of the wiring conductor 16 and supplies driving power to the semiconductor element 11. Alternatively, it is a conductor layer that supplies a ground potential, and this conductor layer is connected to a reference potential that is a power supply potential or a ground potential. The two conductor layers 8 and 9 and the wiring conductor 16 constitute a strip conductor. A second conductor layer 10 having substantially the same area as the mounting portion 11 a is provided between the first conductor layers 8 and 9 and the wiring conductor 16 immediately below the mounting portion 11 a of the semiconductor element 11.

  In FIG. 2, 1 is an insulating layer having a connection pad 17 for external connection on the lower surface, 2 and 6 are insulating layers having a power source or grounding conductor layer 8 and a semiconductor element driving power source or grounding conductor layer 9, 3 and 5 are a plurality of insulating layers having a second conductor layer 10 for power supply or grounding, and 4 is a plurality of wiring conductors 16 and a plurality of receiving pads 15 of through conductors 14 connected to electrodes connected to the semiconductor element 11. An insulating layer having a wiring group 12 including wiring, and 7 is an insulating layer having a mounting portion 11 a of the semiconductor element 11. In FIG. 2, the conductor layers 8, 9, and 10 are hatched for easy understanding. Therefore, they do not show a cross section.

  In addition, the wiring conductor 16 and the conductor layers 8, 9, 10 formed on the insulating layers 1 to 7 are connected to each other by the through conductors 13 and 14. For example, specifically, 13 is a through conductor for driving the semiconductor element 11 that electrically connects the electrode connected to the semiconductor element 11, the conductor layer 9, the second conductor layer 10, and the connection pad 17, and 14 is a wiring conductor. This is a through conductor that electrically connects the receiving pad 15 and the electrodes disposed at both ends of the electrode group connected to the semiconductor element 11 and the wiring conductor 16 and the connection pad 17. The through conductor 14 is not connected to the conductor layer 9 and the second conductor layer 10. For this reason, the portion of the conductor layer 9 and the second conductor layer 10 through which the through conductor 14 penetrates is removed, that is, the conductor layers 9 and 10 are removed in a circular shape or the like so that the through conductor 14 does not contact the conductor layers 9 and 10. The center is penetrated.

  The insulating layers 1 to 7 are laminated by, for example, a ceramic green sheet laminating method to form a laminated body. The laminate is made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Or a composite made by laminating organic insulating materials such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or bonding inorganic insulating powder such as ceramic powder with thermosetting resin such as epoxy resin A multilayer organic resin substrate is formed by laminating an electrical insulating material such as an insulating material.

  The thickness of these insulating layers 1 to 7 satisfies the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications, ease of formation of the through conductor group, etc., depending on the characteristics of the materials used. Set as appropriate.

  The parallel wiring group 12, the conductor layers 8, 9, 10 and the through conductors 13 and 14 are made of metal powder metallization such as tungsten, molybdenum, molybdenum-manganese, copper, silver or silver-palladium, or copper, silver, It consists of nickel, chromium, titanium, gold, niobium or alloys of these metals.

  For example, if it is made of tungsten metal powder metallization, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to the tungsten powder is formed into a predetermined pattern on the ceramic green sheets to be the insulating layers 1-7. The wiring group 12, the conductor layers 8, 9, and 10 and the through conductors 13 and 14 are arranged between the insulating layers 1 to 7 or between the surfaces by printing and applying and firing together with a laminated body of ceramic green sheets. Established. In the case of a thin film of a metal material, a metal layer is formed by, for example, a sputtering method, a vacuum evaporation method, or a plating method, and then formed into a predetermined wiring pattern by a photolithography method.

  In the multilayer wiring board of the present invention, insulating layers 2 and 6 provided with conductor layers 8 and 9 connected to a reference potential serving as a power supply potential or ground are laminated above and below an insulating layer 4 on which a large number of wiring conductors 16 are arranged. Is done. As a result, a high-frequency transmission line having a stripline structure is formed inside, and the insulating layers 3 and 5 are arranged so that the second conductor layer 10 is further disposed between the conductor layers 8 and 9 and the wiring conductor 16. Are stacked simultaneously. The second conductor layer 10 is connected to an upper layer and / or lower layer conductor layer 9 via a through conductor 13 to be a power supply wiring layer or a ground wiring layer for driving the semiconductor element 11, and the through conductor 13 is a semiconductor element. 11 and the connection pad 17 are connected.

  That is, the wiring conductor 16 is connected to the semiconductor element 11 through the through conductor 14 and the receiving pad 15, and the other end is connected to the connection pad 17 to the outside through the through conductor 14. Further, it has a stripline structure in which conductor layers 8 and 9 for power supply or reference potential supply are provided in upper and lower layers, and a wiring conductor 16 is disposed between them.

  In addition, the conductor layer 9 and the second conductor layer 10 are similar to the mounting portion 11a of the semiconductor element 11 in plan view, and include at least a region where the through conductors 13 and 14 are disposed, and are approximately the same as the projection surface of the semiconductor element 11. Is provided in the area.

  Although not shown in FIG. 2, the number of through conductors 13 between the electrode connected to the semiconductor element 11 and the conductor layer 9 is usually the same as the number of electrodes. On the other hand, the number of through conductors 13 between the layers connecting the conductor layer 9 and the second conductor layer 10 is provided more than the number of through conductors 13 between the semiconductor element 11 and the conductor layer 9.

  In order to drive the semiconductor element 11, a power supply potential for driving the semiconductor element 11 and a reference potential for grounding are supplied to the semiconductor element 11 from the multilayer wiring board by the through conductor 13. A vertical current path is formed between the semiconductor element 11 and the connection pad 17. In recent years, the degree of integration of the semiconductor element 11 has increased, and a power supply current or a ground current that varies greatly flows through these current paths in accordance with the switching operation of the semiconductor element 11. In this case, since the inductance component of the current path causes switching noise and affects the operation of the semiconductor element 11, it is necessary to keep the inductance component of the multilayer wiring board low.

  In the multilayer wiring board of the present invention, the second conductor layer 10 is disposed between the wiring conductor 16 and the conductor layer 9. The conductor layer 9 and the second conductor layer 10 are connected by many through conductors 13. Thereby, the conductor layer 9, the second conductor layer 10, and the plurality of through conductors 13 are connected in parallel to each other, and the inductance value can be reduced.

  That is, in the multilayer wiring board of the present invention, by providing the second conductor layer 10, a current flows from the through conductor 13 to the conductor layer 9, and the current spread in the conductor layer 9 passes through the other through conductor 13 to the upper side. Or it flows to the conductor layer 9 or the second conductor layer 10 located on the lower side. In this manner, the vertical current paths that form loops are formed in parallel between the through conductor 13 and the conductor layers 9 and 10 immediately below the semiconductor element 11, thereby reducing the inductance value in these current paths. it can.

  In the multilayer wiring board of the present invention, the wiring conductor 16 includes a portion 16a having a narrow line width in a region where the second conductor layer 10 is formed, that is, in a region where the second conductor layer 10 is projected onto the insulating layer 4. Have. Accordingly, the distance between the second conductor layer 10 and the wiring conductor 16 can be made smaller than the distance between the conductor layer 9 and the wiring conductor 16 without changing the characteristic impedance of the wiring conductor 16. And by adding the 2nd conductor layer 10, since it is not necessary to make the thickness of a board | substrate thick, it can be set as a thin multilayer wiring board.

  The stripline structure is generally formed by a design that maintains a constant characteristic impedance determined by the shape of the wiring conductor 16 and the distance between the wiring conductor 16 and the conductor layers 8 and 9. The width of the wiring conductor 16 is constant, and the second conductor layer 10 is inserted between the conductor layer 9 inside the conductor layer 9 and the wiring conductor 16 so that the distance between the wiring conductor 16 and the second conductor layer 10 is reduced. As a result, the characteristic impedance of the strip line constituted by the wiring conductor 16 and the second conductor layer 10 in the region where the second conductor layer 10 is formed changes. However, according to the multilayer wiring board of the present invention, the second Since the line width of the wiring conductor 16 is reduced in the region overlapping with the conductor layer 10, the second conductor layer 10 can be disposed while suppressing a change in characteristic impedance. As a result, signal reflection due to characteristic impedance mismatch is suppressed, and transmission characteristics with reduced ringing noise can be realized.

  In addition, since the second conductor layer 10 is disposed inside the conductor layer 9 to form a thin multilayer wiring board, the through conductors 13 and 14 do not become long, and the inductance component of the through conductors 13 and 14 does not increase. Therefore, the inductance component due to the through conductors 13 and 14 in the current path can be suppressed. As a result, switching noise caused by the inductance component can be suppressed, and good transmission characteristics can be realized.

  Furthermore, by forming the narrow line width portion 16 a of the wiring conductor 16, more receiving pads 15 can be arranged in the space between the wirings in the narrow line width portion 16 a of the wiring conductor 16. It is possible to cope with an increase in the number of electrodes.

  Although the second conductor layer 10 can suppress the inductance component even if it is provided only on one side above or below the wiring conductor 16, it is more preferable to provide it on both sides above and below. .

  As a result, the number of conductor layers related to the current path is increased as compared with the case of being provided on one side, the inductance component is further suppressed, and the second conductor layer 10 serving as a power supply or ground layer is vertically symmetrical with respect to the wiring conductor 16. Therefore, the spread of the electromagnetic field generated around the wiring conductor 16 is not biased, and more stable signal transmission is possible.

  As described above, according to the present invention, a thin multilayer wiring board in which an inductance component of a power supply or a ground circuit is suppressed can be obtained. Furthermore, by narrowing the line width of the wiring conductor 16 in the region where the second conductor layer 10 is formed and providing the second conductor layer 10 on both the upper and lower sides, there is no mismatch in characteristic impedance, and the characteristic impedance is reduced in the wiring. Thus, a constant multilayer wiring board can be obtained. Thereby, reflection of high-frequency signals for high-speed signal processing can be suppressed, and a multilayer wiring board having good transmission characteristics can be provided.

  In addition, this invention is not limited to the example of the above embodiment, A various change may be added in the range which does not deviate from the summary of this invention. For example, the number of insulating layers 4 provided with the wiring conductors 16 can be further increased to provide a multilayer wiring board in which multiple layers are stacked.

  In the description of the above embodiment, the terms “upper, lower, left and right” are merely used to describe the positional relationship in the drawings, and do not mean the positional relationship in actual use.

It is sectional drawing which shows an example of embodiment of the multilayer wiring board of this invention. It is a disassembled perspective view which shows an example of embodiment of the multilayer wiring board of this invention. It is a disassembled perspective view which shows the example of the conventional multilayer wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1-7: Insulating layer 8,9: Conductor layer 10: 2nd conductor layer 11a: Mount part of a semiconductor element 12: Wiring group including a plurality of wiring conductors 13: Through conductor 14: Through conductor 15: Receiving pad 16: Wiring Conductor 17: Connection pad

Claims (4)

In a multilayer wiring board having a mounting portion on which a semiconductor element is mounted and having a strip line in which a wiring conductor for electrically connecting the semiconductor element is disposed between two conductor layers, the semiconductor At least a part of the conductor layer and the wiring conductor is disposed directly under the element mounting portion, and a second conductor layer having substantially the same area as the mounting portion is provided between the conductor layer and the wiring conductor. A multilayer wiring board characterized by being provided. The multilayer wiring board according to claim 1, wherein the second conductor layer is provided on both upper and lower sides of the wiring conductor. 3. The multilayer wiring board according to claim 1, wherein the wiring conductor has a narrow line width in a region where the second conductor layer is formed. 4. The multilayer wiring board according to claim 1, wherein the conductor layer is connected to a reference potential or a power supply potential.

Images