JP2001007525A - Multilayer interconnection board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer interconnection board, suitable for an electronic circuit board and a package, etc., mounted with an electronic part such as semiconductor devices superior in high frequency property and operating at high speed, in which characteristic impedance Z0 of signal wiring is controlled efficiently by an adjacent wiring conductor in a parallel wiring group laminated alternately, and impedance matching is performed effectively. SOLUTION: A first insulation layer I1 provided with a first parallel wiring group L1 is overlaid with a second insulation layer I2 provided with second parallel wiring group L2 perpendicular to the first parallel wiring group L1, and the first and second parallel wiring groups L1 and L2 are connected electrically to each other with a through conductor group T1, thereby forming a laminated wiring body. In each wiring of the first and second parallel wiring groups L1 and L2, the thickness thereof is made longer than the width in this multilayer interconnection board. Adjacent wirings are bonded more strong than upper and lower wirings to control characteristic impedance of signal wiring efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used for an electronic circuit board or the like, and more particularly to a wiring structure in a multilayer wiring board on which a semiconductor element operating at a high speed is mounted.

[0002]

2. Description of the Related Art Conventionally, in a multilayer wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted and which is used for an electronic circuit board or the like, an insulating material made of ceramics such as alumina is used for forming a wiring conductor for internal wiring. Layers and wiring conductors made of a refractory metal such as tungsten (W) are alternately stacked to form a multilayer wiring board.

In a conventional multilayer wiring board, signal wirings of internal wiring wiring conductors usually have a strip line structure, and a so-called solid pattern is formed above and below wiring conductors formed as signal wirings via insulating layers. A ground (ground) layer or a power supply layer having a wide area of the shape was formed.

Further, with the increase in the speed of electric signals handled by the multilayer wiring board, the insulating layer is replaced with alumina ceramics having a relative dielectric constant of about 10, and a polyimide resin or epoxy resin having a relatively small relative dielectric constant of 3.5 to 5 is used. And a conductive layer for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as a vapor deposition method such as a vapor deposition method or a sputtering method. By forming a wiring conductor in a pattern and multiplying the insulating layer and the wiring conductor into layers, a multilayer wiring board having a high density, a high function and a high speed operation of a semiconductor element has been obtained.

On the other hand, the wiring structure of the internal wiring of the multilayer wiring board is designed to reduce the impedance of the wiring, reduce the crosstalk between signal wirings, etc. A structure has been proposed in which a group of parallel wirings is formed, which is multi-layered, and predetermined wirings in the wiring group of each layer are electrically connected to each other via through conductors such as via conductors and through-hole conductors.

For example, Japanese Unexamined Patent Publication No. 63-129655 discloses a first conductive layer including a plurality of first signal lines extending in a first direction and first power lines alternately arranged with the first signal lines. 1
And a second conductor layer including a second signal line extending in a second direction intersecting with the second direction and a second power line alternately arranged with the second signal line are alternately stacked with the insulating layer, and a corresponding voltage is applied. A multilayer wiring structure is disclosed in which first and second receiving power lines are interconnected. According to this, it is possible to increase the integration density, reduce the power consumption, and increase the operation speed by effectively utilizing the chip area of the semiconductor chip to be mounted.

Japanese Patent Application Laid-Open No. 1-96953 discloses that each set includes at least a first and a second wiring surface, and each wiring surface is disposed at an intersection of a conductive wiring and an orthogonal line facing the main wiring direction. And a wiring structure having a plurality of sets of wiring surfaces, each having a plurality of connection portions, wherein a main wiring direction of a first wiring surface forms an acute angle with a main wiring direction of a second wiring surface. I have.
According to this, the length of the wiring can be shortened and optimized or minimized by using one or several sets of standardized wiring surfaces.

In Japanese Patent Application Laid-Open No. 5-343601, a conductor (wiring conductor) layer having two or less parallel conductor patterns is laminated so that conductor patterns are orthogonal to each other. There is disclosed a connection system for an integrated circuit in which conductors of a conductor layer are connected to each other so that signal conductors are used for signals and the rest are used for power supplies, and the signal conductors are shielded from each other by a power supply conductor. According to this, since the conductor conductor grid is formed so as to sandwich the signal pattern between the pair of power supply patterns, the interval between the signal patterns can be reduced, and the signal patterns can be formed longer in parallel. The surface is effectively used, and the crosstalk is reduced and the S / N ratio is improved.

Further, Japanese Patent Application Laid-Open No. 7-94666 discloses that at least a first and a second interconnect layer are formed, each of the interconnect layers is composed of a plurality of parallel conductive regions.
The conductive regions of the interconnect layer are arranged orthogonal to the conductive regions of the first interconnect layer, and the conductive regions of the first and second interconnect layers have at least two conductive planes. Essentially interconnected with each interconnect layer, such that each conductive plane appears on both interconnect layers, and furthermore, the selected conductive areas form at least one signal circuit. An electrical interconnect medium is disclosed that is electrically interconnected so as to be electrically isolated from one conductive plane. According to this, without losing the advantages of low inductance power distribution, which is characteristic of parallel power and ground planes, and high wiring density of signal interconnect wiring, which is characteristic of optical lithography manufacturing technology.
It is an interconnection medium having a reduced number of interconnections.

Further, Japanese Patent Application Laid-Open No. 9-18156 discloses a first signal wiring section, a first power supply wiring section, and a plurality of first signal wiring sections.
A first layer having a first ground wiring section, a second signal wiring section, a second power supply wiring section, and a plurality of second grounds respectively connected to the plurality of first ground wiring sections in the first layer. A first signal wiring portion in the first layer and a second signal wiring portion in the second layer are in twist positions, that is, A multi-layer printed wiring board at orthogonal positions is disclosed. According to this, the total number of wiring layers can be reduced, and the combined conductance value and the combined resistance value can be controlled to be low even if the wiring width of the ground wiring portion is narrowed. This makes it possible to reduce noise on the transmission signal. Also, noise due to the characteristic impedance of the signal wiring portion can be suppressed by the shielding effect of the ground wiring portion and the power supply wiring portion, and since the first signal wiring portion and the second signal wiring portion are located at twisted positions. In addition, it is possible to control the influence of crosstalk noise generated by electromagnetic coupling and electrostatic coupling between two signal wiring portions.

In the multilayer wiring board having the parallel wiring groups as described above, electronic components such as semiconductor elements mounted on the multilayer wiring board are electrically connected to a mounting board on which the multilayer wiring board is mounted. For this purpose, an appropriate wiring is selected from each parallel wiring group in the multilayer wiring board, and the connection between the wirings between different wiring layers is made via a through conductor such as a via conductor.

[0012]

In a multilayer wiring board having a group of parallel wirings orthogonal to each other as described above, the cross-sectional shape of each wiring conductor usually has a length in the vertical direction, that is, a thickness in the horizontal direction. That is, it is a so-called horizontally long shape smaller than the width.

Further, in the multilayer wiring board having the orthogonal parallel wiring groups, the matching of the characteristic impedance Z ₀ of the signal wiring conductor (signal wiring) with the wiring conductor adjacent thereto in each wiring group is performed. It is controlled by the wiring interval, that is, the gap, and adjusted to a desired value.

However, the characteristic impedance Z of the signal wiring is caused by the gap between the adjacent wiring conductors.
_In the case of controlling ₀ , since the width of the wiring conductor is large between the wiring conductors whose normal cross sections are horizontally long, the area where the wiring conductors of the wiring groups located above and below the wiring group face each other is large. to be those susceptible to their influence, resulting in a problem to be solved that the control of the characteristic impedance Z ₀ by the adjacent wiring conductors to each other is difficult.

The present invention has been devised in view of the above problems, and has as its object to control the characteristic impedance Z ₀ of signal wiring by adjacent wiring conductors in a wiring group of parallel wiring groups alternately stacked. Multilayer wiring board suitable for an electronic circuit board or package on which electronic components such as a semiconductor element or the like that operates at a high speed and have excellent high frequency characteristics can be efficiently performed and impedance matching can be effectively performed. Is to provide.

[0016]

According to the present invention, there is provided a multilayer wiring board comprising a second parallel wiring group orthogonal to the first parallel wiring group on a first insulating layer having the first parallel wiring group. A first insulating layer having a first insulating layer, a first insulating layer, a first insulating layer, and a second insulating layer. Each group of wires is characterized in that its thickness is greater than its width.

In the multilayer wiring board according to the present invention, each of the first and second parallel wiring groups has a thickness 1.1 to 2 times the width of the wiring. It is characterized by having.

Further, in the multilayer wiring board according to the present invention, in each of the above structures, the first and second parallel wiring groups each include a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring. It is characterized by having.

According to the multilayer circuit board of the present invention, the thickness of each wiring of the parallel wiring group is made larger than the width and the horizontal length in the cross-sectional shape is made shorter than the vertical length. In the parallel wiring group, the area where the adjacent wirings face each other increases, so that the characteristic impedance Z ₀ can be controlled more efficiently, and the area of the upper or lower parallel wiring group that faces the wiring decreases. Since these are hardly affected, the coupling between the adjacent wirings can be made larger than the coupling between the upper and lower wirings, and the characteristic impedance Z ₀ of the signal wiring by the adjacent wirings in the wiring group can be reduced. Matching can be performed efficiently and effectively.

Thus, according to the multilayer wiring board of the present invention, the characteristic impedance Z ₀ of the signal wiring can be efficiently controlled by the adjacent wiring conductor, and the impedance matching can be effectively performed. The present invention is suitable for an electronic circuit board, a package, or the like on which electronic components such as a semiconductor element that operates at high speed and have excellent characteristics are mounted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

FIG. 1 is an exploded plan view showing an example of an embodiment of a multilayer wiring body according to the multilayer wiring board of the present invention. FIG. 1A shows a first insulating layer, and FIG. Of the insulating layer,
(C) has shown the top view of the 3rd insulating layer, respectively.
FIG. 2 is a cross-sectional view showing an example of an embodiment of the multilayer wiring board of the present invention including a multilayer wiring body obtained by laminating them.

In these figures, I1 and I2 are first and second insulating layers, respectively, and L1 and L2
T1 represents a first and second parallel wiring group disposed substantially in parallel on the upper surfaces of the first and second insulating layers I1 and I2, respectively,
Is a through conductor group that electrically connects the first parallel wiring group L1 and the second parallel wiring group L2 at predetermined locations. These constitute a multilayer wiring body according to the multilayer wiring board of the present invention. I3 is a third insulating layer laminated on the second insulating layer I2, and I4 is a fourth insulating layer laminated on the third insulating layer I3, which is a surface layer of the multilayer wiring board. L3 is formed on the third insulating layer I3, and the through conductor group T
3 is a third wiring layer electrically connected to the second parallel wiring group L2 through the second wiring layer L2. Here, an example is shown in which a parallel wiring group similar to the first and second parallel wiring groups L1 and L2 is formed.

P1 to P3 are power supply wirings in the first to third parallel wiring groups L1 to L3, respectively, G1 to G3 are ground wirings in the first to third parallel wiring groups L1 to L3, respectively.
S3 indicates a signal wiring in the first to third parallel wiring groups L1 to L3, respectively.

As described above, in the multilayer wiring body of the multilayer wiring board of the present invention, the first parallel wiring group L1 is wired substantially parallel to the first direction, and the second parallel wiring stacked thereon is stacked. The group L2 is disposed substantially parallel to a second direction orthogonal to the first direction, and these wirings are electrically connected by a through conductor group T1 penetrating the second insulating layer I2, It constitutes a laminated wiring body. Further, the third parallel wiring group L3 stacked on the second parallel wiring group L2 is disposed in a direction orthogonal to the second direction, that is, substantially parallel to the first direction. The wiring is electrically connected by a through conductor group T2 penetrating the third insulating layer I3 to form a laminated wiring body.

According to such a laminated wiring body, the first parallel wiring group L1 and the second parallel wiring group L2, and the second parallel wiring group L2 and the third parallel wiring group L3, respectively. Since they are stacked so as to be orthogonal to each other, it is possible to reduce and minimize the crosstalk noise between the wirings of the parallel wiring groups L1 and L2 and between the wirings of L2 and L3.

The plurality of signal wirings S1 to S3 arranged on the same plane may transmit different signals, respectively, and the plurality of power supply wirings P1 to P3 arranged on the same plane may be used.
It goes without saying that P3 may supply different powers.

The fourth insulating layer I4 serving as the surface layer of the multi-layer wiring board is formed as needed, for example, a third insulating layer I4.
In the case where the wiring group L3 is disposed in the third insulating layer I3, it is not always necessary to form the wiring group L3.

Such a multilayer wiring board has, for example, an MPU (Micro Processing Unit) / ASIC on its surface.
(Application Specific Integrated Circuit) DS
A semiconductor element such as a P (Digital Signal Processor) is mounted. These semiconductor elements are mounted on the surface of this multilayer wiring board by, for example, so-called bump electrodes,
Alternatively, it is attached to the mounting portion with an adhesive, brazing material, or the like, and is electrically connected to the third parallel wiring group L3 or the like via a bonding wire or the like.

The through conductor groups T1 and T2 are formed by the respective insulating layers I2 and T2.
The upper and lower wirings are electrically connected to each other by penetrating I3. Usually, through-hole conductors, via conductors, or the like are used, and are formed at locations required for connection. A similar through conductor group is also used for electrically connecting the wiring of each parallel wiring group to an external connection terminal or the like attached to the surface of a semiconductor element or a multilayer wiring board.

According to the multilayer wiring board of the present invention,
In each of the parallel wiring groups L1 to L3, the thickness, that is, the length in the vertical direction in the cross section is larger than the width, that is, the length in the horizontal direction in the cross section. By making the thickness of each wiring larger than the width in this way, the coupling between adjacent wirings in the same parallel wiring group is increased, and the characteristic impedance Z ₀ can be controlled more efficiently. since the binding of the wiring of the parallel line group under becomes less susceptible to these effects is reduced, the matching of the characteristic impedance Z ₀ of the signal lines by the adjacent wirings in the wiring group efficiently and effectively Can be performed.

When the thickness of the wiring is made larger than the width in the multilayer wiring board of the present invention, the ratio of the thickness to the width is in the range of 1.1: 1 to 2: 1, that is, the thickness is larger than the width. The size is preferably 1.1 times to 2 times, and more preferably, the ratio of thickness to width is in the range of 1.2: 1 to 1.7: 1,
That is, the thickness may be 1.2 to 1.7 times the width. By setting as described above, it is possible to obtain a sufficient adhesion strength between the insulating layers while having the above-described effects. Further, when the thickness of the wiring exceeds twice the width, it tends to be difficult to form a wiring having a stable cross-sectional shape by, for example, a thick film printing method.

In the multilayer wiring board of the present invention,
A multilayer wiring board can be formed by stacking multilayer wiring portions having various wiring structures above and below the multilayer wiring body. For example,
Similar to the multilayer wiring body, the wiring structure of the parallel wiring group stacked orthogonally, the wiring structure of the strip line structure, and the microstrip line structure, the coplanar line structure, etc., to the specifications required for the multilayer wiring board It can be appropriately selected and used depending on the situation.

Further, for example, an electronic circuit may be formed by laminating a polyimide insulating layer and a conductor layer formed by copper vapor deposition. Further, a package for semiconductor element accommodation may be configured by attaching a chip resistor, a thin film resistor, a coil inductor, a cross capacitor, a chip capacitor, and an electrolytic capacitor.

The shape of each insulating layer including the first to third insulating layers I1 to I3 is not limited to a substantially square shape as shown, but may be a rectangular shape, a rhombic shape, a polygonal shape, or the like. It may be a shape such as a shape.

The first to third parallel wiring groups L1 to L3
Is not limited to those formed on the surfaces of the first to third insulating layers I1 to I3, and may be formed inside the respective insulating layers I1 to I3.

In the case where the third parallel wiring group L3 is formed inside the third insulating layer I3 with respect to the example shown in FIGS. 1 and 2, the fourth insulating layer I4 is not necessarily required. Will not be.

In the multi-layer wiring board of the present invention, each of the insulating layers including the first to third insulating layers I1 to I3 is formed by, for example, a ceramic green sheet laminating method using an aluminum oxide sintered body or an aluminum nitride sintered body. Using inorganic insulating materials such as sintered body, silicon carbide sintered body, silicon nitride sintered body, mullite sintered body, glass ceramics, or polyimide, epoxy resin, fluororesin, polynorbornene, benzocyclobutene Or an electric insulating material such as a composite insulating material formed by bonding an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin.

When these insulating layers are made of, for example, a sintered body of aluminum oxide, a suitable organic binder, a solvent and the like are added to a raw material powder such as aluminum oxide, silicon oxide, calcium oxide and magnesium oxide. A ceramic green sheet is obtained by forming the sheet into a sheet shape by employing a well-known doctor blade method, and thereafter, the ceramic green sheet is subjected to an appropriate punching process, and each of the parallel wiring groups is formed. In addition, a metal paste to be used as a through-hole conductor group and a conductor layer is printed and applied in a predetermined pattern, and is laminated on top and bottom. Finally, the laminate is fired at a temperature of about 1600 ° C. in a reducing atmosphere.

The thickness of these insulating layers is determined so as to satisfy the requirements such as mechanical strength and electrical characteristics corresponding to the required specifications and ease of forming the through conductor group according to the characteristics of the material used. It is set appropriately.

The first to third parallel wiring groups L1 to L3
And the through conductor groups T1 and T2 are made of metal powder such as tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, or copper, silver, nickel, chromium, titanium, gold, niobium or alloys thereof. And the like.

For example, in the case of metallization of metal powder of tungsten, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to the tungsten powder is printed in a predetermined pattern on a ceramic green sheet serving as an insulating layer. By applying and firing this together with the ceramic green sheet laminate, it is disposed on the upper surface of each insulating layer.

At this time, in order to make each wiring have a cross-sectional shape of a desired thickness and width, for example, a plurality of printing applications or a printing application using a metal paste having an increased viscosity may be performed.

In the case of a thin film of a metal material, a metal layer having a desired thickness is formed by, for example, a sputtering method, a vacuum evaporation method or a plating method, and then a wiring pattern having a predetermined width is formed by a photolithography method. do it.

The first to third parallel wiring groups L1 to L3
The thickness and width of each wiring of L3 and the spacing between the wirings are
Depending on the properties of the material used, also desired characteristic impedance Z ₀ become so in consideration, easiness conditions of arrangement of the electrical characteristics and insulating layer I1~I3 corresponding to required specifications Is set appropriately so as to satisfy the following.

Each of the through conductors of the through conductor groups T1 and T2 may have a rectangular cross section other than a circular cross section, a rectangle such as an ellipse, a square or a rectangle, or any other shape. The position and size are appropriately set according to the characteristics of the material to be used, so as to satisfy conditions such as electrical characteristics corresponding to required specifications and easiness of formation and arrangement on the insulating layer.

For example, when a sintered body of aluminum oxide is used for the insulating layer and a metallization of tungsten is used for the parallel wiring group, the thickness of the insulating layer is set to 200 μm.
Wiring thickness 15μm, line width 100μm, spacing between wiring
By setting 100 μm and the size of the through conductor to 100 μm, the impedance of the signal wiring is set to 50Ω, and the coupling between adjacent wirings is increased while suppressing the influence of the coupling between the upper and lower parallel wiring groups. The characteristic impedance Z ₀ of the signal wiring can be controlled between them to adjust it to a desired value.

It should be noted that the present invention is not limited to the above-described embodiments, and that various changes may be made without departing from the spirit of the present invention. For example, in the above embodiment, the present invention has been described as a multilayer wiring board on which a semiconductor element is mounted. However, the present invention may be applied to a semiconductor element housing package for housing a semiconductor element. Alternatively, an aluminum nitride-based sintered body / silicon carbide-based sintered body considering heat dissipation or a glass-ceramic-based sintered body considering low dielectric constant may be used.

[0049]

According to the multilayer circuit board of the present invention, since the thickness of each wiring of the parallel wiring group is made larger than the width, the coupling between adjacent wirings in the same parallel wiring group is increased, and The characteristic impedance Z ₀ can be controlled more efficiently, and the coupling with the wiring of the upper or lower parallel wiring group is suppressed to be less affected by the wiring. , The matching of the characteristic impedance Z ₀ of the signal wiring can be performed efficiently and effectively.

Thus, according to the multilayer wiring board of the present invention, the characteristic impedance Z of the signal wiring is determined by the adjacent wiring conductors in the wiring group of the parallel wiring group alternately stacked.
₀ can be controlled efficiently and impedance matching can be performed effectively. It has excellent high-frequency characteristics and is suitable for electronic circuit boards and packages, etc., on which electronic components such as semiconductor elements that operate at high speed are mounted. A multilayer wiring board could be provided.

[Brief description of the drawings]

FIGS. 1A to 1C are a first insulating layer, a second insulating layer, and a third insulating layer, each showing an example of an embodiment of a multilayer wiring body according to the multilayer wiring board of the present invention; FIG.

FIG. 2 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention including the multilayer wiring body shown in FIG.

[Explanation of symbols]

 ... I1 to I4... Insulating layer L1 to L3... Parallel wiring group P1 to P3... Power wiring G1 to G3. ... Groups of through conductors

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Yoshihiro Nabe 1-1, Yamashita-cho, Kokubu-shi, Kagoshima F-term in Kyocera Corporation Kagoshima Kokubu Plant (reference) 5E346 AA43 BB02 BB03 BB04 BB07 BB12 BB15 BB17 FF22 GG15 HH03

Claims (3)

[Claims] 1. A second insulating layer having a second parallel wiring group orthogonal to the first parallel wiring group is laminated on a first insulating layer having a first parallel wiring group. 1st and 2nd
Of the first and second parallel wiring groups, wherein the thickness of each wiring of the first and second parallel wiring groups is larger than the width. A multilayer wiring board characterized by the above-mentioned. 2. The multilayer according to claim 1, wherein each of the first and second parallel wiring groups has a thickness 1.1 to 2 times the width thereof. Wiring board. 3. The first and second parallel wiring groups each include a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring.
Or the multilayer wiring board according to claim 2.